1 /*
2  *  include/linux/mmc/sdio.h
3  *
4  *  Copyright 2006-2007 Pierre Ossman
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or (at
9  * your option) any later version.
10  */
11 
12 #ifndef LINUX_MMC_SDIO_H
13 #define LINUX_MMC_SDIO_H
14 
15 /* SDIO commands                         type  argument     response */
16 #define SD_IO_SEND_OP_COND          5 /* bcr  [23:0] OCR         R4  */
17 #define SD_IO_RW_DIRECT            52 /* ac   [31:0] See below   R5  */
18 #define SD_IO_RW_EXTENDED          53 /* adtc [31:0] See below   R5  */
19 
20 /*
21  * SD_IO_RW_DIRECT argument format:
22  *
23  *      [31] R/W flag
24  *      [30:28] Function number
25  *      [27] RAW flag
26  *      [25:9] Register address
27  *      [7:0] Data
28  */
29 
30 /*
31  * SD_IO_RW_EXTENDED argument format:
32  *
33  *      [31] R/W flag
34  *      [30:28] Function number
35  *      [27] Block mode
36  *      [26] Increment address
37  *      [25:9] Register address
38  *      [8:0] Byte/block count
39  */
40 
41 #define R4_18V_PRESENT (1<<24)
42 #define R4_MEMORY_PRESENT (1 << 27)
43 
44 /*
45   SDIO status in R5
46   Type
47 	e : error bit
48 	s : status bit
49 	r : detected and set for the actual command response
50 	x : detected and set during command execution. the host must poll
51             the card by sending status command in order to read these bits.
52   Clear condition
53 	a : according to the card state
54 	b : always related to the previous command. Reception of
55             a valid command will clear it (with a delay of one command)
56 	c : clear by read
57  */
58 
59 #define R5_COM_CRC_ERROR	(1 << 15)	/* er, b */
60 #define R5_ILLEGAL_COMMAND	(1 << 14)	/* er, b */
61 #define R5_ERROR		(1 << 11)	/* erx, c */
62 #define R5_FUNCTION_NUMBER	(1 << 9)	/* er, c */
63 #define R5_OUT_OF_RANGE		(1 << 8)	/* er, c */
64 #define R5_STATUS(x)		(x & 0xCB00)
65 #define R5_IO_CURRENT_STATE(x)	((x & 0x3000) >> 12) /* s, b */
66 
67 /*
68  * Card Common Control Registers (CCCR)
69  */
70 
71 #define SDIO_CCCR_CCCR		0x00
72 
73 #define  SDIO_CCCR_REV_1_00	0	/* CCCR/FBR Version 1.00 */
74 #define  SDIO_CCCR_REV_1_10	1	/* CCCR/FBR Version 1.10 */
75 #define  SDIO_CCCR_REV_1_20	2	/* CCCR/FBR Version 1.20 */
76 #define  SDIO_CCCR_REV_3_00	3	/* CCCR/FBR Version 3.00 */
77 
78 #define  SDIO_SDIO_REV_1_00	0	/* SDIO Spec Version 1.00 */
79 #define  SDIO_SDIO_REV_1_10	1	/* SDIO Spec Version 1.10 */
80 #define  SDIO_SDIO_REV_1_20	2	/* SDIO Spec Version 1.20 */
81 #define  SDIO_SDIO_REV_2_00	3	/* SDIO Spec Version 2.00 */
82 #define  SDIO_SDIO_REV_3_00	4	/* SDIO Spec Version 3.00 */
83 
84 #define SDIO_CCCR_SD		0x01
85 
86 #define  SDIO_SD_REV_1_01	0	/* SD Physical Spec Version 1.01 */
87 #define  SDIO_SD_REV_1_10	1	/* SD Physical Spec Version 1.10 */
88 #define  SDIO_SD_REV_2_00	2	/* SD Physical Spec Version 2.00 */
89 #define  SDIO_SD_REV_3_00	3	/* SD Physical Spev Version 3.00 */
90 
91 #define SDIO_CCCR_IOEx		0x02
92 #define SDIO_CCCR_IORx		0x03
93 
94 #define SDIO_CCCR_IENx		0x04	/* Function/Master Interrupt Enable */
95 #define SDIO_CCCR_INTx		0x05	/* Function Interrupt Pending */
96 
97 #define SDIO_CCCR_ABORT		0x06	/* function abort/card reset */
98 
99 #define SDIO_CCCR_IF		0x07	/* bus interface controls */
100 
101 #define  SDIO_BUS_WIDTH_MASK	0x03	/* data bus width setting */
102 #define  SDIO_BUS_WIDTH_1BIT	0x00
103 #define  SDIO_BUS_WIDTH_RESERVED 0x01
104 #define  SDIO_BUS_WIDTH_4BIT	0x02
105 #define  SDIO_BUS_ECSI		0x20	/* Enable continuous SPI interrupt */
106 #define  SDIO_BUS_SCSI		0x40	/* Support continuous SPI interrupt */
107 
108 #define  SDIO_BUS_ASYNC_INT	0x20
109 
110 #define  SDIO_BUS_CD_DISABLE     0x80	/* disable pull-up on DAT3 (pin 1) */
111 
112 #define SDIO_CCCR_CAPS		0x08
113 
114 #define  SDIO_CCCR_CAP_SDC	0x01	/* can do CMD52 while data transfer */
115 #define  SDIO_CCCR_CAP_SMB	0x02	/* can do multi-block xfers (CMD53) */
116 #define  SDIO_CCCR_CAP_SRW	0x04	/* supports read-wait protocol */
117 #define  SDIO_CCCR_CAP_SBS	0x08	/* supports suspend/resume */
118 #define  SDIO_CCCR_CAP_S4MI	0x10	/* interrupt during 4-bit CMD53 */
119 #define  SDIO_CCCR_CAP_E4MI	0x20	/* enable ints during 4-bit CMD53 */
120 #define  SDIO_CCCR_CAP_LSC	0x40	/* low speed card */
121 #define  SDIO_CCCR_CAP_4BLS	0x80	/* 4 bit low speed card */
122 
123 #define SDIO_CCCR_CIS		0x09	/* common CIS pointer (3 bytes) */
124 
125 /* Following 4 regs are valid only if SBS is set */
126 #define SDIO_CCCR_SUSPEND	0x0c
127 #define SDIO_CCCR_SELx		0x0d
128 #define SDIO_CCCR_EXECx		0x0e
129 #define SDIO_CCCR_READYx	0x0f
130 
131 #define SDIO_CCCR_BLKSIZE	0x10
132 
133 #define SDIO_CCCR_POWER		0x12
134 
135 #define  SDIO_POWER_SMPC	0x01	/* Supports Master Power Control */
136 #define  SDIO_POWER_EMPC	0x02	/* Enable Master Power Control */
137 
138 #define SDIO_CCCR_SPEED		0x13
139 
140 #define  SDIO_SPEED_SHS		0x01	/* Supports High-Speed mode */
141 #define  SDIO_SPEED_BSS_SHIFT	1
142 #define  SDIO_SPEED_BSS_MASK	(7<<SDIO_SPEED_BSS_SHIFT)
143 #define  SDIO_SPEED_SDR12	(0<<SDIO_SPEED_BSS_SHIFT)
144 #define  SDIO_SPEED_SDR25	(1<<SDIO_SPEED_BSS_SHIFT)
145 #define  SDIO_SPEED_SDR50	(2<<SDIO_SPEED_BSS_SHIFT)
146 #define  SDIO_SPEED_SDR104	(3<<SDIO_SPEED_BSS_SHIFT)
147 #define  SDIO_SPEED_DDR50	(4<<SDIO_SPEED_BSS_SHIFT)
148 #define  SDIO_SPEED_EHS		SDIO_SPEED_SDR25	/* Enable High-Speed */
149 
150 #define SDIO_CCCR_UHS		0x14
151 #define  SDIO_UHS_SDR50		0x01
152 #define  SDIO_UHS_SDR104	0x02
153 #define  SDIO_UHS_DDR50		0x04
154 
155 #define SDIO_CCCR_DRIVE_STRENGTH 0x15
156 #define  SDIO_SDTx_MASK		0x07
157 #define  SDIO_DRIVE_SDTA	(1<<0)
158 #define  SDIO_DRIVE_SDTC	(1<<1)
159 #define  SDIO_DRIVE_SDTD	(1<<2)
160 #define  SDIO_DRIVE_DTSx_MASK	0x03
161 #define  SDIO_DRIVE_DTSx_SHIFT	4
162 #define  SDIO_DTSx_SET_TYPE_B	(0 << SDIO_DRIVE_DTSx_SHIFT)
163 #define  SDIO_DTSx_SET_TYPE_A	(1 << SDIO_DRIVE_DTSx_SHIFT)
164 #define  SDIO_DTSx_SET_TYPE_C	(2 << SDIO_DRIVE_DTSx_SHIFT)
165 #define  SDIO_DTSx_SET_TYPE_D	(3 << SDIO_DRIVE_DTSx_SHIFT)
166 /*
167  * Function Basic Registers (FBR)
168  */
169 
170 #define SDIO_FBR_BASE(f)	((f) * 0x100) /* base of function f's FBRs */
171 
172 #define SDIO_FBR_STD_IF		0x00
173 
174 #define  SDIO_FBR_SUPPORTS_CSA	0x40	/* supports Code Storage Area */
175 #define  SDIO_FBR_ENABLE_CSA	0x80	/* enable Code Storage Area */
176 
177 #define SDIO_FBR_STD_IF_EXT	0x01
178 
179 #define SDIO_FBR_POWER		0x02
180 
181 #define  SDIO_FBR_POWER_SPS	0x01	/* Supports Power Selection */
182 #define  SDIO_FBR_POWER_EPS	0x02	/* Enable (low) Power Selection */
183 
184 #define SDIO_FBR_CIS		0x09	/* CIS pointer (3 bytes) */
185 
186 
187 #define SDIO_FBR_CSA		0x0C	/* CSA pointer (3 bytes) */
188 
189 #define SDIO_FBR_CSA_DATA	0x0F
190 
191 #define SDIO_FBR_BLKSIZE	0x10	/* block size (2 bytes) */
192 
193 #endif /* LINUX_MMC_SDIO_H */
194