1 /*
2  * sm5502.h
3  *
4  * Copyright (c) 2014 Samsung Electronics Co., Ltd
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11 
12 #ifndef __LINUX_EXTCON_SM5502_H
13 #define __LINUX_EXTCON_SM5502_H
14 
15 enum sm5502_types {
16 	TYPE_SM5502,
17 };
18 
19 /* SM5502 registers */
20 enum sm5502_reg {
21 	SM5502_REG_DEVICE_ID = 0x01,
22 	SM5502_REG_CONTROL,
23 	SM5502_REG_INT1,
24 	SM5502_REG_INT2,
25 	SM5502_REG_INTMASK1,
26 	SM5502_REG_INTMASK2,
27 	SM5502_REG_ADC,
28 	SM5502_REG_TIMING_SET1,
29 	SM5502_REG_TIMING_SET2,
30 	SM5502_REG_DEV_TYPE1,
31 	SM5502_REG_DEV_TYPE2,
32 	SM5502_REG_BUTTON1,
33 	SM5502_REG_BUTTON2,
34 	SM5502_REG_CAR_KIT_STATUS,
35 	SM5502_REG_RSVD1,
36 	SM5502_REG_RSVD2,
37 	SM5502_REG_RSVD3,
38 	SM5502_REG_RSVD4,
39 	SM5502_REG_MANUAL_SW1,
40 	SM5502_REG_MANUAL_SW2,
41 	SM5502_REG_DEV_TYPE3,
42 	SM5502_REG_RSVD5,
43 	SM5502_REG_RSVD6,
44 	SM5502_REG_RSVD7,
45 	SM5502_REG_RSVD8,
46 	SM5502_REG_RSVD9,
47 	SM5502_REG_RESET,
48 	SM5502_REG_RSVD10,
49 	SM5502_REG_RESERVED_ID1,
50 	SM5502_REG_RSVD11,
51 	SM5502_REG_RSVD12,
52 	SM5502_REG_RESERVED_ID2,
53 	SM5502_REG_RSVD13,
54 	SM5502_REG_OCP,
55 	SM5502_REG_RSVD14,
56 	SM5502_REG_RSVD15,
57 	SM5502_REG_RSVD16,
58 	SM5502_REG_RSVD17,
59 	SM5502_REG_RSVD18,
60 	SM5502_REG_RSVD19,
61 	SM5502_REG_RSVD20,
62 	SM5502_REG_RSVD21,
63 	SM5502_REG_RSVD22,
64 	SM5502_REG_RSVD23,
65 	SM5502_REG_RSVD24,
66 	SM5502_REG_RSVD25,
67 	SM5502_REG_RSVD26,
68 	SM5502_REG_RSVD27,
69 	SM5502_REG_RSVD28,
70 	SM5502_REG_RSVD29,
71 	SM5502_REG_RSVD30,
72 	SM5502_REG_RSVD31,
73 	SM5502_REG_RSVD32,
74 	SM5502_REG_RSVD33,
75 	SM5502_REG_RSVD34,
76 	SM5502_REG_RSVD35,
77 	SM5502_REG_RSVD36,
78 	SM5502_REG_RESERVED_ID3,
79 
80 	SM5502_REG_END,
81 };
82 
83 /* Define SM5502 MASK/SHIFT constant */
84 #define SM5502_REG_DEVICE_ID_VENDOR_SHIFT	0
85 #define SM5502_REG_DEVICE_ID_VERSION_SHIFT	3
86 #define SM5502_REG_DEVICE_ID_VENDOR_MASK	(0x3 << SM5502_REG_DEVICE_ID_VENDOR_SHIFT)
87 #define SM5502_REG_DEVICE_ID_VERSION_MASK	(0x1f << SM5502_REG_DEVICE_ID_VERSION_SHIFT)
88 
89 #define SM5502_REG_CONTROL_MASK_INT_SHIFT	0
90 #define SM5502_REG_CONTROL_WAIT_SHIFT		1
91 #define SM5502_REG_CONTROL_MANUAL_SW_SHIFT	2
92 #define SM5502_REG_CONTROL_RAW_DATA_SHIFT	3
93 #define SM5502_REG_CONTROL_SW_OPEN_SHIFT	4
94 #define SM5502_REG_CONTROL_MASK_INT_MASK	(0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT)
95 #define SM5502_REG_CONTROL_WAIT_MASK		(0x1 << SM5502_REG_CONTROL_WAIT_SHIFT)
96 #define SM5502_REG_CONTROL_MANUAL_SW_MASK	(0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT)
97 #define SM5502_REG_CONTROL_RAW_DATA_MASK	(0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
98 #define SM5502_REG_CONTROL_SW_OPEN_MASK		(0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
99 
100 #define SM5502_REG_INTM1_ATTACH_SHIFT		0
101 #define SM5502_REG_INTM1_DETACH_SHIFT		1
102 #define SM5502_REG_INTM1_KP_SHIFT		2
103 #define SM5502_REG_INTM1_LKP_SHIFT		3
104 #define SM5502_REG_INTM1_LKR_SHIFT		4
105 #define SM5502_REG_INTM1_OVP_EVENT_SHIFT	5
106 #define SM5502_REG_INTM1_OCP_EVENT_SHIFT	6
107 #define SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT	7
108 #define SM5502_REG_INTM1_ATTACH_MASK		(0x1 << SM5502_REG_INTM1_ATTACH_SHIFT)
109 #define SM5502_REG_INTM1_DETACH_MASK		(0x1 << SM5502_REG_INTM1_DETACH_SHIFT)
110 #define SM5502_REG_INTM1_KP_MASK		(0x1 << SM5502_REG_INTM1_KP_SHIFT)
111 #define SM5502_REG_INTM1_LKP_MASK		(0x1 << SM5502_REG_INTM1_LKP_SHIFT)
112 #define SM5502_REG_INTM1_LKR_MASK		(0x1 << SM5502_REG_INTM1_LKR_SHIFT)
113 #define SM5502_REG_INTM1_OVP_EVENT_MASK		(0x1 << SM5502_REG_INTM1_OVP_EVENT_SHIFT)
114 #define SM5502_REG_INTM1_OCP_EVENT_MASK		(0x1 << SM5502_REG_INTM1_OCP_EVENT_SHIFT)
115 #define SM5502_REG_INTM1_OVP_OCP_DIS_MASK	(0x1 << SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT)
116 
117 #define SM5502_REG_INTM2_VBUS_DET_SHIFT		0
118 #define SM5502_REG_INTM2_REV_ACCE_SHIFT		1
119 #define SM5502_REG_INTM2_ADC_CHG_SHIFT		2
120 #define SM5502_REG_INTM2_STUCK_KEY_SHIFT	3
121 #define SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT	4
122 #define SM5502_REG_INTM2_MHL_SHIFT		5
123 #define SM5502_REG_INTM2_VBUS_DET_MASK		(0x1 << SM5502_REG_INTM2_VBUS_DET_SHIFT)
124 #define SM5502_REG_INTM2_REV_ACCE_MASK		(0x1 << SM5502_REG_INTM2_REV_ACCE_SHIFT)
125 #define SM5502_REG_INTM2_ADC_CHG_MASK		(0x1 << SM5502_REG_INTM2_ADC_CHG_SHIFT)
126 #define SM5502_REG_INTM2_STUCK_KEY_MASK		(0x1 << SM5502_REG_INTM2_STUCK_KEY_SHIFT)
127 #define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK	(0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT)
128 #define SM5502_REG_INTM2_MHL_MASK		(0x1 << SM5502_REG_INTM2_MHL_SHIFT)
129 
130 #define SM5502_REG_ADC_SHIFT			0
131 #define SM5502_REG_ADC_MASK			(0x1f << SM5502_REG_ADC_SHIFT)
132 
133 #define SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT	4
134 #define SM5502_REG_TIMING_SET1_KEY_PRESS_MASK	(0xf << SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT)
135 #define TIMING_KEY_PRESS_100MS			0x0
136 #define TIMING_KEY_PRESS_200MS			0x1
137 #define TIMING_KEY_PRESS_300MS			0x2
138 #define TIMING_KEY_PRESS_400MS			0x3
139 #define TIMING_KEY_PRESS_500MS			0x4
140 #define TIMING_KEY_PRESS_600MS			0x5
141 #define TIMING_KEY_PRESS_700MS			0x6
142 #define TIMING_KEY_PRESS_800MS			0x7
143 #define TIMING_KEY_PRESS_900MS			0x8
144 #define TIMING_KEY_PRESS_1000MS			0x9
145 #define SM5502_REG_TIMING_SET1_ADC_DET_SHIFT	0
146 #define SM5502_REG_TIMING_SET1_ADC_DET_MASK	(0xf << SM5502_REG_TIMING_SET1_ADC_DET_SHIFT)
147 #define TIMING_ADC_DET_50MS			0x0
148 #define TIMING_ADC_DET_100MS			0x1
149 #define TIMING_ADC_DET_150MS			0x2
150 #define TIMING_ADC_DET_200MS			0x3
151 #define TIMING_ADC_DET_300MS			0x4
152 #define TIMING_ADC_DET_400MS			0x5
153 #define TIMING_ADC_DET_500MS			0x6
154 #define TIMING_ADC_DET_600MS			0x7
155 #define TIMING_ADC_DET_700MS			0x8
156 #define TIMING_ADC_DET_800MS			0x9
157 #define TIMING_ADC_DET_900MS			0xA
158 #define TIMING_ADC_DET_1000MS			0xB
159 
160 #define SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT	4
161 #define SM5502_REG_TIMING_SET2_SW_WAIT_MASK	(0xf << SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT)
162 #define TIMING_SW_WAIT_10MS			0x0
163 #define TIMING_SW_WAIT_30MS			0x1
164 #define TIMING_SW_WAIT_50MS			0x2
165 #define TIMING_SW_WAIT_70MS			0x3
166 #define TIMING_SW_WAIT_90MS			0x4
167 #define TIMING_SW_WAIT_110MS			0x5
168 #define TIMING_SW_WAIT_130MS			0x6
169 #define TIMING_SW_WAIT_150MS			0x7
170 #define TIMING_SW_WAIT_170MS			0x8
171 #define TIMING_SW_WAIT_190MS			0x9
172 #define TIMING_SW_WAIT_210MS			0xA
173 #define SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT	0
174 #define SM5502_REG_TIMING_SET2_LONG_KEY_MASK	(0xf << SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT)
175 #define TIMING_LONG_KEY_300MS			0x0
176 #define TIMING_LONG_KEY_400MS			0x1
177 #define TIMING_LONG_KEY_500MS			0x2
178 #define TIMING_LONG_KEY_600MS			0x3
179 #define TIMING_LONG_KEY_700MS			0x4
180 #define TIMING_LONG_KEY_800MS			0x5
181 #define TIMING_LONG_KEY_900MS			0x6
182 #define TIMING_LONG_KEY_1000MS			0x7
183 #define TIMING_LONG_KEY_1100MS			0x8
184 #define TIMING_LONG_KEY_1200MS			0x9
185 #define TIMING_LONG_KEY_1300MS			0xA
186 #define TIMING_LONG_KEY_1400MS			0xB
187 #define TIMING_LONG_KEY_1500MS			0xC
188 
189 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT		0
190 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT		1
191 #define SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT		2
192 #define SM5502_REG_DEV_TYPE1_UART_SHIFT			3
193 #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT	4
194 #define SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT		5
195 #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT	6
196 #define SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT		7
197 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_MASK		(0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT)
198 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1__MASK		(0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT)
199 #define SM5502_REG_DEV_TYPE1_USB_SDP_MASK		(0x1 << SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT)
200 #define SM5502_REG_DEV_TYPE1_UART_MASK			(0x1 << SM5502_REG_DEV_TYPE1_UART_SHIFT)
201 #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_MASK	(0x1 << SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT)
202 #define SM5502_REG_DEV_TYPE1_USB_CHG_MASK		(0x1 << SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT)
203 #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK		(0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT)
204 #define SM5502_REG_DEV_TYPE1_USB_OTG_MASK		(0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT)
205 
206 #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT		0
207 #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT		1
208 #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT		2
209 #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT		3
210 #define SM5502_REG_DEV_TYPE2_PPD_SHIFT			4
211 #define SM5502_REG_DEV_TYPE2_TTY_SHIFT			5
212 #define SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT		6
213 #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT)
214 #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT)
215 #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT)
216 #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT)
217 #define SM5502_REG_DEV_TYPE2_PPD_MASK			(0x1 << SM5502_REG_DEV_TYPE2_PPD_SHIFT)
218 #define SM5502_REG_DEV_TYPE2_TTY_MASK			(0x1 << SM5502_REG_DEV_TYPE2_TTY_SHIFT)
219 #define SM5502_REG_DEV_TYPE2_AV_CABLE_MASK		(0x1 << SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT)
220 
221 #define SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT	0
222 #define SM5502_REG_MANUAL_SW1_DP_SHIFT		2
223 #define SM5502_REG_MANUAL_SW1_DM_SHIFT		5
224 #define SM5502_REG_MANUAL_SW1_VBUSIN_MASK	(0x3 << SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT)
225 #define SM5502_REG_MANUAL_SW1_DP_MASK		(0x7 << SM5502_REG_MANUAL_SW1_DP_SHIFT)
226 #define SM5502_REG_MANUAL_SW1_DM_MASK		(0x7 << SM5502_REG_MANUAL_SW1_DM_SHIFT)
227 #define VBUSIN_SWITCH_OPEN			0x0
228 #define VBUSIN_SWITCH_VBUSOUT			0x1
229 #define VBUSIN_SWITCH_MIC			0x2
230 #define VBUSIN_SWITCH_VBUSOUT_WITH_USB		0x3
231 #define DM_DP_CON_SWITCH_OPEN			0x0
232 #define DM_DP_CON_SWITCH_USB			0x1
233 #define DM_DP_CON_SWITCH_AUDIO			0x2
234 #define DM_DP_CON_SWITCH_UART			0x3
235 #define DM_DP_SWITCH_OPEN			((DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
236 						| (DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
237 #define DM_DP_SWITCH_USB			((DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
238 						| (DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
239 #define DM_DP_SWITCH_AUDIO			((DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
240 						| (DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
241 #define DM_DP_SWITCH_UART			((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
242 						| (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
243 
244 #define SM5502_REG_RESET_MASK			(0x1)
245 
246 /* SM5502 Interrupts */
247 enum sm5502_irq {
248 	/* INT1 */
249 	SM5502_IRQ_INT1_ATTACH,
250 	SM5502_IRQ_INT1_DETACH,
251 	SM5502_IRQ_INT1_KP,
252 	SM5502_IRQ_INT1_LKP,
253 	SM5502_IRQ_INT1_LKR,
254 	SM5502_IRQ_INT1_OVP_EVENT,
255 	SM5502_IRQ_INT1_OCP_EVENT,
256 	SM5502_IRQ_INT1_OVP_OCP_DIS,
257 
258 	/* INT2 */
259 	SM5502_IRQ_INT2_VBUS_DET,
260 	SM5502_IRQ_INT2_REV_ACCE,
261 	SM5502_IRQ_INT2_ADC_CHG,
262 	SM5502_IRQ_INT2_STUCK_KEY,
263 	SM5502_IRQ_INT2_STUCK_KEY_RCV,
264 	SM5502_IRQ_INT2_MHL,
265 
266 	SM5502_IRQ_NUM,
267 };
268 
269 #define SM5502_IRQ_INT1_ATTACH_MASK		BIT(0)
270 #define SM5502_IRQ_INT1_DETACH_MASK		BIT(1)
271 #define SM5502_IRQ_INT1_KP_MASK			BIT(2)
272 #define SM5502_IRQ_INT1_LKP_MASK		BIT(3)
273 #define SM5502_IRQ_INT1_LKR_MASK		BIT(4)
274 #define SM5502_IRQ_INT1_OVP_EVENT_MASK		BIT(5)
275 #define SM5502_IRQ_INT1_OCP_EVENT_MASK		BIT(6)
276 #define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK	BIT(7)
277 #define SM5502_IRQ_INT2_VBUS_DET_MASK		BIT(0)
278 #define SM5502_IRQ_INT2_REV_ACCE_MASK		BIT(1)
279 #define SM5502_IRQ_INT2_ADC_CHG_MASK		BIT(2)
280 #define SM5502_IRQ_INT2_STUCK_KEY_MASK		BIT(3)
281 #define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK	BIT(4)
282 #define SM5502_IRQ_INT2_MHL_MASK		BIT(5)
283 
284 #endif /*  __LINUX_EXTCON_SM5502_H */
285