1 /*
2 * Copyright (C) 2008 Marvell International Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/init.h>
14 #include <linux/cpufreq.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17
18 #include <mach/generic.h>
19 #include <mach/pxa3xx-regs.h>
20
21 #define HSS_104M (0)
22 #define HSS_156M (1)
23 #define HSS_208M (2)
24 #define HSS_312M (3)
25
26 #define SMCFS_78M (0)
27 #define SMCFS_104M (2)
28 #define SMCFS_208M (5)
29
30 #define SFLFS_104M (0)
31 #define SFLFS_156M (1)
32 #define SFLFS_208M (2)
33 #define SFLFS_312M (3)
34
35 #define XSPCLK_156M (0)
36 #define XSPCLK_NONE (3)
37
38 #define DMCFS_26M (0)
39 #define DMCFS_260M (3)
40
41 struct pxa3xx_freq_info {
42 unsigned int cpufreq_mhz;
43 unsigned int core_xl : 5;
44 unsigned int core_xn : 3;
45 unsigned int hss : 2;
46 unsigned int dmcfs : 2;
47 unsigned int smcfs : 3;
48 unsigned int sflfs : 2;
49 unsigned int df_clkdiv : 3;
50
51 int vcc_core; /* in mV */
52 int vcc_sram; /* in mV */
53 };
54
55 #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
56 { \
57 .cpufreq_mhz = cpufreq, \
58 .core_xl = _xl, \
59 .core_xn = _xn, \
60 .hss = HSS_##_hss##M, \
61 .dmcfs = DMCFS_##_dmc##M, \
62 .smcfs = SMCFS_##_smc##M, \
63 .sflfs = SFLFS_##_sfl##M, \
64 .df_clkdiv = _dfi, \
65 .vcc_core = vcore, \
66 .vcc_sram = vsram, \
67 }
68
69 static struct pxa3xx_freq_info pxa300_freqs[] = {
70 /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
71 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
72 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
73 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
74 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
75 };
76
77 static struct pxa3xx_freq_info pxa320_freqs[] = {
78 /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
79 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
80 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
81 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
82 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
83 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
84 };
85
86 static unsigned int pxa3xx_freqs_num;
87 static struct pxa3xx_freq_info *pxa3xx_freqs;
88 static struct cpufreq_frequency_table *pxa3xx_freqs_table;
89
setup_freqs_table(struct cpufreq_policy * policy,struct pxa3xx_freq_info * freqs,int num)90 static int setup_freqs_table(struct cpufreq_policy *policy,
91 struct pxa3xx_freq_info *freqs, int num)
92 {
93 struct cpufreq_frequency_table *table;
94 int i;
95
96 table = kcalloc(num + 1, sizeof(*table), GFP_KERNEL);
97 if (table == NULL)
98 return -ENOMEM;
99
100 for (i = 0; i < num; i++) {
101 table[i].driver_data = i;
102 table[i].frequency = freqs[i].cpufreq_mhz * 1000;
103 }
104 table[num].driver_data = i;
105 table[num].frequency = CPUFREQ_TABLE_END;
106
107 pxa3xx_freqs = freqs;
108 pxa3xx_freqs_num = num;
109 pxa3xx_freqs_table = table;
110
111 policy->freq_table = table;
112
113 return 0;
114 }
115
__update_core_freq(struct pxa3xx_freq_info * info)116 static void __update_core_freq(struct pxa3xx_freq_info *info)
117 {
118 uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
119 uint32_t accr = ACCR;
120 uint32_t xclkcfg;
121
122 accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
123 accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
124
125 /* No clock until core PLL is re-locked */
126 accr |= ACCR_XSPCLK(XSPCLK_NONE);
127
128 xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */
129
130 ACCR = accr;
131 __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
132
133 while ((ACSR & mask) != (accr & mask))
134 cpu_relax();
135 }
136
__update_bus_freq(struct pxa3xx_freq_info * info)137 static void __update_bus_freq(struct pxa3xx_freq_info *info)
138 {
139 uint32_t mask;
140 uint32_t accr = ACCR;
141
142 mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
143 ACCR_DMCFS_MASK;
144
145 accr &= ~mask;
146 accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
147 ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
148
149 ACCR = accr;
150
151 while ((ACSR & mask) != (accr & mask))
152 cpu_relax();
153 }
154
pxa3xx_cpufreq_get(unsigned int cpu)155 static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
156 {
157 return pxa3xx_get_clk_frequency_khz(0);
158 }
159
pxa3xx_cpufreq_set(struct cpufreq_policy * policy,unsigned int index)160 static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy, unsigned int index)
161 {
162 struct pxa3xx_freq_info *next;
163 unsigned long flags;
164
165 if (policy->cpu != 0)
166 return -EINVAL;
167
168 next = &pxa3xx_freqs[index];
169
170 local_irq_save(flags);
171 __update_core_freq(next);
172 __update_bus_freq(next);
173 local_irq_restore(flags);
174
175 return 0;
176 }
177
pxa3xx_cpufreq_init(struct cpufreq_policy * policy)178 static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
179 {
180 int ret = -EINVAL;
181
182 /* set default policy and cpuinfo */
183 policy->min = policy->cpuinfo.min_freq = 104000;
184 policy->max = policy->cpuinfo.max_freq =
185 (cpu_is_pxa320()) ? 806000 : 624000;
186 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
187
188 if (cpu_is_pxa300() || cpu_is_pxa310())
189 ret = setup_freqs_table(policy, pxa300_freqs,
190 ARRAY_SIZE(pxa300_freqs));
191
192 if (cpu_is_pxa320())
193 ret = setup_freqs_table(policy, pxa320_freqs,
194 ARRAY_SIZE(pxa320_freqs));
195
196 if (ret) {
197 pr_err("failed to setup frequency table\n");
198 return ret;
199 }
200
201 pr_info("CPUFREQ support for PXA3xx initialized\n");
202 return 0;
203 }
204
205 static struct cpufreq_driver pxa3xx_cpufreq_driver = {
206 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
207 .verify = cpufreq_generic_frequency_table_verify,
208 .target_index = pxa3xx_cpufreq_set,
209 .init = pxa3xx_cpufreq_init,
210 .get = pxa3xx_cpufreq_get,
211 .name = "pxa3xx-cpufreq",
212 };
213
cpufreq_init(void)214 static int __init cpufreq_init(void)
215 {
216 if (cpu_is_pxa3xx())
217 return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
218
219 return 0;
220 }
221 module_init(cpufreq_init);
222
cpufreq_exit(void)223 static void __exit cpufreq_exit(void)
224 {
225 cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
226 }
227 module_exit(cpufreq_exit);
228
229 MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
230 MODULE_LICENSE("GPL");
231