Searched refs:SOCFPGA_PLL_DIVQ_MASK (Results 1 – 2 of 2) sorted by relevance
34 #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 macro55 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
38 #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 macro62 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()