1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Xing Zheng <zhengxing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 18 19 /* core clocks */ 20 #define PLL_APLLL 1 21 #define PLL_APLLB 2 22 #define PLL_DPLL 3 23 #define PLL_CPLL 4 24 #define PLL_GPLL 5 25 #define PLL_NPLL 6 26 #define PLL_VPLL 7 27 #define ARMCLKL 8 28 #define ARMCLKB 9 29 30 /* sclk gates (special clocks) */ 31 #define SCLK_I2C1 65 32 #define SCLK_I2C2 66 33 #define SCLK_I2C3 67 34 #define SCLK_I2C5 68 35 #define SCLK_I2C6 69 36 #define SCLK_I2C7 70 37 #define SCLK_SPI0 71 38 #define SCLK_SPI1 72 39 #define SCLK_SPI2 73 40 #define SCLK_SPI4 74 41 #define SCLK_SPI5 75 42 #define SCLK_SDMMC 76 43 #define SCLK_SDIO 77 44 #define SCLK_EMMC 78 45 #define SCLK_TSADC 79 46 #define SCLK_SARADC 80 47 #define SCLK_UART0 81 48 #define SCLK_UART1 82 49 #define SCLK_UART2 83 50 #define SCLK_UART3 84 51 #define SCLK_SPDIF_8CH 85 52 #define SCLK_I2S0_8CH 86 53 #define SCLK_I2S1_8CH 87 54 #define SCLK_I2S2_8CH 88 55 #define SCLK_I2S_8CH_OUT 89 56 #define SCLK_TIMER00 90 57 #define SCLK_TIMER01 91 58 #define SCLK_TIMER02 92 59 #define SCLK_TIMER03 93 60 #define SCLK_TIMER04 94 61 #define SCLK_TIMER05 95 62 #define SCLK_TIMER06 96 63 #define SCLK_TIMER07 97 64 #define SCLK_TIMER08 98 65 #define SCLK_TIMER09 99 66 #define SCLK_TIMER10 100 67 #define SCLK_TIMER11 101 68 #define SCLK_MACREF 102 69 #define SCLK_MAC_RX 103 70 #define SCLK_MAC_TX 104 71 #define SCLK_MAC 105 72 #define SCLK_MACREF_OUT 106 73 #define SCLK_VOP0_PWM 107 74 #define SCLK_VOP1_PWM 108 75 #define SCLK_RGA_CORE 109 76 #define SCLK_ISP0 110 77 #define SCLK_ISP1 111 78 #define SCLK_HDMI_CEC 112 79 #define SCLK_HDMI_SFR 113 80 #define SCLK_DP_CORE 114 81 #define SCLK_PVTM_CORE_L 115 82 #define SCLK_PVTM_CORE_B 116 83 #define SCLK_PVTM_GPU 117 84 #define SCLK_PVTM_DDR 118 85 #define SCLK_MIPIDPHY_REF 119 86 #define SCLK_MIPIDPHY_CFG 120 87 #define SCLK_HSICPHY 121 88 #define SCLK_USBPHY480M 122 89 #define SCLK_USB2PHY0_REF 123 90 #define SCLK_USB2PHY1_REF 124 91 #define SCLK_UPHY0_TCPDPHY_REF 125 92 #define SCLK_UPHY0_TCPDCORE 126 93 #define SCLK_UPHY1_TCPDPHY_REF 127 94 #define SCLK_UPHY1_TCPDCORE 128 95 #define SCLK_USB3OTG0_REF 129 96 #define SCLK_USB3OTG1_REF 130 97 #define SCLK_USB3OTG0_SUSPEND 131 98 #define SCLK_USB3OTG1_SUSPEND 132 99 #define SCLK_CRYPTO0 133 100 #define SCLK_CRYPTO1 134 101 #define SCLK_CCI_TRACE 135 102 #define SCLK_CS 136 103 #define SCLK_CIF_OUT 137 104 #define SCLK_PCIEPHY_REF 138 105 #define SCLK_PCIE_CORE 139 106 #define SCLK_M0_PERILP 140 107 #define SCLK_M0_PERILP_DEC 141 108 #define SCLK_CM0S 142 109 #define SCLK_DBG_NOC 143 110 #define SCLK_DBG_PD_CORE_B 144 111 #define SCLK_DBG_PD_CORE_L 145 112 #define SCLK_DFIMON0_TIMER 146 113 #define SCLK_DFIMON1_TIMER 147 114 #define SCLK_INTMEM0 148 115 #define SCLK_INTMEM1 149 116 #define SCLK_INTMEM2 150 117 #define SCLK_INTMEM3 151 118 #define SCLK_INTMEM4 152 119 #define SCLK_INTMEM5 153 120 #define SCLK_SDMMC_DRV 154 121 #define SCLK_SDMMC_SAMPLE 155 122 #define SCLK_SDIO_DRV 156 123 #define SCLK_SDIO_SAMPLE 157 124 #define SCLK_VDU_CORE 158 125 #define SCLK_VDU_CA 159 126 #define SCLK_PCIE_PM 160 127 #define SCLK_SPDIF_REC_DPTX 161 128 #define SCLK_DPHY_PLL 162 129 #define SCLK_DPHY_TX0_CFG 163 130 #define SCLK_DPHY_TX1RX1_CFG 164 131 #define SCLK_DPHY_RX0_CFG 165 132 #define SCLK_RMII_SRC 166 133 #define SCLK_PCIEPHY_REF100M 167 134 #define SCLK_DDRC 168 135 #define SCLK_TESTCLKOUT1 169 136 #define SCLK_TESTCLKOUT2 170 137 138 #define DCLK_VOP0 180 139 #define DCLK_VOP1 181 140 #define DCLK_VOP0_DIV 182 141 #define DCLK_VOP1_DIV 183 142 #define DCLK_M0_PERILP 184 143 #define DCLK_VOP0_FRAC 185 144 #define DCLK_VOP1_FRAC 186 145 146 #define FCLK_CM0S 190 147 148 /* aclk gates */ 149 #define ACLK_PERIHP 192 150 #define ACLK_PERIHP_NOC 193 151 #define ACLK_PERILP0 194 152 #define ACLK_PERILP0_NOC 195 153 #define ACLK_PERF_PCIE 196 154 #define ACLK_PCIE 197 155 #define ACLK_INTMEM 198 156 #define ACLK_TZMA 199 157 #define ACLK_DCF 200 158 #define ACLK_CCI 201 159 #define ACLK_CCI_NOC0 202 160 #define ACLK_CCI_NOC1 203 161 #define ACLK_CCI_GRF 204 162 #define ACLK_CENTER 205 163 #define ACLK_CENTER_MAIN_NOC 206 164 #define ACLK_CENTER_PERI_NOC 207 165 #define ACLK_GPU 208 166 #define ACLK_PERF_GPU 209 167 #define ACLK_GPU_GRF 210 168 #define ACLK_DMAC0_PERILP 211 169 #define ACLK_DMAC1_PERILP 212 170 #define ACLK_GMAC 213 171 #define ACLK_GMAC_NOC 214 172 #define ACLK_PERF_GMAC 215 173 #define ACLK_VOP0_NOC 216 174 #define ACLK_VOP0 217 175 #define ACLK_VOP1_NOC 218 176 #define ACLK_VOP1 219 177 #define ACLK_RGA 220 178 #define ACLK_RGA_NOC 221 179 #define ACLK_HDCP 222 180 #define ACLK_HDCP_NOC 223 181 #define ACLK_HDCP22 224 182 #define ACLK_IEP 225 183 #define ACLK_IEP_NOC 226 184 #define ACLK_VIO 227 185 #define ACLK_VIO_NOC 228 186 #define ACLK_ISP0 229 187 #define ACLK_ISP1 230 188 #define ACLK_ISP0_NOC 231 189 #define ACLK_ISP1_NOC 232 190 #define ACLK_ISP0_WRAPPER 233 191 #define ACLK_ISP1_WRAPPER 234 192 #define ACLK_VCODEC 235 193 #define ACLK_VCODEC_NOC 236 194 #define ACLK_VDU 237 195 #define ACLK_VDU_NOC 238 196 #define ACLK_PERI 239 197 #define ACLK_EMMC 240 198 #define ACLK_EMMC_CORE 241 199 #define ACLK_EMMC_NOC 242 200 #define ACLK_EMMC_GRF 243 201 #define ACLK_USB3 244 202 #define ACLK_USB3_NOC 245 203 #define ACLK_USB3OTG0 246 204 #define ACLK_USB3OTG1 247 205 #define ACLK_USB3_RKSOC_AXI_PERF 248 206 #define ACLK_USB3_GRF 249 207 #define ACLK_GIC 250 208 #define ACLK_GIC_NOC 251 209 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252 210 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253 211 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254 212 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255 213 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 214 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 215 #define ACLK_ADB400M_PD_CORE_L 258 216 #define ACLK_ADB400M_PD_CORE_B 259 217 #define ACLK_PERF_CORE_L 260 218 #define ACLK_PERF_CORE_B 261 219 #define ACLK_GIC_PRE 262 220 #define ACLK_VOP0_PRE 263 221 #define ACLK_VOP1_PRE 264 222 223 /* pclk gates */ 224 #define PCLK_PERIHP 320 225 #define PCLK_PERIHP_NOC 321 226 #define PCLK_PERILP0 322 227 #define PCLK_PERILP1 323 228 #define PCLK_PERILP1_NOC 324 229 #define PCLK_PERILP_SGRF 325 230 #define PCLK_PERIHP_GRF 326 231 #define PCLK_PCIE 327 232 #define PCLK_SGRF 328 233 #define PCLK_INTR_ARB 329 234 #define PCLK_CENTER_MAIN_NOC 330 235 #define PCLK_CIC 331 236 #define PCLK_COREDBG_B 332 237 #define PCLK_COREDBG_L 333 238 #define PCLK_DBG_CXCS_PD_CORE_B 334 239 #define PCLK_DCF 335 240 #define PCLK_GPIO2 336 241 #define PCLK_GPIO3 337 242 #define PCLK_GPIO4 338 243 #define PCLK_GRF 339 244 #define PCLK_HSICPHY 340 245 #define PCLK_I2C1 341 246 #define PCLK_I2C2 342 247 #define PCLK_I2C3 343 248 #define PCLK_I2C5 344 249 #define PCLK_I2C6 345 250 #define PCLK_I2C7 346 251 #define PCLK_SPI0 347 252 #define PCLK_SPI1 348 253 #define PCLK_SPI2 349 254 #define PCLK_SPI4 350 255 #define PCLK_SPI5 351 256 #define PCLK_UART0 352 257 #define PCLK_UART1 353 258 #define PCLK_UART2 354 259 #define PCLK_UART3 355 260 #define PCLK_TSADC 356 261 #define PCLK_SARADC 357 262 #define PCLK_GMAC 358 263 #define PCLK_GMAC_NOC 359 264 #define PCLK_TIMER0 360 265 #define PCLK_TIMER1 361 266 #define PCLK_EDP 362 267 #define PCLK_EDP_NOC 363 268 #define PCLK_EDP_CTRL 364 269 #define PCLK_VIO 365 270 #define PCLK_VIO_NOC 366 271 #define PCLK_VIO_GRF 367 272 #define PCLK_MIPI_DSI0 368 273 #define PCLK_MIPI_DSI1 369 274 #define PCLK_HDCP 370 275 #define PCLK_HDCP_NOC 371 276 #define PCLK_HDMI_CTRL 372 277 #define PCLK_DP_CTRL 373 278 #define PCLK_HDCP22 374 279 #define PCLK_GASKET 375 280 #define PCLK_DDR 376 281 #define PCLK_DDR_MON 377 282 #define PCLK_DDR_SGRF 378 283 #define PCLK_ISP1_WRAPPER 379 284 #define PCLK_WDT 380 285 #define PCLK_EFUSE1024NS 381 286 #define PCLK_EFUSE1024S 382 287 #define PCLK_PMU_INTR_ARB 383 288 #define PCLK_MAILBOX0 384 289 #define PCLK_USBPHY_MUX_G 385 290 #define PCLK_UPHY0_TCPHY_G 386 291 #define PCLK_UPHY0_TCPD_G 387 292 #define PCLK_UPHY1_TCPHY_G 388 293 #define PCLK_UPHY1_TCPD_G 389 294 #define PCLK_ALIVE 390 295 296 /* hclk gates */ 297 #define HCLK_PERIHP 448 298 #define HCLK_PERILP0 449 299 #define HCLK_PERILP1 450 300 #define HCLK_PERILP0_NOC 451 301 #define HCLK_PERILP1_NOC 452 302 #define HCLK_M0_PERILP 453 303 #define HCLK_M0_PERILP_NOC 454 304 #define HCLK_AHB1TOM 455 305 #define HCLK_HOST0 456 306 #define HCLK_HOST0_ARB 457 307 #define HCLK_HOST1 458 308 #define HCLK_HOST1_ARB 459 309 #define HCLK_HSIC 460 310 #define HCLK_SD 461 311 #define HCLK_SDMMC 462 312 #define HCLK_SDMMC_NOC 463 313 #define HCLK_M_CRYPTO0 464 314 #define HCLK_M_CRYPTO1 465 315 #define HCLK_S_CRYPTO0 466 316 #define HCLK_S_CRYPTO1 467 317 #define HCLK_I2S0_8CH 468 318 #define HCLK_I2S1_8CH 469 319 #define HCLK_I2S2_8CH 470 320 #define HCLK_SPDIF 471 321 #define HCLK_VOP0_NOC 472 322 #define HCLK_VOP0 473 323 #define HCLK_VOP1_NOC 474 324 #define HCLK_VOP1 475 325 #define HCLK_ROM 476 326 #define HCLK_IEP 477 327 #define HCLK_IEP_NOC 478 328 #define HCLK_ISP0 479 329 #define HCLK_ISP1 480 330 #define HCLK_ISP0_NOC 481 331 #define HCLK_ISP1_NOC 482 332 #define HCLK_ISP0_WRAPPER 483 333 #define HCLK_ISP1_WRAPPER 484 334 #define HCLK_RGA 485 335 #define HCLK_RGA_NOC 486 336 #define HCLK_HDCP 487 337 #define HCLK_HDCP_NOC 488 338 #define HCLK_HDCP22 489 339 #define HCLK_VCODEC 490 340 #define HCLK_VCODEC_NOC 491 341 #define HCLK_VDU 492 342 #define HCLK_VDU_NOC 493 343 #define HCLK_SDIO 494 344 #define HCLK_SDIO_NOC 495 345 #define HCLK_SDIOAUDIO_NOC 496 346 347 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) 348 349 /* pmu-clocks indices */ 350 351 #define PLL_PPLL 1 352 353 #define SCLK_32K_SUSPEND_PMU 2 354 #define SCLK_SPI3_PMU 3 355 #define SCLK_TIMER12_PMU 4 356 #define SCLK_TIMER13_PMU 5 357 #define SCLK_UART4_PMU 6 358 #define SCLK_PVTM_PMU 7 359 #define SCLK_WIFI_PMU 8 360 #define SCLK_I2C0_PMU 9 361 #define SCLK_I2C4_PMU 10 362 #define SCLK_I2C8_PMU 11 363 364 #define PCLK_SRC_PMU 19 365 #define PCLK_PMU 20 366 #define PCLK_PMUGRF_PMU 21 367 #define PCLK_INTMEM1_PMU 22 368 #define PCLK_GPIO0_PMU 23 369 #define PCLK_GPIO1_PMU 24 370 #define PCLK_SGRF_PMU 25 371 #define PCLK_NOC_PMU 26 372 #define PCLK_I2C0_PMU 27 373 #define PCLK_I2C4_PMU 28 374 #define PCLK_I2C8_PMU 29 375 #define PCLK_RKPWM_PMU 30 376 #define PCLK_SPI3_PMU 31 377 #define PCLK_TIMER_PMU 32 378 #define PCLK_MAILBOX_PMU 33 379 #define PCLK_UART4_PMU 34 380 #define PCLK_WDT_M0_PMU 35 381 382 #define FCLK_CM0S_SRC_PMU 44 383 #define FCLK_CM0S_PMU 45 384 #define SCLK_CM0S_PMU 46 385 #define HCLK_CM0S_PMU 47 386 #define DCLK_CM0S_PMU 48 387 #define PCLK_INTR_ARB_PMU 49 388 #define HCLK_NOC_PMU 50 389 390 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) 391 392 /* soft-reset indices */ 393 394 /* cru_softrst_con0 */ 395 #define SRST_CORE_L0 0 396 #define SRST_CORE_B0 1 397 #define SRST_CORE_PO_L0 2 398 #define SRST_CORE_PO_B0 3 399 #define SRST_L2_L 4 400 #define SRST_L2_B 5 401 #define SRST_ADB_L 6 402 #define SRST_ADB_B 7 403 #define SRST_A_CCI 8 404 #define SRST_A_CCIM0_NOC 9 405 #define SRST_A_CCIM1_NOC 10 406 #define SRST_DBG_NOC 11 407 408 /* cru_softrst_con1 */ 409 #define SRST_CORE_L0_T 16 410 #define SRST_CORE_L1 17 411 #define SRST_CORE_L2 18 412 #define SRST_CORE_L3 19 413 #define SRST_CORE_PO_L0_T 20 414 #define SRST_CORE_PO_L1 21 415 #define SRST_CORE_PO_L2 22 416 #define SRST_CORE_PO_L3 23 417 #define SRST_A_ADB400_GIC2COREL 24 418 #define SRST_A_ADB400_COREL2GIC 25 419 #define SRST_P_DBG_L 26 420 #define SRST_L2_L_T 28 421 #define SRST_ADB_L_T 29 422 #define SRST_A_RKPERF_L 30 423 #define SRST_PVTM_CORE_L 31 424 425 /* cru_softrst_con2 */ 426 #define SRST_CORE_B0_T 32 427 #define SRST_CORE_B1 33 428 #define SRST_CORE_PO_B0_T 36 429 #define SRST_CORE_PO_B1 37 430 #define SRST_A_ADB400_GIC2COREB 40 431 #define SRST_A_ADB400_COREB2GIC 41 432 #define SRST_P_DBG_B 42 433 #define SRST_L2_B_T 43 434 #define SRST_ADB_B_T 45 435 #define SRST_A_RKPERF_B 46 436 #define SRST_PVTM_CORE_B 47 437 438 /* cru_softrst_con3 */ 439 #define SRST_A_CCI_T 50 440 #define SRST_A_CCIM0_NOC_T 51 441 #define SRST_A_CCIM1_NOC_T 52 442 #define SRST_A_ADB400M_PD_CORE_B_T 53 443 #define SRST_A_ADB400M_PD_CORE_L_T 54 444 #define SRST_DBG_NOC_T 55 445 #define SRST_DBG_CXCS 56 446 #define SRST_CCI_TRACE 57 447 #define SRST_P_CCI_GRF 58 448 449 /* cru_softrst_con4 */ 450 #define SRST_A_CENTER_MAIN_NOC 64 451 #define SRST_A_CENTER_PERI_NOC 65 452 #define SRST_P_CENTER_MAIN 66 453 #define SRST_P_DDRMON 67 454 #define SRST_P_CIC 68 455 #define SRST_P_CENTER_SGRF 69 456 #define SRST_DDR0_MSCH 70 457 #define SRST_DDRCFG0_MSCH 71 458 #define SRST_DDR0 72 459 #define SRST_DDRPHY0 73 460 #define SRST_DDR1_MSCH 74 461 #define SRST_DDRCFG1_MSCH 75 462 #define SRST_DDR1 76 463 #define SRST_DDRPHY1 77 464 #define SRST_DDR_CIC 78 465 #define SRST_PVTM_DDR 79 466 467 /* cru_softrst_con5 */ 468 #define SRST_A_VCODEC_NOC 80 469 #define SRST_A_VCODEC 81 470 #define SRST_H_VCODEC_NOC 82 471 #define SRST_H_VCODEC 83 472 #define SRST_A_VDU_NOC 88 473 #define SRST_A_VDU 89 474 #define SRST_H_VDU_NOC 90 475 #define SRST_H_VDU 91 476 #define SRST_VDU_CORE 92 477 #define SRST_VDU_CA 93 478 479 /* cru_softrst_con6 */ 480 #define SRST_A_IEP_NOC 96 481 #define SRST_A_VOP_IEP 97 482 #define SRST_A_IEP 98 483 #define SRST_H_IEP_NOC 99 484 #define SRST_H_IEP 100 485 #define SRST_A_RGA_NOC 102 486 #define SRST_A_RGA 103 487 #define SRST_H_RGA_NOC 104 488 #define SRST_H_RGA 105 489 #define SRST_RGA_CORE 106 490 #define SRST_EMMC_NOC 108 491 #define SRST_EMMC 109 492 #define SRST_EMMC_GRF 110 493 494 /* cru_softrst_con7 */ 495 #define SRST_A_PERIHP_NOC 112 496 #define SRST_P_PERIHP_GRF 113 497 #define SRST_H_PERIHP_NOC 114 498 #define SRST_USBHOST0 115 499 #define SRST_HOSTC0_AUX 116 500 #define SRST_HOST0_ARB 117 501 #define SRST_USBHOST1 118 502 #define SRST_HOSTC1_AUX 119 503 #define SRST_HOST1_ARB 120 504 #define SRST_SDIO0 121 505 #define SRST_SDMMC 122 506 #define SRST_HSIC 123 507 #define SRST_HSIC_AUX 124 508 #define SRST_AHB1TOM 125 509 #define SRST_P_PERIHP_NOC 126 510 #define SRST_HSICPHY 127 511 512 /* cru_softrst_con8 */ 513 #define SRST_A_PCIE 128 514 #define SRST_P_PCIE 129 515 #define SRST_PCIE_CORE 130 516 #define SRST_PCIE_MGMT 131 517 #define SRST_PCIE_MGMT_STICKY 132 518 #define SRST_PCIE_PIPE 133 519 #define SRST_PCIE_PM 134 520 #define SRST_PCIEPHY 135 521 #define SRST_A_GMAC_NOC 136 522 #define SRST_A_GMAC 137 523 #define SRST_P_GMAC_NOC 138 524 #define SRST_P_GMAC_GRF 140 525 #define SRST_HSICPHY_POR 142 526 #define SRST_HSICPHY_UTMI 143 527 528 /* cru_softrst_con9 */ 529 #define SRST_USB2PHY0_POR 144 530 #define SRST_USB2PHY0_UTMI_PORT0 145 531 #define SRST_USB2PHY0_UTMI_PORT1 146 532 #define SRST_USB2PHY0_EHCIPHY 147 533 #define SRST_UPHY0_PIPE_L00 148 534 #define SRST_UPHY0 149 535 #define SRST_UPHY0_TCPDPWRUP 150 536 #define SRST_USB2PHY1_POR 152 537 #define SRST_USB2PHY1_UTMI_PORT0 153 538 #define SRST_USB2PHY1_UTMI_PORT1 154 539 #define SRST_USB2PHY1_EHCIPHY 155 540 #define SRST_UPHY1_PIPE_L00 156 541 #define SRST_UPHY1 157 542 #define SRST_UPHY1_TCPDPWRUP 158 543 544 /* cru_softrst_con10 */ 545 #define SRST_A_PERILP0_NOC 160 546 #define SRST_A_DCF 161 547 #define SRST_GIC500 162 548 #define SRST_DMAC0_PERILP0 163 549 #define SRST_DMAC1_PERILP0 164 550 #define SRST_TZMA 165 551 #define SRST_INTMEM 166 552 #define SRST_ADB400_MST0 167 553 #define SRST_ADB400_MST1 168 554 #define SRST_ADB400_SLV0 169 555 #define SRST_ADB400_SLV1 170 556 #define SRST_H_PERILP0 171 557 #define SRST_H_PERILP0_NOC 172 558 #define SRST_ROM 173 559 #define SRST_CRYPTO_S 174 560 #define SRST_CRYPTO_M 175 561 562 /* cru_softrst_con11 */ 563 #define SRST_P_DCF 176 564 #define SRST_CM0S_NOC 177 565 #define SRST_CM0S 178 566 #define SRST_CM0S_DBG 179 567 #define SRST_CM0S_PO 180 568 #define SRST_CRYPTO 181 569 #define SRST_P_PERILP1_SGRF 182 570 #define SRST_P_PERILP1_GRF 183 571 #define SRST_CRYPTO1_S 184 572 #define SRST_CRYPTO1_M 185 573 #define SRST_CRYPTO1 186 574 #define SRST_GIC_NOC 188 575 #define SRST_SD_NOC 189 576 #define SRST_SDIOAUDIO_BRG 190 577 578 /* cru_softrst_con12 */ 579 #define SRST_H_PERILP1 192 580 #define SRST_H_PERILP1_NOC 193 581 #define SRST_H_I2S0_8CH 194 582 #define SRST_H_I2S1_8CH 195 583 #define SRST_H_I2S2_8CH 196 584 #define SRST_H_SPDIF_8CH 197 585 #define SRST_P_PERILP1_NOC 198 586 #define SRST_P_EFUSE_1024 199 587 #define SRST_P_EFUSE_1024S 200 588 #define SRST_P_I2C0 201 589 #define SRST_P_I2C1 202 590 #define SRST_P_I2C2 203 591 #define SRST_P_I2C3 204 592 #define SRST_P_I2C4 205 593 #define SRST_P_I2C5 206 594 #define SRST_P_MAILBOX0 207 595 596 /* cru_softrst_con13 */ 597 #define SRST_P_UART0 208 598 #define SRST_P_UART1 209 599 #define SRST_P_UART2 210 600 #define SRST_P_UART3 211 601 #define SRST_P_SARADC 212 602 #define SRST_P_TSADC 213 603 #define SRST_P_SPI0 214 604 #define SRST_P_SPI1 215 605 #define SRST_P_SPI2 216 606 #define SRST_P_SPI3 217 607 #define SRST_P_SPI4 218 608 #define SRST_SPI0 219 609 #define SRST_SPI1 220 610 #define SRST_SPI2 221 611 #define SRST_SPI3 222 612 #define SRST_SPI4 223 613 614 /* cru_softrst_con14 */ 615 #define SRST_I2S0_8CH 224 616 #define SRST_I2S1_8CH 225 617 #define SRST_I2S2_8CH 226 618 #define SRST_SPDIF_8CH 227 619 #define SRST_UART0 228 620 #define SRST_UART1 229 621 #define SRST_UART2 230 622 #define SRST_UART3 231 623 #define SRST_TSADC 232 624 #define SRST_I2C0 233 625 #define SRST_I2C1 234 626 #define SRST_I2C2 235 627 #define SRST_I2C3 236 628 #define SRST_I2C4 237 629 #define SRST_I2C5 238 630 #define SRST_SDIOAUDIO_NOC 239 631 632 /* cru_softrst_con15 */ 633 #define SRST_A_VIO_NOC 240 634 #define SRST_A_HDCP_NOC 241 635 #define SRST_A_HDCP 242 636 #define SRST_H_HDCP_NOC 243 637 #define SRST_H_HDCP 244 638 #define SRST_P_HDCP_NOC 245 639 #define SRST_P_HDCP 246 640 #define SRST_P_HDMI_CTRL 247 641 #define SRST_P_DP_CTRL 248 642 #define SRST_S_DP_CTRL 249 643 #define SRST_C_DP_CTRL 250 644 #define SRST_P_MIPI_DSI0 251 645 #define SRST_P_MIPI_DSI1 252 646 #define SRST_DP_CORE 253 647 #define SRST_DP_I2S 254 648 649 /* cru_softrst_con16 */ 650 #define SRST_GASKET 256 651 #define SRST_VIO_GRF 258 652 #define SRST_DPTX_SPDIF_REC 259 653 #define SRST_HDMI_CTRL 260 654 #define SRST_HDCP_CTRL 261 655 #define SRST_A_ISP0_NOC 262 656 #define SRST_A_ISP1_NOC 263 657 #define SRST_H_ISP0_NOC 266 658 #define SRST_H_ISP1_NOC 267 659 #define SRST_H_ISP0 268 660 #define SRST_H_ISP1 269 661 #define SRST_ISP0 270 662 #define SRST_ISP1 271 663 664 /* cru_softrst_con17 */ 665 #define SRST_A_VOP0_NOC 272 666 #define SRST_A_VOP1_NOC 273 667 #define SRST_A_VOP0 274 668 #define SRST_A_VOP1 275 669 #define SRST_H_VOP0_NOC 276 670 #define SRST_H_VOP1_NOC 277 671 #define SRST_H_VOP0 278 672 #define SRST_H_VOP1 279 673 #define SRST_D_VOP0 280 674 #define SRST_D_VOP1 281 675 #define SRST_VOP0_PWM 282 676 #define SRST_VOP1_PWM 283 677 #define SRST_P_EDP_NOC 284 678 #define SRST_P_EDP_CTRL 285 679 680 /* cru_softrst_con18 */ 681 #define SRST_A_GPU 288 682 #define SRST_A_GPU_NOC 289 683 #define SRST_A_GPU_GRF 290 684 #define SRST_PVTM_GPU 291 685 #define SRST_A_USB3_NOC 292 686 #define SRST_A_USB3_OTG0 293 687 #define SRST_A_USB3_OTG1 294 688 #define SRST_A_USB3_GRF 295 689 #define SRST_PMU 296 690 691 /* cru_softrst_con19 */ 692 #define SRST_P_TIMER0_5 304 693 #define SRST_TIMER0 305 694 #define SRST_TIMER1 306 695 #define SRST_TIMER2 307 696 #define SRST_TIMER3 308 697 #define SRST_TIMER4 309 698 #define SRST_TIMER5 310 699 #define SRST_P_TIMER6_11 311 700 #define SRST_TIMER6 312 701 #define SRST_TIMER7 313 702 #define SRST_TIMER8 314 703 #define SRST_TIMER9 315 704 #define SRST_TIMER10 316 705 #define SRST_TIMER11 317 706 #define SRST_P_INTR_ARB_PMU 318 707 #define SRST_P_ALIVE_SGRF 319 708 709 /* cru_softrst_con20 */ 710 #define SRST_P_GPIO2 320 711 #define SRST_P_GPIO3 321 712 #define SRST_P_GPIO4 322 713 #define SRST_P_GRF 323 714 #define SRST_P_ALIVE_NOC 324 715 #define SRST_P_WDT0 325 716 #define SRST_P_WDT1 326 717 #define SRST_P_INTR_ARB 327 718 #define SRST_P_UPHY0_DPTX 328 719 #define SRST_P_UPHY0_APB 330 720 #define SRST_P_UPHY0_TCPHY 332 721 #define SRST_P_UPHY1_TCPHY 333 722 #define SRST_P_UPHY0_TCPDCTRL 334 723 #define SRST_P_UPHY1_TCPDCTRL 335 724 725 /* pmu soft-reset indices */ 726 727 /* pmu_cru_softrst_con0 */ 728 #define SRST_P_NOC 0 729 #define SRST_P_INTMEM 1 730 #define SRST_H_CM0S 2 731 #define SRST_H_CM0S_NOC 3 732 #define SRST_DBG_CM0S 4 733 #define SRST_PO_CM0S 5 734 #define SRST_P_SPI6 6 735 #define SRST_SPI6 7 736 #define SRST_P_TIMER_0_1 8 737 #define SRST_P_TIMER_0 9 738 #define SRST_P_TIMER_1 10 739 #define SRST_P_UART4 11 740 #define SRST_UART4 12 741 #define SRST_P_WDT 13 742 743 /* pmu_cru_softrst_con1 */ 744 #define SRST_P_I2C6 16 745 #define SRST_P_I2C7 17 746 #define SRST_P_I2C8 18 747 #define SRST_P_MAILBOX 19 748 #define SRST_P_RKPWM 20 749 #define SRST_P_PMUGRF 21 750 #define SRST_P_SGRF 22 751 #define SRST_P_GPIO0 23 752 #define SRST_P_GPIO1 24 753 #define SRST_P_CRU 25 754 #define SRST_P_INTR 26 755 #define SRST_PVTM 27 756 #define SRST_I2C6 28 757 #define SRST_I2C7 29 758 #define SRST_I2C8 30 759 760 #endif 761