1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __INCLUDE_ATMEL_SSC_H 3 #define __INCLUDE_ATMEL_SSC_H 4 5 #include <linux/platform_device.h> 6 #include <linux/list.h> 7 #include <linux/io.h> 8 9 struct atmel_ssc_platform_data { 10 int use_dma; 11 int has_fslen_ext; 12 }; 13 14 struct ssc_device { 15 struct list_head list; 16 dma_addr_t phybase; 17 void __iomem *regs; 18 struct platform_device *pdev; 19 struct atmel_ssc_platform_data *pdata; 20 struct clk *clk; 21 int user; 22 int irq; 23 bool clk_from_rk_pin; 24 bool sound_dai; 25 }; 26 27 struct ssc_device * __must_check ssc_request(unsigned int ssc_num); 28 void ssc_free(struct ssc_device *ssc); 29 30 /* SSC register offsets */ 31 32 /* SSC Control Register */ 33 #define SSC_CR 0x00000000 34 #define SSC_CR_RXDIS_SIZE 1 35 #define SSC_CR_RXDIS_OFFSET 1 36 #define SSC_CR_RXEN_SIZE 1 37 #define SSC_CR_RXEN_OFFSET 0 38 #define SSC_CR_SWRST_SIZE 1 39 #define SSC_CR_SWRST_OFFSET 15 40 #define SSC_CR_TXDIS_SIZE 1 41 #define SSC_CR_TXDIS_OFFSET 9 42 #define SSC_CR_TXEN_SIZE 1 43 #define SSC_CR_TXEN_OFFSET 8 44 45 /* SSC Clock Mode Register */ 46 #define SSC_CMR 0x00000004 47 #define SSC_CMR_DIV_SIZE 12 48 #define SSC_CMR_DIV_OFFSET 0 49 50 /* SSC Receive Clock Mode Register */ 51 #define SSC_RCMR 0x00000010 52 #define SSC_RCMR_CKG_SIZE 2 53 #define SSC_RCMR_CKG_OFFSET 6 54 #define SSC_RCMR_CKI_SIZE 1 55 #define SSC_RCMR_CKI_OFFSET 5 56 #define SSC_RCMR_CKO_SIZE 3 57 #define SSC_RCMR_CKO_OFFSET 2 58 #define SSC_RCMR_CKS_SIZE 2 59 #define SSC_RCMR_CKS_OFFSET 0 60 #define SSC_RCMR_PERIOD_SIZE 8 61 #define SSC_RCMR_PERIOD_OFFSET 24 62 #define SSC_RCMR_START_SIZE 4 63 #define SSC_RCMR_START_OFFSET 8 64 #define SSC_RCMR_STOP_SIZE 1 65 #define SSC_RCMR_STOP_OFFSET 12 66 #define SSC_RCMR_STTDLY_SIZE 8 67 #define SSC_RCMR_STTDLY_OFFSET 16 68 69 /* SSC Receive Frame Mode Register */ 70 #define SSC_RFMR 0x00000014 71 #define SSC_RFMR_DATLEN_SIZE 5 72 #define SSC_RFMR_DATLEN_OFFSET 0 73 #define SSC_RFMR_DATNB_SIZE 4 74 #define SSC_RFMR_DATNB_OFFSET 8 75 #define SSC_RFMR_FSEDGE_SIZE 1 76 #define SSC_RFMR_FSEDGE_OFFSET 24 77 /* 78 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10, 79 * at91sam9g20, and at91sam9g45 and newer SoCs 80 */ 81 #define SSC_RFMR_FSLEN_EXT_SIZE 4 82 #define SSC_RFMR_FSLEN_EXT_OFFSET 28 83 #define SSC_RFMR_FSLEN_SIZE 4 84 #define SSC_RFMR_FSLEN_OFFSET 16 85 #define SSC_RFMR_FSOS_SIZE 4 86 #define SSC_RFMR_FSOS_OFFSET 20 87 #define SSC_RFMR_LOOP_SIZE 1 88 #define SSC_RFMR_LOOP_OFFSET 5 89 #define SSC_RFMR_MSBF_SIZE 1 90 #define SSC_RFMR_MSBF_OFFSET 7 91 92 /* SSC Transmit Clock Mode Register */ 93 #define SSC_TCMR 0x00000018 94 #define SSC_TCMR_CKG_SIZE 2 95 #define SSC_TCMR_CKG_OFFSET 6 96 #define SSC_TCMR_CKI_SIZE 1 97 #define SSC_TCMR_CKI_OFFSET 5 98 #define SSC_TCMR_CKO_SIZE 3 99 #define SSC_TCMR_CKO_OFFSET 2 100 #define SSC_TCMR_CKS_SIZE 2 101 #define SSC_TCMR_CKS_OFFSET 0 102 #define SSC_TCMR_PERIOD_SIZE 8 103 #define SSC_TCMR_PERIOD_OFFSET 24 104 #define SSC_TCMR_START_SIZE 4 105 #define SSC_TCMR_START_OFFSET 8 106 #define SSC_TCMR_STTDLY_SIZE 8 107 #define SSC_TCMR_STTDLY_OFFSET 16 108 109 /* SSC Transmit Frame Mode Register */ 110 #define SSC_TFMR 0x0000001c 111 #define SSC_TFMR_DATDEF_SIZE 1 112 #define SSC_TFMR_DATDEF_OFFSET 5 113 #define SSC_TFMR_DATLEN_SIZE 5 114 #define SSC_TFMR_DATLEN_OFFSET 0 115 #define SSC_TFMR_DATNB_SIZE 4 116 #define SSC_TFMR_DATNB_OFFSET 8 117 #define SSC_TFMR_FSDEN_SIZE 1 118 #define SSC_TFMR_FSDEN_OFFSET 23 119 #define SSC_TFMR_FSEDGE_SIZE 1 120 #define SSC_TFMR_FSEDGE_OFFSET 24 121 /* 122 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10, 123 * at91sam9g20, and at91sam9g45 and newer SoCs 124 */ 125 #define SSC_TFMR_FSLEN_EXT_SIZE 4 126 #define SSC_TFMR_FSLEN_EXT_OFFSET 28 127 #define SSC_TFMR_FSLEN_SIZE 4 128 #define SSC_TFMR_FSLEN_OFFSET 16 129 #define SSC_TFMR_FSOS_SIZE 3 130 #define SSC_TFMR_FSOS_OFFSET 20 131 #define SSC_TFMR_MSBF_SIZE 1 132 #define SSC_TFMR_MSBF_OFFSET 7 133 134 /* SSC Receive Hold Register */ 135 #define SSC_RHR 0x00000020 136 #define SSC_RHR_RDAT_SIZE 32 137 #define SSC_RHR_RDAT_OFFSET 0 138 139 /* SSC Transmit Hold Register */ 140 #define SSC_THR 0x00000024 141 #define SSC_THR_TDAT_SIZE 32 142 #define SSC_THR_TDAT_OFFSET 0 143 144 /* SSC Receive Sync. Holding Register */ 145 #define SSC_RSHR 0x00000030 146 #define SSC_RSHR_RSDAT_SIZE 16 147 #define SSC_RSHR_RSDAT_OFFSET 0 148 149 /* SSC Transmit Sync. Holding Register */ 150 #define SSC_TSHR 0x00000034 151 #define SSC_TSHR_TSDAT_SIZE 16 152 #define SSC_TSHR_RSDAT_OFFSET 0 153 154 /* SSC Receive Compare 0 Register */ 155 #define SSC_RC0R 0x00000038 156 #define SSC_RC0R_CP0_SIZE 16 157 #define SSC_RC0R_CP0_OFFSET 0 158 159 /* SSC Receive Compare 1 Register */ 160 #define SSC_RC1R 0x0000003c 161 #define SSC_RC1R_CP1_SIZE 16 162 #define SSC_RC1R_CP1_OFFSET 0 163 164 /* SSC Status Register */ 165 #define SSC_SR 0x00000040 166 #define SSC_SR_CP0_SIZE 1 167 #define SSC_SR_CP0_OFFSET 8 168 #define SSC_SR_CP1_SIZE 1 169 #define SSC_SR_CP1_OFFSET 9 170 #define SSC_SR_ENDRX_SIZE 1 171 #define SSC_SR_ENDRX_OFFSET 6 172 #define SSC_SR_ENDTX_SIZE 1 173 #define SSC_SR_ENDTX_OFFSET 2 174 #define SSC_SR_OVRUN_SIZE 1 175 #define SSC_SR_OVRUN_OFFSET 5 176 #define SSC_SR_RXBUFF_SIZE 1 177 #define SSC_SR_RXBUFF_OFFSET 7 178 #define SSC_SR_RXEN_SIZE 1 179 #define SSC_SR_RXEN_OFFSET 17 180 #define SSC_SR_RXRDY_SIZE 1 181 #define SSC_SR_RXRDY_OFFSET 4 182 #define SSC_SR_RXSYN_SIZE 1 183 #define SSC_SR_RXSYN_OFFSET 11 184 #define SSC_SR_TXBUFE_SIZE 1 185 #define SSC_SR_TXBUFE_OFFSET 3 186 #define SSC_SR_TXEMPTY_SIZE 1 187 #define SSC_SR_TXEMPTY_OFFSET 1 188 #define SSC_SR_TXEN_SIZE 1 189 #define SSC_SR_TXEN_OFFSET 16 190 #define SSC_SR_TXRDY_SIZE 1 191 #define SSC_SR_TXRDY_OFFSET 0 192 #define SSC_SR_TXSYN_SIZE 1 193 #define SSC_SR_TXSYN_OFFSET 10 194 195 /* SSC Interrupt Enable Register */ 196 #define SSC_IER 0x00000044 197 #define SSC_IER_CP0_SIZE 1 198 #define SSC_IER_CP0_OFFSET 8 199 #define SSC_IER_CP1_SIZE 1 200 #define SSC_IER_CP1_OFFSET 9 201 #define SSC_IER_ENDRX_SIZE 1 202 #define SSC_IER_ENDRX_OFFSET 6 203 #define SSC_IER_ENDTX_SIZE 1 204 #define SSC_IER_ENDTX_OFFSET 2 205 #define SSC_IER_OVRUN_SIZE 1 206 #define SSC_IER_OVRUN_OFFSET 5 207 #define SSC_IER_RXBUFF_SIZE 1 208 #define SSC_IER_RXBUFF_OFFSET 7 209 #define SSC_IER_RXRDY_SIZE 1 210 #define SSC_IER_RXRDY_OFFSET 4 211 #define SSC_IER_RXSYN_SIZE 1 212 #define SSC_IER_RXSYN_OFFSET 11 213 #define SSC_IER_TXBUFE_SIZE 1 214 #define SSC_IER_TXBUFE_OFFSET 3 215 #define SSC_IER_TXEMPTY_SIZE 1 216 #define SSC_IER_TXEMPTY_OFFSET 1 217 #define SSC_IER_TXRDY_SIZE 1 218 #define SSC_IER_TXRDY_OFFSET 0 219 #define SSC_IER_TXSYN_SIZE 1 220 #define SSC_IER_TXSYN_OFFSET 10 221 222 /* SSC Interrupt Disable Register */ 223 #define SSC_IDR 0x00000048 224 #define SSC_IDR_CP0_SIZE 1 225 #define SSC_IDR_CP0_OFFSET 8 226 #define SSC_IDR_CP1_SIZE 1 227 #define SSC_IDR_CP1_OFFSET 9 228 #define SSC_IDR_ENDRX_SIZE 1 229 #define SSC_IDR_ENDRX_OFFSET 6 230 #define SSC_IDR_ENDTX_SIZE 1 231 #define SSC_IDR_ENDTX_OFFSET 2 232 #define SSC_IDR_OVRUN_SIZE 1 233 #define SSC_IDR_OVRUN_OFFSET 5 234 #define SSC_IDR_RXBUFF_SIZE 1 235 #define SSC_IDR_RXBUFF_OFFSET 7 236 #define SSC_IDR_RXRDY_SIZE 1 237 #define SSC_IDR_RXRDY_OFFSET 4 238 #define SSC_IDR_RXSYN_SIZE 1 239 #define SSC_IDR_RXSYN_OFFSET 11 240 #define SSC_IDR_TXBUFE_SIZE 1 241 #define SSC_IDR_TXBUFE_OFFSET 3 242 #define SSC_IDR_TXEMPTY_SIZE 1 243 #define SSC_IDR_TXEMPTY_OFFSET 1 244 #define SSC_IDR_TXRDY_SIZE 1 245 #define SSC_IDR_TXRDY_OFFSET 0 246 #define SSC_IDR_TXSYN_SIZE 1 247 #define SSC_IDR_TXSYN_OFFSET 10 248 249 /* SSC Interrupt Mask Register */ 250 #define SSC_IMR 0x0000004c 251 #define SSC_IMR_CP0_SIZE 1 252 #define SSC_IMR_CP0_OFFSET 8 253 #define SSC_IMR_CP1_SIZE 1 254 #define SSC_IMR_CP1_OFFSET 9 255 #define SSC_IMR_ENDRX_SIZE 1 256 #define SSC_IMR_ENDRX_OFFSET 6 257 #define SSC_IMR_ENDTX_SIZE 1 258 #define SSC_IMR_ENDTX_OFFSET 2 259 #define SSC_IMR_OVRUN_SIZE 1 260 #define SSC_IMR_OVRUN_OFFSET 5 261 #define SSC_IMR_RXBUFF_SIZE 1 262 #define SSC_IMR_RXBUFF_OFFSET 7 263 #define SSC_IMR_RXRDY_SIZE 1 264 #define SSC_IMR_RXRDY_OFFSET 4 265 #define SSC_IMR_RXSYN_SIZE 1 266 #define SSC_IMR_RXSYN_OFFSET 11 267 #define SSC_IMR_TXBUFE_SIZE 1 268 #define SSC_IMR_TXBUFE_OFFSET 3 269 #define SSC_IMR_TXEMPTY_SIZE 1 270 #define SSC_IMR_TXEMPTY_OFFSET 1 271 #define SSC_IMR_TXRDY_SIZE 1 272 #define SSC_IMR_TXRDY_OFFSET 0 273 #define SSC_IMR_TXSYN_SIZE 1 274 #define SSC_IMR_TXSYN_OFFSET 10 275 276 /* SSC PDC Receive Pointer Register */ 277 #define SSC_PDC_RPR 0x00000100 278 279 /* SSC PDC Receive Counter Register */ 280 #define SSC_PDC_RCR 0x00000104 281 282 /* SSC PDC Transmit Pointer Register */ 283 #define SSC_PDC_TPR 0x00000108 284 285 /* SSC PDC Receive Next Pointer Register */ 286 #define SSC_PDC_RNPR 0x00000110 287 288 /* SSC PDC Receive Next Counter Register */ 289 #define SSC_PDC_RNCR 0x00000114 290 291 /* SSC PDC Transmit Counter Register */ 292 #define SSC_PDC_TCR 0x0000010c 293 294 /* SSC PDC Transmit Next Pointer Register */ 295 #define SSC_PDC_TNPR 0x00000118 296 297 /* SSC PDC Transmit Next Counter Register */ 298 #define SSC_PDC_TNCR 0x0000011c 299 300 /* SSC PDC Transfer Control Register */ 301 #define SSC_PDC_PTCR 0x00000120 302 #define SSC_PDC_PTCR_RXTDIS_SIZE 1 303 #define SSC_PDC_PTCR_RXTDIS_OFFSET 1 304 #define SSC_PDC_PTCR_RXTEN_SIZE 1 305 #define SSC_PDC_PTCR_RXTEN_OFFSET 0 306 #define SSC_PDC_PTCR_TXTDIS_SIZE 1 307 #define SSC_PDC_PTCR_TXTDIS_OFFSET 9 308 #define SSC_PDC_PTCR_TXTEN_SIZE 1 309 #define SSC_PDC_PTCR_TXTEN_OFFSET 8 310 311 /* SSC PDC Transfer Status Register */ 312 #define SSC_PDC_PTSR 0x00000124 313 #define SSC_PDC_PTSR_RXTEN_SIZE 1 314 #define SSC_PDC_PTSR_RXTEN_OFFSET 0 315 #define SSC_PDC_PTSR_TXTEN_SIZE 1 316 #define SSC_PDC_PTSR_TXTEN_OFFSET 8 317 318 /* Bit manipulation macros */ 319 #define SSC_BIT(name) \ 320 (1 << SSC_##name##_OFFSET) 321 #define SSC_BF(name, value) \ 322 (((value) & ((1 << SSC_##name##_SIZE) - 1)) \ 323 << SSC_##name##_OFFSET) 324 #define SSC_BFEXT(name, value) \ 325 (((value) >> SSC_##name##_OFFSET) \ 326 & ((1 << SSC_##name##_SIZE) - 1)) 327 #define SSC_BFINS(name, value, old) \ 328 (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \ 329 << SSC_##name##_OFFSET)) | SSC_BF(name, value)) 330 331 /* Register access macros */ 332 #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) 333 #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg) 334 335 #endif /* __INCLUDE_ATMEL_SSC_H */ 336