1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Thunderbolt Cactus Ridge driver - Port/Switch config area registers
4  *
5  * Every thunderbolt device consists (logically) of a switch with multiple
6  * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
7  * COUNTERS) which are used to configure the device.
8  *
9  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
10  */
11 
12 #ifndef _TB_REGS
13 #define _TB_REGS
14 
15 #include <linux/types.h>
16 
17 
18 #define TB_ROUTE_SHIFT 8  /* number of bits in a port entry of a route */
19 
20 
21 /*
22  * TODO: should be 63? But we do not know how to receive frames larger than 256
23  * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
24  */
25 #define TB_MAX_CONFIG_RW_LENGTH 60
26 
27 enum tb_switch_cap {
28 	TB_SWITCH_CAP_VSE		= 0x05,
29 };
30 
31 enum tb_switch_vse_cap {
32 	TB_VSE_CAP_PLUG_EVENTS		= 0x01, /* also EEPROM */
33 	TB_VSE_CAP_TIME2		= 0x03,
34 	TB_VSE_CAP_IECS			= 0x04,
35 	TB_VSE_CAP_LINK_CONTROLLER	= 0x06, /* also IECS */
36 };
37 
38 enum tb_port_cap {
39 	TB_PORT_CAP_PHY			= 0x01,
40 	TB_PORT_CAP_TIME1		= 0x03,
41 	TB_PORT_CAP_ADAP		= 0x04,
42 	TB_PORT_CAP_VSE			= 0x05,
43 };
44 
45 enum tb_port_state {
46 	TB_PORT_DISABLED	= 0, /* tb_cap_phy.disable == 1 */
47 	TB_PORT_CONNECTING	= 1, /* retry */
48 	TB_PORT_UP		= 2,
49 	TB_PORT_UNPLUGGED	= 7,
50 };
51 
52 /* capability headers */
53 
54 struct tb_cap_basic {
55 	u8 next;
56 	/* enum tb_cap cap:8; prevent "narrower than values of its type" */
57 	u8 cap; /* if cap == 0x05 then we have a extended capability */
58 } __packed;
59 
60 /**
61  * struct tb_cap_extended_short - Switch extended short capability
62  * @next: Pointer to the next capability. If @next and @length are zero
63  *	  then we have a long cap.
64  * @cap: Base capability ID (see &enum tb_switch_cap)
65  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
66  * @length: Length of this capability
67  */
68 struct tb_cap_extended_short {
69 	u8 next;
70 	u8 cap;
71 	u8 vsec_id;
72 	u8 length;
73 } __packed;
74 
75 /**
76  * struct tb_cap_extended_long - Switch extended long capability
77  * @zero1: This field should be zero
78  * @cap: Base capability ID (see &enum tb_switch_cap)
79  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
80  * @zero2: This field should be zero
81  * @next: Pointer to the next capability
82  * @length: Length of this capability
83  */
84 struct tb_cap_extended_long {
85 	u8 zero1;
86 	u8 cap;
87 	u8 vsec_id;
88 	u8 zero2;
89 	u16 next;
90 	u16 length;
91 } __packed;
92 
93 /* capabilities */
94 
95 struct tb_cap_link_controller {
96 	struct tb_cap_extended_long cap_header;
97 	u32 count:4; /* number of link controllers */
98 	u32 unknown1:4;
99 	u32 base_offset:8; /*
100 			    * offset (into this capability) of the configuration
101 			    * area of the first link controller
102 			    */
103 	u32 length:12; /* link controller configuration area length */
104 	u32 unknown2:4; /* TODO check that length is correct */
105 } __packed;
106 
107 struct tb_cap_phy {
108 	struct tb_cap_basic cap_header;
109 	u32 unknown1:16;
110 	u32 unknown2:14;
111 	bool disable:1;
112 	u32 unknown3:11;
113 	enum tb_port_state state:4;
114 	u32 unknown4:2;
115 } __packed;
116 
117 struct tb_eeprom_ctl {
118 	bool clock:1; /* send pulse to transfer one bit */
119 	bool access_low:1; /* set to 0 before access */
120 	bool data_out:1; /* to eeprom */
121 	bool data_in:1; /* from eeprom */
122 	bool access_high:1; /* set to 1 before access */
123 	bool not_present:1; /* should be 0 */
124 	bool unknown1:1;
125 	bool present:1; /* should be 1 */
126 	u32 unknown2:24;
127 } __packed;
128 
129 struct tb_cap_plug_events {
130 	struct tb_cap_extended_short cap_header;
131 	u32 __unknown1:2;
132 	u32 plug_events:5;
133 	u32 __unknown2:25;
134 	u32 __unknown3;
135 	u32 __unknown4;
136 	struct tb_eeprom_ctl eeprom_ctl;
137 	u32 __unknown5[7];
138 	u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
139 } __packed;
140 
141 /* device headers */
142 
143 /* Present on port 0 in TB_CFG_SWITCH at address zero. */
144 struct tb_regs_switch_header {
145 	/* DWORD 0 */
146 	u16 vendor_id;
147 	u16 device_id;
148 	/* DWORD 1 */
149 	u32 first_cap_offset:8;
150 	u32 upstream_port_number:6;
151 	u32 max_port_number:6;
152 	u32 depth:3;
153 	u32 __unknown1:1;
154 	u32 revision:8;
155 	/* DWORD 2 */
156 	u32 route_lo;
157 	/* DWORD 3 */
158 	u32 route_hi:31;
159 	bool enabled:1;
160 	/* DWORD 4 */
161 	u32 plug_events_delay:8; /*
162 				  * RW, pause between plug events in
163 				  * milliseconds. Writing 0x00 is interpreted
164 				  * as 255ms.
165 				  */
166 	u32 __unknown4:16;
167 	u32 thunderbolt_version:8;
168 } __packed;
169 
170 enum tb_port_type {
171 	TB_TYPE_INACTIVE	= 0x000000,
172 	TB_TYPE_PORT		= 0x000001,
173 	TB_TYPE_NHI		= 0x000002,
174 	/* TB_TYPE_ETHERNET	= 0x020000, lower order bits are not known */
175 	/* TB_TYPE_SATA		= 0x080000, lower order bits are not known */
176 	TB_TYPE_DP_HDMI_IN	= 0x0e0101,
177 	TB_TYPE_DP_HDMI_OUT	= 0x0e0102,
178 	TB_TYPE_PCIE_DOWN	= 0x100101,
179 	TB_TYPE_PCIE_UP		= 0x100102,
180 	/* TB_TYPE_USB		= 0x200000, lower order bits are not known */
181 };
182 
183 /* Present on every port in TB_CF_PORT at address zero. */
184 struct tb_regs_port_header {
185 	/* DWORD 0 */
186 	u16 vendor_id;
187 	u16 device_id;
188 	/* DWORD 1 */
189 	u32 first_cap_offset:8;
190 	u32 max_counters:11;
191 	u32 __unknown1:5;
192 	u32 revision:8;
193 	/* DWORD 2 */
194 	enum tb_port_type type:24;
195 	u32 thunderbolt_version:8;
196 	/* DWORD 3 */
197 	u32 __unknown2:20;
198 	u32 port_number:6;
199 	u32 __unknown3:6;
200 	/* DWORD 4 */
201 	u32 nfc_credits;
202 	/* DWORD 5 */
203 	u32 max_in_hop_id:11;
204 	u32 max_out_hop_id:11;
205 	u32 __unknown4:10;
206 	/* DWORD 6 */
207 	u32 __unknown5;
208 	/* DWORD 7 */
209 	u32 __unknown6;
210 
211 } __packed;
212 
213 /* Hop register from TB_CFG_HOPS. 8 byte per entry. */
214 struct tb_regs_hop {
215 	/* DWORD 0 */
216 	u32 next_hop:11; /*
217 			  * hop to take after sending the packet through
218 			  * out_port (on the incoming port of the next switch)
219 			  */
220 	u32 out_port:6; /* next port of the path (on the same switch) */
221 	u32 initial_credits:8;
222 	u32 unknown1:6; /* set to zero */
223 	bool enable:1;
224 
225 	/* DWORD 1 */
226 	u32 weight:4;
227 	u32 unknown2:4; /* set to zero */
228 	u32 priority:3;
229 	bool drop_packages:1;
230 	u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
231 	bool counter_enable:1;
232 	bool ingress_fc:1;
233 	bool egress_fc:1;
234 	bool ingress_shared_buffer:1;
235 	bool egress_shared_buffer:1;
236 	u32 unknown3:4; /* set to zero */
237 } __packed;
238 
239 
240 #endif
241