Searched refs:TEGRA_DIVIDER_ROUND_UP (Results 1 – 10 of 10) sorted by relevance
| /linux-4.19.296/drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 149 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
156 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
163 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
169 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
175 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
183 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
190 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
197 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
204 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
211 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
[all …]
|
| D | clk-utils.c | 26 if (flags & TEGRA_DIVIDER_ROUND_UP) in div_frac_get()
|
| D | clk-tegra20.c | 149 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
156 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
647 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
661 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
695 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
|
| D | clk-tegra30.c | 170 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
176 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
183 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
838 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
852 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
|
| D | clk-tegra-audio.c | 205 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
|
| D | clk-sdmmc-mux.c | 123 if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP) in clk_sdmmc_mux_determine_rate()
|
| D | clk-tegra210.c | 2943 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1,
2952 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0);
3035 TEGRA_DIVIDER_ROUND_UP, 0, NULL); in tegra210_periph_clk_init()
3040 TEGRA_DIVIDER_ROUND_UP, 0, NULL); in tegra210_periph_clk_init()
3074 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3136 TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3147 TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3204 TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3244 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
|
| D | clk-tegra114.c | 129 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
939 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
963 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
|
| D | clk.h | 80 #define TEGRA_DIVIDER_ROUND_UP BIT(0) macro
|
| D | clk-tegra124.c | 1064 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
1098 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
|