Searched refs:UTMIPLL_HW_PWRDN_CFG0 (Results 1 – 2 of 2) sorted by relevance
205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro2715 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()2723 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()2731 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()2733 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()2753 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2755 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2809 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2812 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2823 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()[all …]
216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro1763 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1767 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1780 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1783 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1788 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1790 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()