1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 #ifndef __LINUX_ARM_SMCCC_H 15 #define __LINUX_ARM_SMCCC_H 16 17 #include <uapi/linux/const.h> 18 19 /* 20 * This file provides common defines for ARM SMC Calling Convention as 21 * specified in 22 * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html 23 */ 24 25 #define ARM_SMCCC_STD_CALL _AC(0,U) 26 #define ARM_SMCCC_FAST_CALL _AC(1,U) 27 #define ARM_SMCCC_TYPE_SHIFT 31 28 29 #define ARM_SMCCC_SMC_32 0 30 #define ARM_SMCCC_SMC_64 1 31 #define ARM_SMCCC_CALL_CONV_SHIFT 30 32 33 #define ARM_SMCCC_OWNER_MASK 0x3F 34 #define ARM_SMCCC_OWNER_SHIFT 24 35 36 #define ARM_SMCCC_FUNC_MASK 0xFFFF 37 38 #define ARM_SMCCC_IS_FAST_CALL(smc_val) \ 39 ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) 40 #define ARM_SMCCC_IS_64(smc_val) \ 41 ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) 42 #define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) 43 #define ARM_SMCCC_OWNER_NUM(smc_val) \ 44 (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) 45 46 #define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ 47 (((type) << ARM_SMCCC_TYPE_SHIFT) | \ 48 ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ 49 (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ 50 ((func_num) & ARM_SMCCC_FUNC_MASK)) 51 52 #define ARM_SMCCC_OWNER_ARCH 0 53 #define ARM_SMCCC_OWNER_CPU 1 54 #define ARM_SMCCC_OWNER_SIP 2 55 #define ARM_SMCCC_OWNER_OEM 3 56 #define ARM_SMCCC_OWNER_STANDARD 4 57 #define ARM_SMCCC_OWNER_TRUSTED_APP 48 58 #define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 59 #define ARM_SMCCC_OWNER_TRUSTED_OS 50 60 #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 61 62 #define ARM_SMCCC_QUIRK_NONE 0 63 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ 64 65 #define ARM_SMCCC_VERSION_1_0 0x10000 66 #define ARM_SMCCC_VERSION_1_1 0x10001 67 68 #define ARM_SMCCC_VERSION_FUNC_ID \ 69 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 70 ARM_SMCCC_SMC_32, \ 71 0, 0) 72 73 #define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ 74 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 75 ARM_SMCCC_SMC_32, \ 76 0, 1) 77 78 #define ARM_SMCCC_ARCH_WORKAROUND_1 \ 79 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 80 ARM_SMCCC_SMC_32, \ 81 0, 0x8000) 82 83 #define ARM_SMCCC_ARCH_WORKAROUND_2 \ 84 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 85 ARM_SMCCC_SMC_32, \ 86 0, 0x7fff) 87 88 #define ARM_SMCCC_ARCH_WORKAROUND_3 \ 89 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 90 ARM_SMCCC_SMC_32, \ 91 0, 0x3fff) 92 93 #define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED 1 94 95 #ifndef __ASSEMBLY__ 96 97 #include <linux/linkage.h> 98 #include <linux/types.h> 99 100 enum arm_smccc_conduit { 101 SMCCC_CONDUIT_NONE, 102 SMCCC_CONDUIT_SMC, 103 SMCCC_CONDUIT_HVC, 104 }; 105 106 /** 107 * arm_smccc_1_1_get_conduit() 108 * 109 * Returns the conduit to be used for SMCCCv1.1 or later. 110 * 111 * When SMCCCv1.1 is not present, returns SMCCC_CONDUIT_NONE. 112 */ 113 enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void); 114 115 /** 116 * struct arm_smccc_res - Result from SMC/HVC call 117 * @a0-a3 result values from registers 0 to 3 118 */ 119 struct arm_smccc_res { 120 unsigned long a0; 121 unsigned long a1; 122 unsigned long a2; 123 unsigned long a3; 124 }; 125 126 /** 127 * struct arm_smccc_quirk - Contains quirk information 128 * @id: quirk identification 129 * @state: quirk specific information 130 * @a6: Qualcomm quirk entry for returning post-smc call contents of a6 131 */ 132 struct arm_smccc_quirk { 133 int id; 134 union { 135 unsigned long a6; 136 } state; 137 }; 138 139 /** 140 * __arm_smccc_smc() - make SMC calls 141 * @a0-a7: arguments passed in registers 0 to 7 142 * @res: result values from registers 0 to 3 143 * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. 144 * 145 * This function is used to make SMC calls following SMC Calling Convention. 146 * The content of the supplied param are copied to registers 0 to 7 prior 147 * to the SMC instruction. The return values are updated with the content 148 * from register 0 to 3 on return from the SMC instruction. An optional 149 * quirk structure provides vendor specific behavior. 150 */ 151 asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1, 152 unsigned long a2, unsigned long a3, unsigned long a4, 153 unsigned long a5, unsigned long a6, unsigned long a7, 154 struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); 155 156 /** 157 * __arm_smccc_hvc() - make HVC calls 158 * @a0-a7: arguments passed in registers 0 to 7 159 * @res: result values from registers 0 to 3 160 * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. 161 * 162 * This function is used to make HVC calls following SMC Calling 163 * Convention. The content of the supplied param are copied to registers 0 164 * to 7 prior to the HVC instruction. The return values are updated with 165 * the content from register 0 to 3 on return from the HVC instruction. An 166 * optional quirk structure provides vendor specific behavior. 167 */ 168 asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, 169 unsigned long a2, unsigned long a3, unsigned long a4, 170 unsigned long a5, unsigned long a6, unsigned long a7, 171 struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); 172 173 #define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) 174 175 #define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) 176 177 #define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL) 178 179 #define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__) 180 181 /* SMCCC v1.1 implementation madness follows */ 182 #ifdef CONFIG_ARM64 183 184 #define SMCCC_SMC_INST "smc #0" 185 #define SMCCC_HVC_INST "hvc #0" 186 187 #elif defined(CONFIG_ARM) 188 #include <asm/opcodes-sec.h> 189 #include <asm/opcodes-virt.h> 190 191 #define SMCCC_SMC_INST __SMC(0) 192 #define SMCCC_HVC_INST __HVC(0) 193 194 #endif 195 196 #define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x 197 198 #define __count_args(...) \ 199 ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) 200 201 #define __constraint_write_0 \ 202 "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) 203 #define __constraint_write_1 \ 204 "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) 205 #define __constraint_write_2 \ 206 "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) 207 #define __constraint_write_3 \ 208 "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) 209 #define __constraint_write_4 __constraint_write_3 210 #define __constraint_write_5 __constraint_write_4 211 #define __constraint_write_6 __constraint_write_5 212 #define __constraint_write_7 __constraint_write_6 213 214 #define __constraint_read_0 215 #define __constraint_read_1 216 #define __constraint_read_2 217 #define __constraint_read_3 218 #define __constraint_read_4 "r" (r4) 219 #define __constraint_read_5 __constraint_read_4, "r" (r5) 220 #define __constraint_read_6 __constraint_read_5, "r" (r6) 221 #define __constraint_read_7 __constraint_read_6, "r" (r7) 222 223 #define __declare_arg_0(a0, res) \ 224 struct arm_smccc_res *___res = res; \ 225 register unsigned long r0 asm("r0") = (u32)a0; \ 226 register unsigned long r1 asm("r1"); \ 227 register unsigned long r2 asm("r2"); \ 228 register unsigned long r3 asm("r3") 229 230 #define __declare_arg_1(a0, a1, res) \ 231 typeof(a1) __a1 = a1; \ 232 struct arm_smccc_res *___res = res; \ 233 register unsigned long r0 asm("r0") = (u32)a0; \ 234 register unsigned long r1 asm("r1") = __a1; \ 235 register unsigned long r2 asm("r2"); \ 236 register unsigned long r3 asm("r3") 237 238 #define __declare_arg_2(a0, a1, a2, res) \ 239 typeof(a1) __a1 = a1; \ 240 typeof(a2) __a2 = a2; \ 241 struct arm_smccc_res *___res = res; \ 242 register unsigned long r0 asm("r0") = (u32)a0; \ 243 register unsigned long r1 asm("r1") = __a1; \ 244 register unsigned long r2 asm("r2") = __a2; \ 245 register unsigned long r3 asm("r3") 246 247 #define __declare_arg_3(a0, a1, a2, a3, res) \ 248 typeof(a1) __a1 = a1; \ 249 typeof(a2) __a2 = a2; \ 250 typeof(a3) __a3 = a3; \ 251 struct arm_smccc_res *___res = res; \ 252 register unsigned long r0 asm("r0") = (u32)a0; \ 253 register unsigned long r1 asm("r1") = __a1; \ 254 register unsigned long r2 asm("r2") = __a2; \ 255 register unsigned long r3 asm("r3") = __a3 256 257 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ 258 typeof(a4) __a4 = a4; \ 259 __declare_arg_3(a0, a1, a2, a3, res); \ 260 register unsigned long r4 asm("r4") = __a4 261 262 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ 263 typeof(a5) __a5 = a5; \ 264 __declare_arg_4(a0, a1, a2, a3, a4, res); \ 265 register unsigned long r5 asm("r5") = __a5 266 267 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ 268 typeof(a6) __a6 = a6; \ 269 __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ 270 register unsigned long r6 asm("r6") = __a6 271 272 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ 273 typeof(a7) __a7 = a7; \ 274 __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ 275 register unsigned long r7 asm("r7") = __a7 276 277 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) 278 #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) 279 280 #define ___constraints(count) \ 281 : __constraint_write_ ## count \ 282 : __constraint_read_ ## count \ 283 : "memory" 284 #define __constraints(count) ___constraints(count) 285 286 /* 287 * We have an output list that is not necessarily used, and GCC feels 288 * entitled to optimise the whole sequence away. "volatile" is what 289 * makes it stick. 290 */ 291 #define __arm_smccc_1_1(inst, ...) \ 292 do { \ 293 __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ 294 asm volatile(inst "\n" \ 295 __constraints(__count_args(__VA_ARGS__))); \ 296 if (___res) \ 297 *___res = (typeof(*___res)){r0, r1, r2, r3}; \ 298 } while (0) 299 300 /* 301 * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call 302 * 303 * This is a variadic macro taking one to eight source arguments, and 304 * an optional return structure. 305 * 306 * @a0-a7: arguments passed in registers 0 to 7 307 * @res: result values from registers 0 to 3 308 * 309 * This macro is used to make SMC calls following SMC Calling Convention v1.1. 310 * The content of the supplied param are copied to registers 0 to 7 prior 311 * to the SMC instruction. The return values are updated with the content 312 * from register 0 to 3 on return from the SMC instruction if not NULL. 313 */ 314 #define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) 315 316 /* 317 * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call 318 * 319 * This is a variadic macro taking one to eight source arguments, and 320 * an optional return structure. 321 * 322 * @a0-a7: arguments passed in registers 0 to 7 323 * @res: result values from registers 0 to 3 324 * 325 * This macro is used to make HVC calls following SMC Calling Convention v1.1. 326 * The content of the supplied param are copied to registers 0 to 7 prior 327 * to the HVC instruction. The return values are updated with the content 328 * from register 0 to 3 on return from the HVC instruction if not NULL. 329 */ 330 #define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) 331 332 /* Return codes defined in ARM DEN 0070A */ 333 #define SMCCC_RET_SUCCESS 0 334 #define SMCCC_RET_NOT_SUPPORTED -1 335 #define SMCCC_RET_NOT_REQUIRED -2 336 337 /* 338 * Like arm_smccc_1_1* but always returns SMCCC_RET_NOT_SUPPORTED. 339 * Used when the SMCCC conduit is not defined. The empty asm statement 340 * avoids compiler warnings about unused variables. 341 */ 342 #define __fail_smccc_1_1(...) \ 343 do { \ 344 __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ 345 asm ("" __constraints(__count_args(__VA_ARGS__))); \ 346 if (___res) \ 347 ___res->a0 = SMCCC_RET_NOT_SUPPORTED; \ 348 } while (0) 349 350 /* 351 * arm_smccc_1_1_invoke() - make an SMCCC v1.1 compliant call 352 * 353 * This is a variadic macro taking one to eight source arguments, and 354 * an optional return structure. 355 * 356 * @a0-a7: arguments passed in registers 0 to 7 357 * @res: result values from registers 0 to 3 358 * 359 * This macro will make either an HVC call or an SMC call depending on the 360 * current SMCCC conduit. If no valid conduit is available then -1 361 * (SMCCC_RET_NOT_SUPPORTED) is returned in @res.a0 (if supplied). 362 * 363 * The return value also provides the conduit that was used. 364 */ 365 #define arm_smccc_1_1_invoke(...) ({ \ 366 int method = arm_smccc_1_1_get_conduit(); \ 367 switch (method) { \ 368 case SMCCC_CONDUIT_HVC: \ 369 arm_smccc_1_1_hvc(__VA_ARGS__); \ 370 break; \ 371 case SMCCC_CONDUIT_SMC: \ 372 arm_smccc_1_1_smc(__VA_ARGS__); \ 373 break; \ 374 default: \ 375 __fail_smccc_1_1(__VA_ARGS__); \ 376 method = SMCCC_CONDUIT_NONE; \ 377 break; \ 378 } \ 379 method; \ 380 }) 381 382 /* Paravirtualised time calls (defined by ARM DEN0057A) */ 383 #define ARM_SMCCC_HV_PV_TIME_FEATURES \ 384 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 385 ARM_SMCCC_SMC_64, \ 386 ARM_SMCCC_OWNER_STANDARD_HYP, \ 387 0x20) 388 389 #define ARM_SMCCC_HV_PV_TIME_ST \ 390 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 391 ARM_SMCCC_SMC_64, \ 392 ARM_SMCCC_OWNER_STANDARD_HYP, \ 393 0x21) 394 395 #endif /*__ASSEMBLY__*/ 396 #endif /*__LINUX_ARM_SMCCC_H*/ 397