| /linux-4.19.296/drivers/clk/zte/ |
| D | clk.h | 40 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
47 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
55 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
56 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
63 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
71 _parent, \
83 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
89 _parent, \
101 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
110 _parent, \
[all …]
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| /linux-4.19.296/drivers/clk/actions/ |
| D | owl-composite.h | 37 #define OWL_COMP_DIV(_struct, _name, _parent, \ argument
46 _parent, \
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ argument
60 _parent, \
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ argument
75 _parent, \
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ argument
91 _parent, \
97 #define OWL_COMP_PASS(_struct, _name, _parent, \ argument
105 _parent, \
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| D | owl-fixed-factor.h | 16 #define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags) \ argument
21 _parent, \
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| /linux-4.19.296/drivers/clk/renesas/ |
| D | renesas-cpg-mssr.h | 48 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
49 DEF_TYPE(_name, _id, _type, .parent = _parent)
53 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
55 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
57 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
58 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
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| /linux-4.19.296/drivers/clk/sprd/ |
| D | gate.h | 21 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
31 _parent, \
37 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
39 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
43 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
45 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
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| D | pll.h | 64 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
80 _parent, \
86 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
89 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
93 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
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| D | composite.h | 21 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
30 _parent, \
36 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
38 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
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| /linux-4.19.296/drivers/clk/sunxi-ng/ |
| D | ccu_nm.h | 45 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
62 _parent, \
68 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
86 _parent, \
92 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ argument
112 _parent, \
118 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
130 _parent, \
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| D | ccu_div.h | 95 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
105 _parent, \
112 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
115 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
157 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
166 _parent, \
172 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
174 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
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| /linux-4.19.296/drivers/clk/mediatek/ |
| D | clk-mt2701-aud.c | 18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
21 .parent_name = _parent, \
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
30 .parent_name = _parent, \
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
39 .parent_name = _parent, \
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
48 .parent_name = _parent, \
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| D | clk-mt7622-aud.c | 27 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
30 .parent_name = _parent, \
36 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
39 .parent_name = _parent, \
45 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
48 .parent_name = _parent, \
54 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
57 .parent_name = _parent, \
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| D | clk-mtk.h | 37 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
40 .parent = _parent, \
55 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
58 .parent_name = _parent, \
127 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ argument
130 .parent = _parent, \
180 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
183 .parent_name = _parent, \
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| D | clk-mt2712-vdec.c | 35 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
38 .parent_name = _parent, \
44 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
47 .parent_name = _parent, \
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| D | clk-mt2712-mm.c | 41 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
44 .parent_name = _parent, \
50 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
53 .parent_name = _parent, \
59 #define GATE_MM2(_id, _name, _parent, _shift) { \ argument
62 .parent_name = _parent, \
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| D | clk-mt2701-vdec.c | 35 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
38 .parent_name = _parent, \
44 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
47 .parent_name = _parent, \
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| D | clk-mt6797-vdec.c | 35 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
38 .parent_name = _parent, \
44 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
47 .parent_name = _parent, \
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| D | clk-mt8173.c | 630 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
633 .parent_name = _parent, \
669 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
672 .parent_name = _parent, \
678 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
681 .parent_name = _parent, \
745 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
748 .parent_name = _parent, \
776 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
779 .parent_name = _parent, \
[all …]
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| D | clk-mt2701-mm.c | 35 #define GATE_DISP0(_id, _name, _parent, _shift) { \ argument
38 .parent_name = _parent, \
44 #define GATE_DISP1(_id, _name, _parent, _shift) { \ argument
47 .parent_name = _parent, \
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| D | clk-mt7622.c | 60 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ argument
63 .parent_name = _parent, \
69 #define GATE_INFRA(_id, _name, _parent, _shift) { \ argument
72 .parent_name = _parent, \
78 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
81 .parent_name = _parent, \
87 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
90 .parent_name = _parent, \
96 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
99 .parent_name = _parent, \
[all …]
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| D | clk-mt7622-eth.c | 27 #define GATE_ETH(_id, _name, _parent, _shift) { \ argument
30 .parent_name = _parent, \
56 #define GATE_SGMII(_id, _name, _parent, _shift) { \ argument
59 .parent_name = _parent, \
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| D | clk-mt6797-mm.c | 34 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
37 .parent_name = _parent, \
43 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
46 .parent_name = _parent, \
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| D | clk-mt2701-bdp.c | 35 #define GATE_BDP0(_id, _name, _parent, _shift) { \ argument
38 .parent_name = _parent, \
44 #define GATE_BDP1(_id, _name, _parent, _shift) { \ argument
47 .parent_name = _parent, \
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| D | clk-mt7622-hif.c | 27 #define GATE_PCIE(_id, _name, _parent, _shift) { \ argument
30 .parent_name = _parent, \
36 #define GATE_SSUSB(_id, _name, _parent, _shift) { \ argument
39 .parent_name = _parent, \
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| /linux-4.19.296/include/linux/ |
| D | sh_clk.h | 117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ argument
119 .parent = _parent, \
151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
153 .parent = _parent, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
190 .parent = _parent, \
205 #define SH_CLK_FSIDIV(_reg, _parent) \ argument
208 .parent = _parent, \
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| /linux-4.19.296/drivers/clk/uniphier/ |
| D | clk-uniphier.h | 92 #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \ argument
98 .parent_name = (_parent), \
104 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
110 .parent_name = (_parent), \
|