1 /*
2  * AMD 76x Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * Written by Thayne Harbaugh
8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
9  *	http://www.anime.net/~goemon/linux-ecc/
10  *
11  * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
12  *
13  */
14 
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/pci_ids.h>
19 #include <linux/edac.h>
20 #include "edac_module.h"
21 
22 #define EDAC_MOD_STR	"amd76x_edac"
23 
24 #define amd76x_printk(level, fmt, arg...) \
25 	edac_printk(level, "amd76x", fmt, ##arg)
26 
27 #define amd76x_mc_printk(mci, level, fmt, arg...) \
28 	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
29 
30 #define AMD76X_NR_CSROWS 8
31 #define AMD76X_NR_DIMMS  4
32 
33 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
34 
35 #define AMD76X_ECC_MODE_STATUS	0x48	/* Mode and status of ECC (32b)
36 					 *
37 					 * 31:16 reserved
38 					 * 15:14 SERR enabled: x1=ue 1x=ce
39 					 * 13    reserved
40 					 * 12    diag: disabled, enabled
41 					 * 11:10 mode: dis, EC, ECC, ECC+scrub
42 					 *  9:8  status: x1=ue 1x=ce
43 					 *  7:4  UE cs row
44 					 *  3:0  CE cs row
45 					 */
46 
47 #define AMD76X_DRAM_MODE_STATUS	0x58	/* DRAM Mode and status (32b)
48 					 *
49 					 * 31:26 clock disable 5 - 0
50 					 * 25    SDRAM init
51 					 * 24    reserved
52 					 * 23    mode register service
53 					 * 22:21 suspend to RAM
54 					 * 20    burst refresh enable
55 					 * 19    refresh disable
56 					 * 18    reserved
57 					 * 17:16 cycles-per-refresh
58 					 * 15:8  reserved
59 					 *  7:0  x4 mode enable 7 - 0
60 					 */
61 
62 #define AMD76X_MEM_BASE_ADDR	0xC0	/* Memory base address (8 x 32b)
63 					 *
64 					 * 31:23 chip-select base
65 					 * 22:16 reserved
66 					 * 15:7  chip-select mask
67 					 *  6:3  reserved
68 					 *  2:1  address mode
69 					 *  0    chip-select enable
70 					 */
71 
72 struct amd76x_error_info {
73 	u32 ecc_mode_status;
74 };
75 
76 enum amd76x_chips {
77 	AMD761 = 0,
78 	AMD762
79 };
80 
81 struct amd76x_dev_info {
82 	const char *ctl_name;
83 };
84 
85 static const struct amd76x_dev_info amd76x_devs[] = {
86 	[AMD761] = {
87 		.ctl_name = "AMD761"},
88 	[AMD762] = {
89 		.ctl_name = "AMD762"},
90 };
91 
92 static struct edac_pci_ctl_info *amd76x_pci;
93 
94 /**
95  *	amd76x_get_error_info	-	fetch error information
96  *	@mci: Memory controller
97  *	@info: Info to fill in
98  *
99  *	Fetch and store the AMD76x ECC status. Clear pending status
100  *	on the chip so that further errors will be reported
101  */
amd76x_get_error_info(struct mem_ctl_info * mci,struct amd76x_error_info * info)102 static void amd76x_get_error_info(struct mem_ctl_info *mci,
103 				struct amd76x_error_info *info)
104 {
105 	struct pci_dev *pdev;
106 
107 	pdev = to_pci_dev(mci->pdev);
108 	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
109 			&info->ecc_mode_status);
110 
111 	if (info->ecc_mode_status & BIT(8))
112 		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
113 				 (u32) BIT(8), (u32) BIT(8));
114 
115 	if (info->ecc_mode_status & BIT(9))
116 		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
117 				 (u32) BIT(9), (u32) BIT(9));
118 }
119 
120 /**
121  *	amd76x_process_error_info	-	Error check
122  *	@mci: Memory controller
123  *	@info: Previously fetched information from chip
124  *	@handle_errors: 1 if we should do recovery
125  *
126  *	Process the chip state and decide if an error has occurred.
127  *	A return of 1 indicates an error. Also if handle_errors is true
128  *	then attempt to handle and clean up after the error
129  */
amd76x_process_error_info(struct mem_ctl_info * mci,struct amd76x_error_info * info,int handle_errors)130 static int amd76x_process_error_info(struct mem_ctl_info *mci,
131 				struct amd76x_error_info *info,
132 				int handle_errors)
133 {
134 	int error_found;
135 	u32 row;
136 
137 	error_found = 0;
138 
139 	/*
140 	 *      Check for an uncorrectable error
141 	 */
142 	if (info->ecc_mode_status & BIT(8)) {
143 		error_found = 1;
144 
145 		if (handle_errors) {
146 			row = (info->ecc_mode_status >> 4) & 0xf;
147 			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
148 					     mci->csrows[row]->first_page, 0, 0,
149 					     row, 0, -1,
150 					     mci->ctl_name, "");
151 		}
152 	}
153 
154 	/*
155 	 *      Check for a correctable error
156 	 */
157 	if (info->ecc_mode_status & BIT(9)) {
158 		error_found = 1;
159 
160 		if (handle_errors) {
161 			row = info->ecc_mode_status & 0xf;
162 			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
163 					     mci->csrows[row]->first_page, 0, 0,
164 					     row, 0, -1,
165 					     mci->ctl_name, "");
166 		}
167 	}
168 
169 	return error_found;
170 }
171 
172 /**
173  *	amd76x_check	-	Poll the controller
174  *	@mci: Memory controller
175  *
176  *	Called by the poll handlers this function reads the status
177  *	from the controller and checks for errors.
178  */
amd76x_check(struct mem_ctl_info * mci)179 static void amd76x_check(struct mem_ctl_info *mci)
180 {
181 	struct amd76x_error_info info;
182 	edac_dbg(3, "\n");
183 	amd76x_get_error_info(mci, &info);
184 	amd76x_process_error_info(mci, &info, 1);
185 }
186 
amd76x_init_csrows(struct mem_ctl_info * mci,struct pci_dev * pdev,enum edac_type edac_mode)187 static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
188 			enum edac_type edac_mode)
189 {
190 	struct csrow_info *csrow;
191 	struct dimm_info *dimm;
192 	u32 mba, mba_base, mba_mask, dms;
193 	int index;
194 
195 	for (index = 0; index < mci->nr_csrows; index++) {
196 		csrow = mci->csrows[index];
197 		dimm = csrow->channels[0]->dimm;
198 
199 		/* find the DRAM Chip Select Base address and mask */
200 		pci_read_config_dword(pdev,
201 				AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
202 
203 		if (!(mba & BIT(0)))
204 			continue;
205 
206 		mba_base = mba & 0xff800000UL;
207 		mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
208 		pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
209 		csrow->first_page = mba_base >> PAGE_SHIFT;
210 		dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
211 		csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
212 		csrow->page_mask = mba_mask >> PAGE_SHIFT;
213 		dimm->grain = dimm->nr_pages << PAGE_SHIFT;
214 		dimm->mtype = MEM_RDDR;
215 		dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
216 		dimm->edac_mode = edac_mode;
217 	}
218 }
219 
220 /**
221  *	amd76x_probe1	-	Perform set up for detected device
222  *	@pdev; PCI device detected
223  *	@dev_idx: Device type index
224  *
225  *	We have found an AMD76x and now need to set up the memory
226  *	controller status reporting. We configure and set up the
227  *	memory controller reporting and claim the device.
228  */
amd76x_probe1(struct pci_dev * pdev,int dev_idx)229 static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
230 {
231 	static const enum edac_type ems_modes[] = {
232 		EDAC_NONE,
233 		EDAC_EC,
234 		EDAC_SECDED,
235 		EDAC_SECDED
236 	};
237 	struct mem_ctl_info *mci;
238 	struct edac_mc_layer layers[2];
239 	u32 ems;
240 	u32 ems_mode;
241 	struct amd76x_error_info discard;
242 
243 	edac_dbg(0, "\n");
244 	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
245 	ems_mode = (ems >> 10) & 0x3;
246 
247 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
248 	layers[0].size = AMD76X_NR_CSROWS;
249 	layers[0].is_virt_csrow = true;
250 	layers[1].type = EDAC_MC_LAYER_CHANNEL;
251 	layers[1].size = 1;
252 	layers[1].is_virt_csrow = false;
253 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
254 
255 	if (mci == NULL)
256 		return -ENOMEM;
257 
258 	edac_dbg(0, "mci = %p\n", mci);
259 	mci->pdev = &pdev->dev;
260 	mci->mtype_cap = MEM_FLAG_RDDR;
261 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
262 	mci->edac_cap = ems_mode ?
263 		(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
264 	mci->mod_name = EDAC_MOD_STR;
265 	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
266 	mci->dev_name = pci_name(pdev);
267 	mci->edac_check = amd76x_check;
268 	mci->ctl_page_to_phys = NULL;
269 
270 	amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
271 	amd76x_get_error_info(mci, &discard);	/* clear counters */
272 
273 	/* Here we assume that we will never see multiple instances of this
274 	 * type of memory controller.  The ID is therefore hardcoded to 0.
275 	 */
276 	if (edac_mc_add_mc(mci)) {
277 		edac_dbg(3, "failed edac_mc_add_mc()\n");
278 		goto fail;
279 	}
280 
281 	/* allocating generic PCI control info */
282 	amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
283 	if (!amd76x_pci) {
284 		printk(KERN_WARNING
285 			"%s(): Unable to create PCI control\n",
286 			__func__);
287 		printk(KERN_WARNING
288 			"%s(): PCI error report via EDAC not setup\n",
289 			__func__);
290 	}
291 
292 	/* get this far and it's successful */
293 	edac_dbg(3, "success\n");
294 	return 0;
295 
296 fail:
297 	edac_mc_free(mci);
298 	return -ENODEV;
299 }
300 
301 /* returns count (>= 0), or negative on error */
amd76x_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)302 static int amd76x_init_one(struct pci_dev *pdev,
303 			   const struct pci_device_id *ent)
304 {
305 	edac_dbg(0, "\n");
306 
307 	/* don't need to call pci_enable_device() */
308 	return amd76x_probe1(pdev, ent->driver_data);
309 }
310 
311 /**
312  *	amd76x_remove_one	-	driver shutdown
313  *	@pdev: PCI device being handed back
314  *
315  *	Called when the driver is unloaded. Find the matching mci
316  *	structure for the device then delete the mci and free the
317  *	resources.
318  */
amd76x_remove_one(struct pci_dev * pdev)319 static void amd76x_remove_one(struct pci_dev *pdev)
320 {
321 	struct mem_ctl_info *mci;
322 
323 	edac_dbg(0, "\n");
324 
325 	if (amd76x_pci)
326 		edac_pci_release_generic_ctl(amd76x_pci);
327 
328 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
329 		return;
330 
331 	edac_mc_free(mci);
332 }
333 
334 static const struct pci_device_id amd76x_pci_tbl[] = {
335 	{
336 	 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
337 	 AMD762},
338 	{
339 	 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
340 	 AMD761},
341 	{
342 	 0,
343 	 }			/* 0 terminated list. */
344 };
345 
346 MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
347 
348 static struct pci_driver amd76x_driver = {
349 	.name = EDAC_MOD_STR,
350 	.probe = amd76x_init_one,
351 	.remove = amd76x_remove_one,
352 	.id_table = amd76x_pci_tbl,
353 };
354 
amd76x_init(void)355 static int __init amd76x_init(void)
356 {
357        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
358        opstate_init();
359 
360 	return pci_register_driver(&amd76x_driver);
361 }
362 
amd76x_exit(void)363 static void __exit amd76x_exit(void)
364 {
365 	pci_unregister_driver(&amd76x_driver);
366 }
367 
368 module_init(amd76x_init);
369 module_exit(amd76x_exit);
370 
371 MODULE_LICENSE("GPL");
372 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
373 MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
374 
375 module_param(edac_op_state, int, 0444);
376 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
377