Home
last modified time | relevance | path

Searched refs:base (Results 1 – 25 of 1097) sorted by relevance

12345678910>>...44

/linux-4.19.296/drivers/clk/imx/
Dclk-imx7d.c406 void __iomem *base; in imx7d_clocks_init() local
414 base = of_iomap(np, 0); in imx7d_clocks_init()
415 WARN_ON(!base); in imx7d_clocks_init()
418 …clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src… in imx7d_clocks_init()
419 …clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_sr… in imx7d_clocks_init()
420 …clks[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src… in imx7d_clocks_init()
421 …clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_sr… in imx7d_clocks_init()
422 …clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_… in imx7d_clocks_init()
423 …clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass… in imx7d_clocks_init()
425 clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f); in imx7d_clocks_init()
[all …]
Dclk-imx6sll.c82 void __iomem *base; in imx6sll_clocks_init() local
94 base = of_iomap(np, 0); in imx6sll_clocks_init()
96 WARN_ON(!base); in imx6sll_clocks_init()
99 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
100 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
101 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
102 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
103 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
104 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
105 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0)); in imx6sll_clocks_init()
[all …]
Dclk-imx6ul.c125 void __iomem *base; in imx6ul_clocks_init() local
137 base = of_iomap(np, 0); in imx6ul_clocks_init()
139 WARN_ON(!base); in imx6ul_clocks_init()
141 …clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
142 …clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
143 …clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
144 …clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
145 …clks[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
146 …clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
147 …clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
[all …]
Dclk-imx6sx.c136 void __iomem *base; in imx6sx_clocks_init() local
152 base = of_iomap(np, 0); in imx6sx_clocks_init()
153 WARN_ON(!base); in imx6sx_clocks_init()
156 …clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
157 …clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
158 …clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
159 …clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
160 …clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
161 …clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
162 …clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
[all …]
Dclk-imx6sl.c195 void __iomem *base; in imx6sl_clocks_init() local
205 base = of_iomap(np, 0); in imx6sl_clocks_init()
206 WARN_ON(!base); in imx6sl_clocks_init()
207 anatop_base = base; in imx6sl_clocks_init()
209 …clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
210 …clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
211 …clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
212 …clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
213 …clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
214 …clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
[all …]
Dclk-imx6q.c413 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
425 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
426 WARN_ON(!base); in imx6q_clocks_init()
437 …clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
438 …clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
439 …clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
440 …clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
441 …clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
442 …clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
443 …clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
[all …]
Dclk-imx35.c99 void __iomem *base; in _mx35_clocks_init() local
104 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); in _mx35_clocks_init()
105 BUG_ON(!base); in _mx35_clocks_init()
107 pdr0 = __raw_readl(base + MXC_CCM_PDR0); in _mx35_clocks_init()
121 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
122 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
147 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); in _mx35_clocks_init()
148 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); in _mx35_clocks_init()
149 …clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_… in _mx35_clocks_init()
151 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
[all …]
Dclk-imx31.c76 static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) in _mx31_clocks_init() argument
81 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
82 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); in _mx31_clocks_init()
84 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_… in _mx31_clocks_init()
85 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); in _mx31_clocks_init()
86 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
87 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
88 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
89 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); in _mx31_clocks_init()
[all …]
/linux-4.19.296/drivers/isdn/hardware/avm/
Davmcard.h219 static inline unsigned char b1outp(unsigned int base, in b1outp() argument
223 outb(value, base + offset); in b1outp()
224 return inb(base + B1_ANALYSE); in b1outp()
228 static inline int b1_rx_full(unsigned int base) in b1_rx_full() argument
230 return inb(base + B1_INSTAT) & 0x1; in b1_rx_full()
233 static inline unsigned char b1_get_byte(unsigned int base) in b1_get_byte() argument
236 while (!b1_rx_full(base) && time_before(jiffies, stop)); in b1_get_byte()
237 if (b1_rx_full(base)) in b1_get_byte()
238 return inb(base + B1_READ); in b1_get_byte()
239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); in b1_get_byte()
[all …]
/linux-4.19.296/drivers/s390/block/
Ddasd_ioctl.c46 struct dasd_device *base; in dasd_ioctl_enable() local
51 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_enable()
52 if (!base) in dasd_ioctl_enable()
55 dasd_enable_device(base); in dasd_ioctl_enable()
59 (loff_t)get_capacity(base->block->gdp) << 9); in dasd_ioctl_enable()
61 dasd_put_device(base); in dasd_ioctl_enable()
72 struct dasd_device *base; in dasd_ioctl_disable() local
77 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_disable()
78 if (!base) in dasd_ioctl_disable()
88 dasd_set_target_state(base, DASD_STATE_BASIC); in dasd_ioctl_disable()
[all …]
/linux-4.19.296/include/linux/mmc/
Dsh_mmcif.h97 static inline void sh_mmcif_boot_cmd_send(void __iomem *base, in sh_mmcif_boot_cmd_send() argument
100 sh_mmcif_writel(base, MMCIF_CE_INT, 0); in sh_mmcif_boot_cmd_send()
101 sh_mmcif_writel(base, MMCIF_CE_ARG, arg); in sh_mmcif_boot_cmd_send()
102 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); in sh_mmcif_boot_cmd_send()
105 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) in sh_mmcif_boot_cmd_poll() argument
111 tmp = sh_mmcif_readl(base, MMCIF_CE_INT); in sh_mmcif_boot_cmd_poll()
113 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); in sh_mmcif_boot_cmd_poll()
121 static inline int sh_mmcif_boot_cmd(void __iomem *base, in sh_mmcif_boot_cmd() argument
124 sh_mmcif_boot_cmd_send(base, cmd, arg); in sh_mmcif_boot_cmd()
125 return sh_mmcif_boot_cmd_poll(base, 0x00010000); in sh_mmcif_boot_cmd()
[all …]
/linux-4.19.296/drivers/gpio/
Dgpio-winbond.c131 unsigned long base; member
142 static int winbond_sio_enter(unsigned long base) in winbond_sio_enter() argument
144 if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME)) in winbond_sio_enter()
151 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
152 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
157 static void winbond_sio_select_logical(unsigned long base, u8 dev) in winbond_sio_select_logical() argument
159 outb(WB_SIO_REG_LOGICAL, base); in winbond_sio_select_logical()
160 outb(dev, base + 1); in winbond_sio_select_logical()
163 static void winbond_sio_leave(unsigned long base) in winbond_sio_leave() argument
165 outb(WB_SIO_EXT_EXIT_KEY, base); in winbond_sio_leave()
[all …]
/linux-4.19.296/drivers/irqchip/
Dirq-vic.c73 void __iomem *base; member
99 static void vic_init2(void __iomem *base) in vic_init2() argument
104 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); in vic_init2()
108 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2()
114 void __iomem *base = vic->base; in resume_one_vic() local
116 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); in resume_one_vic()
119 vic_init2(base); in resume_one_vic()
121 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
122 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic()
125 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic()
[all …]
Dirq-sirfsoc.c37 static __init void sirfsoc_alloc_gc(void __iomem *base) in sirfsoc_alloc_gc() argument
51 gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET; in sirfsoc_alloc_gc()
61 void __iomem *base = sirfsoc_irq_get_regbase(); in sirfsoc_handle_irq() local
64 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); in sirfsoc_handle_irq()
71 void __iomem *base = of_iomap(np, 0); in sirfsoc_irq_init() local
72 if (!base) in sirfsoc_irq_init()
76 &irq_generic_chip_ops, base); in sirfsoc_irq_init()
77 sirfsoc_alloc_gc(base); in sirfsoc_irq_init()
79 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_init()
80 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_init()
[all …]
Dirq-vt8500.c75 void __iomem *base; /* IO Memory base address */ member
86 void __iomem *base = priv->base; in vt8500_irq_mask() local
87 void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4); in vt8500_irq_mask()
91 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; in vt8500_irq_mask()
98 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask()
100 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask()
107 void __iomem *base = priv->base; in vt8500_irq_unmask() local
110 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask()
112 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask()
118 void __iomem *base = priv->base; in vt8500_irq_set_type() local
[all …]
/linux-4.19.296/drivers/misc/lkdtm/
Dheap.c28 int *base, *again; in lkdtm_WRITE_AFTER_FREE() local
35 size_t offset = (len / sizeof(*base)) / 2; in lkdtm_WRITE_AFTER_FREE()
37 base = kmalloc(len, GFP_KERNEL); in lkdtm_WRITE_AFTER_FREE()
38 if (!base) in lkdtm_WRITE_AFTER_FREE()
40 pr_info("Allocated memory %p-%p\n", base, &base[offset * 2]); in lkdtm_WRITE_AFTER_FREE()
42 &base[offset]); in lkdtm_WRITE_AFTER_FREE()
43 kfree(base); in lkdtm_WRITE_AFTER_FREE()
44 base[offset] = 0x0abcdef0; in lkdtm_WRITE_AFTER_FREE()
48 if (again != base) in lkdtm_WRITE_AFTER_FREE()
54 int *base, *val, saw; in lkdtm_READ_AFTER_FREE() local
[all …]
/linux-4.19.296/drivers/nvmem/
Dbcm-ocotp.c82 void __iomem *base; member
87 static inline void set_command(void __iomem *base, u32 command) in set_command() argument
89 writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET); in set_command()
92 static inline void set_cpu_address(void __iomem *base, u32 addr) in set_cpu_address() argument
94 writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET); in set_cpu_address()
97 static inline void set_start_bit(void __iomem *base) in set_start_bit() argument
99 writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET); in set_start_bit()
102 static inline void reset_start_bit(void __iomem *base) in reset_start_bit() argument
104 writel(0, base + OTPC_CMD_START_OFFSET); in reset_start_bit()
107 static inline void write_cpu_data(void __iomem *base, u32 value) in write_cpu_data() argument
[all …]
/linux-4.19.296/drivers/rtc/
Drtc-goldfish.c35 void __iomem *base; member
46 void __iomem *base; in goldfish_rtc_read_alarm() local
50 base = rtcdrv->base; in goldfish_rtc_read_alarm()
52 rtc_alarm_low = readl(base + TIMER_ALARM_LOW); in goldfish_rtc_read_alarm()
53 rtc_alarm_high = readl(base + TIMER_ALARM_HIGH); in goldfish_rtc_read_alarm()
61 if (readl(base + TIMER_ALARM_STATUS)) in goldfish_rtc_read_alarm()
76 void __iomem *base; in goldfish_rtc_set_alarm() local
80 base = rtcdrv->base; in goldfish_rtc_set_alarm()
88 writel((rtc_alarm64 >> 32), base + TIMER_ALARM_HIGH); in goldfish_rtc_set_alarm()
89 writel(rtc_alarm64, base + TIMER_ALARM_LOW); in goldfish_rtc_set_alarm()
[all …]
/linux-4.19.296/lib/
Dkstrtox.c24 const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) in _parse_integer_fixup_radix() argument
26 if (*base == 0) { in _parse_integer_fixup_radix()
29 *base = 16; in _parse_integer_fixup_radix()
31 *base = 8; in _parse_integer_fixup_radix()
33 *base = 10; in _parse_integer_fixup_radix()
35 if (*base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') in _parse_integer_fixup_radix()
49 unsigned int _parse_integer_limit(const char *s, unsigned int base, unsigned long long *p, in _parse_integer_limit() argument
69 if (val >= base) in _parse_integer_limit()
76 if (res > div_u64(ULLONG_MAX - val, base)) in _parse_integer_limit()
79 res = res * base + val; in _parse_integer_limit()
[all …]
Dsort.c14 static int alignment_ok(const void *base, int align) in alignment_ok() argument
17 ((unsigned long)base & (align - 1)) == 0; in alignment_ok()
62 void sort(void *base, size_t num, size_t size, in sort() argument
70 if (size == 4 && alignment_ok(base, 4)) in sort()
72 else if (size == 8 && alignment_ok(base, 8)) in sort()
83 cmp_func(base + c, base + c + size) < 0) in sort()
85 if (cmp_func(base + r, base + c) >= 0) in sort()
87 swap_func(base + r, base + c, size); in sort()
93 swap_func(base, base + i, size); in sort()
97 cmp_func(base + c, base + c + size) < 0) in sort()
[all …]
/linux-4.19.296/include/crypto/internal/
Daead.h27 char head[offsetof(struct aead_alg, base)];
28 struct crypto_instance base; member
35 struct crypto_spawn base; member
39 struct crypto_queue base; member
44 return crypto_tfm_ctx(&tfm->base); in crypto_aead_ctx()
50 return container_of(&inst->alg.base, struct crypto_instance, alg); in aead_crypto_instance()
55 return container_of(&inst->alg, struct aead_instance, alg.base); in aead_instance()
60 return aead_instance(crypto_tfm_alg_instance(&aead->base)); in aead_alg_instance()
75 req->base.complete(&req->base, err); in aead_request_complete()
80 return req->base.flags; in aead_request_flags()
[all …]
/linux-4.19.296/drivers/clk/
Dclk-efm32gg.c25 void __iomem *base; in efm32gg_cmu_init() local
39 base = of_iomap(np, 0); in efm32gg_cmu_init()
40 if (!base) { in efm32gg_cmu_init()
49 "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL); in efm32gg_cmu_init()
51 "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL); in efm32gg_cmu_init()
53 "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL); in efm32gg_cmu_init()
55 "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL); in efm32gg_cmu_init()
57 "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL); in efm32gg_cmu_init()
59 "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL); in efm32gg_cmu_init()
61 "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL); in efm32gg_cmu_init()
[all …]
/linux-4.19.296/drivers/clk/samsung/
Dclk-cpu.c139 static void exynos_set_safe_div(void __iomem *base, unsigned long div, in exynos_set_safe_div() argument
144 div0 = readl(base + E4210_DIV_CPU0); in exynos_set_safe_div()
146 writel(div0, base + E4210_DIV_CPU0); in exynos_set_safe_div()
147 wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); in exynos_set_safe_div()
152 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_pre_rate_change() argument
177 if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) in exynos_cpuclk_pre_rate_change()
178 div1 = readl(base + E4210_DIV_CPU1) & in exynos_cpuclk_pre_rate_change()
204 exynos_set_safe_div(base, alt_div, alt_div_mask); in exynos_cpuclk_pre_rate_change()
209 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
210 writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
[all …]
/linux-4.19.296/drivers/clk/davinci/
Dpll-dm365.c60 int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in dm365_pll1_init() argument
64 davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip); in dm365_pll1_init()
66 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); in dm365_pll1_init()
69 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); in dm365_pll1_init()
72 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); in dm365_pll1_init()
75 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base); in dm365_pll1_init()
78 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base); in dm365_pll1_init()
81 davinci_pll_sysclk_register(dev, &pll1_sysclk6, base); in dm365_pll1_init()
83 davinci_pll_sysclk_register(dev, &pll1_sysclk7, base); in dm365_pll1_init()
85 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base); in dm365_pll1_init()
[all …]
/linux-4.19.296/include/sound/
Dsnd_wavefront.h23 unsigned long base; /* I/O port address */ member
52 unsigned long base; /* low i/o port address */ member
55 #define mpu_data_port base
56 #define mpu_command_port base + 1 /* write semantics */
57 #define mpu_status_port base + 1 /* read semantics */
58 #define data_port base + 2
59 #define status_port base + 3 /* read semantics */
60 #define control_port base + 3 /* write semantics */
61 #define block_port base + 4 /* 16 bit, writeonly */
62 #define last_block_port base + 6 /* 16 bit, writeonly */
[all …]

12345678910>>...44