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Searched refs:base_addr (Results 1 – 25 of 51) sorted by relevance

123

/linux-4.19.296/include/trace/events/
Dpercpu.h13 size_t align, void *base_addr, int off, void __percpu *ptr),
15 TP_ARGS(reserved, is_atomic, size, align, base_addr, off, ptr),
22 __field( void *, base_addr )
32 __entry->base_addr = base_addr;
40 __entry->base_addr, __entry->off, __entry->ptr)
45 TP_PROTO(void *base_addr, int off, void __percpu *ptr),
47 TP_ARGS(base_addr, off, ptr),
50 __field( void *, base_addr )
56 __entry->base_addr = base_addr;
62 __entry->base_addr, __entry->off, __entry->ptr)
[all …]
/linux-4.19.296/drivers/irqchip/
Dirq-ftintc010.c27 #define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00) argument
28 #define FT010_IRQ_MASK(base_addr) (base_addr + 0x04) argument
29 #define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08) argument
31 #define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C) argument
33 #define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10) argument
34 #define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14) argument
35 #define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20) argument
36 #define FT010_FIQ_MASK(base_addr) (base_addr + 0x24) argument
37 #define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28) argument
38 #define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C) argument
[all …]
/linux-4.19.296/drivers/char/ipmi/
Dipmi_dmi.c32 static void __init dmi_add_platform_ipmi(unsigned long base_addr, in dmi_add_platform_ipmi() argument
90 info->addr = base_addr; in dmi_add_platform_ipmi()
107 p[pidx++] = PROPERTY_ENTRY_U16("i2c-addr", base_addr); in dmi_add_platform_ipmi()
113 r[0].start = base_addr; in dmi_add_platform_ipmi()
178 unsigned long base_addr) in ipmi_dmi_get_slave_addr() argument
185 info->addr == base_addr) in ipmi_dmi_get_slave_addr()
207 unsigned long base_addr; in dmi_decode_ipmi() local
219 memcpy(&base_addr, data + DMI_IPMI_ADDR, sizeof(unsigned long)); in dmi_decode_ipmi()
220 if (!base_addr) { in dmi_decode_ipmi()
228 base_addr = data[DMI_IPMI_ADDR] >> 1; in dmi_decode_ipmi()
[all …]
Dipmi_dmi.h8 unsigned long base_addr);
/linux-4.19.296/drivers/parisc/
Ddino.c181 void __iomem *base_addr = d->hba.base_addr; in dino_cfg_read() local
184 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, in dino_cfg_read()
189 __raw_writel(v, base_addr + DINO_PCI_ADDR); in dino_cfg_read()
193 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); in dino_cfg_read()
195 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); in dino_cfg_read()
197 *val = readl(base_addr + DINO_CONFIG_DATA); in dino_cfg_read()
216 void __iomem *base_addr = d->hba.base_addr; in dino_cfg_write() local
219 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, in dino_cfg_write()
224 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); in dino_cfg_write()
225 __raw_readl(base_addr + DINO_CONFIG_DATA); in dino_cfg_write()
[all …]
Dlba_pci.c210 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
213 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
219 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
225 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
231 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
240 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
245 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
250 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
255 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
310 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
[all …]
/linux-4.19.296/drivers/gpio/
Dgpio-zynq.c126 void __iomem *base_addr; member
231 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
234 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
239 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
242 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
247 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
287 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
317 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
319 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
346 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
[all …]
Dgpio-ts4800.c27 void __iomem *base_addr; in ts4800_gpio_probe() local
36 base_addr = devm_ioremap_resource(&pdev->dev, res); in ts4800_gpio_probe()
37 if (IS_ERR(base_addr)) in ts4800_gpio_probe()
38 return PTR_ERR(base_addr); in ts4800_gpio_probe()
50 retval = bgpio_init(chip, &pdev->dev, 2, base_addr + INPUT_REG_OFFSET, in ts4800_gpio_probe()
51 base_addr + OUTPUT_REG_OFFSET, NULL, in ts4800_gpio_probe()
52 base_addr + DIRECTION_REG_OFFSET, NULL, 0); in ts4800_gpio_probe()
Dgpio-htc-egpio.c35 void __iomem *base_addr; member
55 writew(value, ei->base_addr + (reg << ei->bus_shift)); in egpio_writew()
60 return readw(ei->base_addr + (reg << ei->bus_shift)); in egpio_readw()
169 ei->base_addr, reg << ei->bus_shift, value); in egpio_get()
303 ei->base_addr = devm_ioremap_nocache(&pdev->dev, res->start, in egpio_probe()
305 if (!ei->base_addr) in egpio_probe()
307 pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr); in egpio_probe()
Dgpio-sch311x.c355 unsigned short base_addr; in sch311x_detect() local
387 base_addr = (sch311x_sio_inb(sio_config_port, 0x60) << 8) | in sch311x_detect()
389 if (!base_addr) { in sch311x_detect()
394 *addr = base_addr; in sch311x_detect()
396 pr_info("Found an SMSC SCH311%d chip at 0x%04x\n", dev_id, base_addr); in sch311x_detect()
/linux-4.19.296/drivers/clk/mediatek/
Dclk-apmixed.c29 void __iomem *base_addr; member
41 return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK; in mtk_ref2usb_tx_is_prepared()
49 val = readl(tx->base_addr); in mtk_ref2usb_tx_prepare()
52 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
56 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
59 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
69 val = readl(tx->base_addr); in mtk_ref2usb_tx_unprepare()
71 writel(val, tx->base_addr); in mtk_ref2usb_tx_unprepare()
91 tx->base_addr = reg; in mtk_clk_register_ref2usb_tx()
Dclk-pll.c46 void __iomem *base_addr; member
64 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
123 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; in mtk_pll_set_rate_regs()
145 con1 = readl(pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
150 writel(con1, pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
259 r = readl(pll->base_addr + REG_CON0); in mtk_pll_prepare()
261 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare()
268 r = readl(pll->base_addr + REG_CON0); in mtk_pll_prepare()
270 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare()
282 r = readl(pll->base_addr + REG_CON0); in mtk_pll_unprepare()
[all …]
/linux-4.19.296/fs/f2fs/
Dxattr.c208 static struct f2fs_xattr_entry *__find_xattr(void *base_addr, in __find_xattr() argument
214 list_for_each_xattr(entry, base_addr) { in __find_xattr()
230 void *base_addr, void **last_addr, int index, in __find_inline_xattr() argument
235 void *max_addr = base_addr + inline_size; in __find_inline_xattr()
237 list_for_each_xattr(entry, base_addr) { in __find_inline_xattr()
306 void **base_addr, int *base_size) in lookup_all_xattrs() argument
361 *base_addr = txattr_addr; in lookup_all_xattrs()
369 void **base_addr) in read_all_xattrs() argument
404 *base_addr = txattr_addr; in read_all_xattrs()
499 void *base_addr = NULL; in f2fs_getxattr() local
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/linux-4.19.296/drivers/misc/
Dqcom-coincell.c25 u32 base_addr; member
47 chgr->base_addr + QCOM_COINCELL_REG_ENABLE, 0); in qcom_coincell_chgr_config()
70 chgr->base_addr + QCOM_COINCELL_REG_RSET, i); in qcom_coincell_chgr_config()
83 chgr->base_addr + QCOM_COINCELL_REG_VSET, j); in qcom_coincell_chgr_config()
89 chgr->base_addr + QCOM_COINCELL_REG_ENABLE, in qcom_coincell_chgr_config()
110 rc = of_property_read_u32(node, "reg", &chgr.base_addr); in qcom_coincell_probe()
/linux-4.19.296/drivers/misc/mic/scif/
Dscif_map.h38 *dma_handle = *dma_handle + scifdev->base_addr; in scif_alloc_coherent()
50 if (scifdev_is_p2p(scifdev) && local > scifdev->base_addr) in scif_free_coherent()
51 local = local - scifdev->base_addr; in scif_free_coherent()
71 *dma_handle = *dma_handle + scifdev->base_addr; in scif_map_single()
84 local = local - scifdev->base_addr; in scif_unmap_single()
130 *dma_handle = *dma_handle + scifdev->base_addr; in scif_map_page()
/linux-4.19.296/drivers/i2c/busses/
Di2c-mlxcpld.c85 u32 base_addr; member
115 u32 addr = priv->base_addr + offs; in mlxcpld_i2c_read_comm()
140 u32 addr = priv->base_addr + offs; in mlxcpld_i2c_write_comm()
506 priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR; in mlxcpld_i2c_probe()
Di2c-eg20t.c740 void __iomem *base_addr; in pch_i2c_probe() local
764 base_addr = pci_iomap(pdev, 1, 0); in pch_i2c_probe()
766 if (base_addr == NULL) { in pch_i2c_probe()
788 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i; in pch_i2c_probe()
823 pci_iounmap(pdev, base_addr); in pch_i2c_probe()
/linux-4.19.296/include/linux/
Dcyclades.h75 void __iomem *base_addr; member
125 void __iomem *base_addr; member
Deisa.h39 unsigned long base_addr; member
Dpercpu.h115 void *base_addr);
/linux-4.19.296/drivers/pci/controller/
Dpcie-iproc.h86 phys_addr_t base_addr; member
Dpcie-iproc-bcma.c57 pcie->base_addr = bdev->addr; in iproc_pcie_bcma_probe()
Dpcie-iproc-platform.c72 pcie->base_addr = reg.start; in iproc_pcie_pltfm_probe()
/linux-4.19.296/virt/kvm/arm/vgic/
Dvgic-mmio-v3.c640 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) in vgic_register_redist_iodev()
662 rd_dev->base_addr = rd_base; in vgic_register_redist_iodev()
677 sgi_dev->base_addr = sgi_base; in vgic_register_redist_iodev()
851 iodev.base_addr = 0; in vgic_v3_has_attr_regs()
856 iodev.base_addr = 0; in vgic_v3_has_attr_regs()
/linux-4.19.296/drivers/misc/mei/
Dhw-txe.c44 static inline u32 mei_txe_reg_read(void __iomem *base_addr, in mei_txe_reg_read() argument
47 return ioread32(base_addr + offset); in mei_txe_reg_read()
57 static inline void mei_txe_reg_write(void __iomem *base_addr, in mei_txe_reg_write() argument
60 iowrite32(value, base_addr + offset); in mei_txe_reg_write()

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