1 /*
2  * Definitions for the NVM Express interface
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14 
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17 
18 #include <linux/types.h>
19 #include <linux/uuid.h>
20 
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN	256
23 
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE		223
26 
27 #define NVMF_TRSVCID_SIZE	32
28 #define NVMF_TRADDR_SIZE	256
29 #define NVMF_TSAS_SIZE		256
30 
31 #define NVME_DISC_SUBSYS_NAME	"nqn.2014-08.org.nvmexpress.discovery"
32 
33 #define NVME_RDMA_IP_PORT	4420
34 
35 #define NVME_NSID_ALL		0xffffffff
36 
37 enum nvme_subsys_type {
38 	NVME_NQN_DISC	= 1,		/* Discovery type target subsystem */
39 	NVME_NQN_NVME	= 2,		/* NVME type target subsystem */
40 };
41 
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
43 enum {
44 	NVMF_ADDR_FAMILY_PCI	= 0,	/* PCIe */
45 	NVMF_ADDR_FAMILY_IP4	= 1,	/* IP4 */
46 	NVMF_ADDR_FAMILY_IP6	= 2,	/* IP6 */
47 	NVMF_ADDR_FAMILY_IB	= 3,	/* InfiniBand */
48 	NVMF_ADDR_FAMILY_FC	= 4,	/* Fibre Channel */
49 };
50 
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
52 enum {
53 	NVMF_TRTYPE_RDMA	= 1,	/* RDMA */
54 	NVMF_TRTYPE_FC		= 2,	/* Fibre Channel */
55 	NVMF_TRTYPE_LOOP	= 254,	/* Reserved for host usage */
56 	NVMF_TRTYPE_MAX,
57 };
58 
59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
60 enum {
61 	NVMF_TREQ_NOT_SPECIFIED	= 0,	/* Not specified */
62 	NVMF_TREQ_REQUIRED	= 1,	/* Required */
63 	NVMF_TREQ_NOT_REQUIRED	= 2,	/* Not Required */
64 };
65 
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67  * RDMA_QPTYPE field
68  */
69 enum {
70 	NVMF_RDMA_QPTYPE_CONNECTED	= 1, /* Reliable Connected */
71 	NVMF_RDMA_QPTYPE_DATAGRAM	= 2, /* Reliable Datagram */
72 };
73 
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75  * RDMA_QPTYPE field
76  */
77 enum {
78 	NVMF_RDMA_PRTYPE_NOT_SPECIFIED	= 1, /* No Provider Specified */
79 	NVMF_RDMA_PRTYPE_IB		= 2, /* InfiniBand */
80 	NVMF_RDMA_PRTYPE_ROCE		= 3, /* InfiniBand RoCE */
81 	NVMF_RDMA_PRTYPE_ROCEV2		= 4, /* InfiniBand RoCEV2 */
82 	NVMF_RDMA_PRTYPE_IWARP		= 5, /* IWARP */
83 };
84 
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86  * entry TSAS RDMA_CMS field
87  */
88 enum {
89 	NVMF_RDMA_CMS_RDMA_CM	= 1, /* Sockets based endpoint addressing */
90 };
91 
92 #define NVME_AQ_DEPTH		32
93 #define NVME_NR_AEN_COMMANDS	1
94 #define NVME_AQ_BLK_MQ_DEPTH	(NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
95 
96 /*
97  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
98  * NVM-Express 1.2 specification, section 4.1.2.
99  */
100 #define NVME_AQ_MQ_TAG_DEPTH	(NVME_AQ_BLK_MQ_DEPTH - 1)
101 
102 enum {
103 	NVME_REG_CAP	= 0x0000,	/* Controller Capabilities */
104 	NVME_REG_VS	= 0x0008,	/* Version */
105 	NVME_REG_INTMS	= 0x000c,	/* Interrupt Mask Set */
106 	NVME_REG_INTMC	= 0x0010,	/* Interrupt Mask Clear */
107 	NVME_REG_CC	= 0x0014,	/* Controller Configuration */
108 	NVME_REG_CSTS	= 0x001c,	/* Controller Status */
109 	NVME_REG_NSSR	= 0x0020,	/* NVM Subsystem Reset */
110 	NVME_REG_AQA	= 0x0024,	/* Admin Queue Attributes */
111 	NVME_REG_ASQ	= 0x0028,	/* Admin SQ Base Address */
112 	NVME_REG_ACQ	= 0x0030,	/* Admin CQ Base Address */
113 	NVME_REG_CMBLOC = 0x0038,	/* Controller Memory Buffer Location */
114 	NVME_REG_CMBSZ	= 0x003c,	/* Controller Memory Buffer Size */
115 	NVME_REG_DBS	= 0x1000,	/* SQ 0 Tail Doorbell */
116 };
117 
118 #define NVME_CAP_MQES(cap)	((cap) & 0xffff)
119 #define NVME_CAP_TIMEOUT(cap)	(((cap) >> 24) & 0xff)
120 #define NVME_CAP_STRIDE(cap)	(((cap) >> 32) & 0xf)
121 #define NVME_CAP_NSSRC(cap)	(((cap) >> 36) & 0x1)
122 #define NVME_CAP_MPSMIN(cap)	(((cap) >> 48) & 0xf)
123 #define NVME_CAP_MPSMAX(cap)	(((cap) >> 52) & 0xf)
124 
125 #define NVME_CMB_BIR(cmbloc)	((cmbloc) & 0x7)
126 #define NVME_CMB_OFST(cmbloc)	(((cmbloc) >> 12) & 0xfffff)
127 
128 enum {
129 	NVME_CMBSZ_SQS		= 1 << 0,
130 	NVME_CMBSZ_CQS		= 1 << 1,
131 	NVME_CMBSZ_LISTS	= 1 << 2,
132 	NVME_CMBSZ_RDS		= 1 << 3,
133 	NVME_CMBSZ_WDS		= 1 << 4,
134 
135 	NVME_CMBSZ_SZ_SHIFT	= 12,
136 	NVME_CMBSZ_SZ_MASK	= 0xfffff,
137 
138 	NVME_CMBSZ_SZU_SHIFT	= 8,
139 	NVME_CMBSZ_SZU_MASK	= 0xf,
140 };
141 
142 /*
143  * Submission and Completion Queue Entry Sizes for the NVM command set.
144  * (In bytes and specified as a power of two (2^n)).
145  */
146 #define NVME_NVM_IOSQES		6
147 #define NVME_NVM_IOCQES		4
148 
149 enum {
150 	NVME_CC_ENABLE		= 1 << 0,
151 	NVME_CC_CSS_NVM		= 0 << 4,
152 	NVME_CC_EN_SHIFT	= 0,
153 	NVME_CC_CSS_SHIFT	= 4,
154 	NVME_CC_MPS_SHIFT	= 7,
155 	NVME_CC_AMS_SHIFT	= 11,
156 	NVME_CC_SHN_SHIFT	= 14,
157 	NVME_CC_IOSQES_SHIFT	= 16,
158 	NVME_CC_IOCQES_SHIFT	= 20,
159 	NVME_CC_AMS_RR		= 0 << NVME_CC_AMS_SHIFT,
160 	NVME_CC_AMS_WRRU	= 1 << NVME_CC_AMS_SHIFT,
161 	NVME_CC_AMS_VS		= 7 << NVME_CC_AMS_SHIFT,
162 	NVME_CC_SHN_NONE	= 0 << NVME_CC_SHN_SHIFT,
163 	NVME_CC_SHN_NORMAL	= 1 << NVME_CC_SHN_SHIFT,
164 	NVME_CC_SHN_ABRUPT	= 2 << NVME_CC_SHN_SHIFT,
165 	NVME_CC_SHN_MASK	= 3 << NVME_CC_SHN_SHIFT,
166 	NVME_CC_IOSQES		= NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
167 	NVME_CC_IOCQES		= NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
168 	NVME_CSTS_RDY		= 1 << 0,
169 	NVME_CSTS_CFS		= 1 << 1,
170 	NVME_CSTS_NSSRO		= 1 << 4,
171 	NVME_CSTS_PP		= 1 << 5,
172 	NVME_CSTS_SHST_NORMAL	= 0 << 2,
173 	NVME_CSTS_SHST_OCCUR	= 1 << 2,
174 	NVME_CSTS_SHST_CMPLT	= 2 << 2,
175 	NVME_CSTS_SHST_MASK	= 3 << 2,
176 };
177 
178 struct nvme_id_power_state {
179 	__le16			max_power;	/* centiwatts */
180 	__u8			rsvd2;
181 	__u8			flags;
182 	__le32			entry_lat;	/* microseconds */
183 	__le32			exit_lat;	/* microseconds */
184 	__u8			read_tput;
185 	__u8			read_lat;
186 	__u8			write_tput;
187 	__u8			write_lat;
188 	__le16			idle_power;
189 	__u8			idle_scale;
190 	__u8			rsvd19;
191 	__le16			active_power;
192 	__u8			active_work_scale;
193 	__u8			rsvd23[9];
194 };
195 
196 enum {
197 	NVME_PS_FLAGS_MAX_POWER_SCALE	= 1 << 0,
198 	NVME_PS_FLAGS_NON_OP_STATE	= 1 << 1,
199 };
200 
201 struct nvme_id_ctrl {
202 	__le16			vid;
203 	__le16			ssvid;
204 	char			sn[20];
205 	char			mn[40];
206 	char			fr[8];
207 	__u8			rab;
208 	__u8			ieee[3];
209 	__u8			cmic;
210 	__u8			mdts;
211 	__le16			cntlid;
212 	__le32			ver;
213 	__le32			rtd3r;
214 	__le32			rtd3e;
215 	__le32			oaes;
216 	__le32			ctratt;
217 	__u8			rsvd100[156];
218 	__le16			oacs;
219 	__u8			acl;
220 	__u8			aerl;
221 	__u8			frmw;
222 	__u8			lpa;
223 	__u8			elpe;
224 	__u8			npss;
225 	__u8			avscc;
226 	__u8			apsta;
227 	__le16			wctemp;
228 	__le16			cctemp;
229 	__le16			mtfa;
230 	__le32			hmpre;
231 	__le32			hmmin;
232 	__u8			tnvmcap[16];
233 	__u8			unvmcap[16];
234 	__le32			rpmbs;
235 	__le16			edstt;
236 	__u8			dsto;
237 	__u8			fwug;
238 	__le16			kas;
239 	__le16			hctma;
240 	__le16			mntmt;
241 	__le16			mxtmt;
242 	__le32			sanicap;
243 	__le32			hmminds;
244 	__le16			hmmaxd;
245 	__u8			rsvd338[4];
246 	__u8			anatt;
247 	__u8			anacap;
248 	__le32			anagrpmax;
249 	__le32			nanagrpid;
250 	__u8			rsvd352[160];
251 	__u8			sqes;
252 	__u8			cqes;
253 	__le16			maxcmd;
254 	__le32			nn;
255 	__le16			oncs;
256 	__le16			fuses;
257 	__u8			fna;
258 	__u8			vwc;
259 	__le16			awun;
260 	__le16			awupf;
261 	__u8			nvscc;
262 	__u8			nwpc;
263 	__le16			acwu;
264 	__u8			rsvd534[2];
265 	__le32			sgls;
266 	__le32			mnan;
267 	__u8			rsvd544[224];
268 	char			subnqn[256];
269 	__u8			rsvd1024[768];
270 	__le32			ioccsz;
271 	__le32			iorcsz;
272 	__le16			icdoff;
273 	__u8			ctrattr;
274 	__u8			msdbd;
275 	__u8			rsvd1804[244];
276 	struct nvme_id_power_state	psd[32];
277 	__u8			vs[1024];
278 };
279 
280 enum {
281 	NVME_CTRL_ONCS_COMPARE			= 1 << 0,
282 	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE	= 1 << 1,
283 	NVME_CTRL_ONCS_DSM			= 1 << 2,
284 	NVME_CTRL_ONCS_WRITE_ZEROES		= 1 << 3,
285 	NVME_CTRL_ONCS_TIMESTAMP		= 1 << 6,
286 	NVME_CTRL_VWC_PRESENT			= 1 << 0,
287 	NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
288 	NVME_CTRL_OACS_DIRECTIVES		= 1 << 5,
289 	NVME_CTRL_OACS_DBBUF_SUPP		= 1 << 8,
290 	NVME_CTRL_LPA_CMD_EFFECTS_LOG		= 1 << 1,
291 };
292 
293 struct nvme_lbaf {
294 	__le16			ms;
295 	__u8			ds;
296 	__u8			rp;
297 };
298 
299 struct nvme_id_ns {
300 	__le64			nsze;
301 	__le64			ncap;
302 	__le64			nuse;
303 	__u8			nsfeat;
304 	__u8			nlbaf;
305 	__u8			flbas;
306 	__u8			mc;
307 	__u8			dpc;
308 	__u8			dps;
309 	__u8			nmic;
310 	__u8			rescap;
311 	__u8			fpi;
312 	__u8			rsvd33;
313 	__le16			nawun;
314 	__le16			nawupf;
315 	__le16			nacwu;
316 	__le16			nabsn;
317 	__le16			nabo;
318 	__le16			nabspf;
319 	__le16			noiob;
320 	__u8			nvmcap[16];
321 	__u8			rsvd64[28];
322 	__le32			anagrpid;
323 	__u8			rsvd96[3];
324 	__u8			nsattr;
325 	__u8			rsvd100[4];
326 	__u8			nguid[16];
327 	__u8			eui64[8];
328 	struct nvme_lbaf	lbaf[16];
329 	__u8			rsvd192[192];
330 	__u8			vs[3712];
331 };
332 
333 enum {
334 	NVME_ID_CNS_NS			= 0x00,
335 	NVME_ID_CNS_CTRL		= 0x01,
336 	NVME_ID_CNS_NS_ACTIVE_LIST	= 0x02,
337 	NVME_ID_CNS_NS_DESC_LIST	= 0x03,
338 	NVME_ID_CNS_NS_PRESENT_LIST	= 0x10,
339 	NVME_ID_CNS_NS_PRESENT		= 0x11,
340 	NVME_ID_CNS_CTRL_NS_LIST	= 0x12,
341 	NVME_ID_CNS_CTRL_LIST		= 0x13,
342 };
343 
344 enum {
345 	NVME_DIR_IDENTIFY		= 0x00,
346 	NVME_DIR_STREAMS		= 0x01,
347 	NVME_DIR_SND_ID_OP_ENABLE	= 0x01,
348 	NVME_DIR_SND_ST_OP_REL_ID	= 0x01,
349 	NVME_DIR_SND_ST_OP_REL_RSC	= 0x02,
350 	NVME_DIR_RCV_ID_OP_PARAM	= 0x01,
351 	NVME_DIR_RCV_ST_OP_PARAM	= 0x01,
352 	NVME_DIR_RCV_ST_OP_STATUS	= 0x02,
353 	NVME_DIR_RCV_ST_OP_RESOURCE	= 0x03,
354 	NVME_DIR_ENDIR			= 0x01,
355 };
356 
357 enum {
358 	NVME_NS_FEAT_THIN	= 1 << 0,
359 	NVME_NS_FLBAS_LBA_MASK	= 0xf,
360 	NVME_NS_FLBAS_META_EXT	= 0x10,
361 	NVME_LBAF_RP_BEST	= 0,
362 	NVME_LBAF_RP_BETTER	= 1,
363 	NVME_LBAF_RP_GOOD	= 2,
364 	NVME_LBAF_RP_DEGRADED	= 3,
365 	NVME_NS_DPC_PI_LAST	= 1 << 4,
366 	NVME_NS_DPC_PI_FIRST	= 1 << 3,
367 	NVME_NS_DPC_PI_TYPE3	= 1 << 2,
368 	NVME_NS_DPC_PI_TYPE2	= 1 << 1,
369 	NVME_NS_DPC_PI_TYPE1	= 1 << 0,
370 	NVME_NS_DPS_PI_FIRST	= 1 << 3,
371 	NVME_NS_DPS_PI_MASK	= 0x7,
372 	NVME_NS_DPS_PI_TYPE1	= 1,
373 	NVME_NS_DPS_PI_TYPE2	= 2,
374 	NVME_NS_DPS_PI_TYPE3	= 3,
375 };
376 
377 struct nvme_ns_id_desc {
378 	__u8 nidt;
379 	__u8 nidl;
380 	__le16 reserved;
381 };
382 
383 #define NVME_NIDT_EUI64_LEN	8
384 #define NVME_NIDT_NGUID_LEN	16
385 #define NVME_NIDT_UUID_LEN	16
386 
387 enum {
388 	NVME_NIDT_EUI64		= 0x01,
389 	NVME_NIDT_NGUID		= 0x02,
390 	NVME_NIDT_UUID		= 0x03,
391 };
392 
393 struct nvme_smart_log {
394 	__u8			critical_warning;
395 	__u8			temperature[2];
396 	__u8			avail_spare;
397 	__u8			spare_thresh;
398 	__u8			percent_used;
399 	__u8			rsvd6[26];
400 	__u8			data_units_read[16];
401 	__u8			data_units_written[16];
402 	__u8			host_reads[16];
403 	__u8			host_writes[16];
404 	__u8			ctrl_busy_time[16];
405 	__u8			power_cycles[16];
406 	__u8			power_on_hours[16];
407 	__u8			unsafe_shutdowns[16];
408 	__u8			media_errors[16];
409 	__u8			num_err_log_entries[16];
410 	__le32			warning_temp_time;
411 	__le32			critical_comp_time;
412 	__le16			temp_sensor[8];
413 	__u8			rsvd216[296];
414 };
415 
416 struct nvme_fw_slot_info_log {
417 	__u8			afi;
418 	__u8			rsvd1[7];
419 	__le64			frs[7];
420 	__u8			rsvd64[448];
421 };
422 
423 enum {
424 	NVME_CMD_EFFECTS_CSUPP		= 1 << 0,
425 	NVME_CMD_EFFECTS_LBCC		= 1 << 1,
426 	NVME_CMD_EFFECTS_NCC		= 1 << 2,
427 	NVME_CMD_EFFECTS_NIC		= 1 << 3,
428 	NVME_CMD_EFFECTS_CCC		= 1 << 4,
429 	NVME_CMD_EFFECTS_CSE_MASK	= 3 << 16,
430 };
431 
432 struct nvme_effects_log {
433 	__le32 acs[256];
434 	__le32 iocs[256];
435 	__u8   resv[2048];
436 };
437 
438 enum nvme_ana_state {
439 	NVME_ANA_OPTIMIZED		= 0x01,
440 	NVME_ANA_NONOPTIMIZED		= 0x02,
441 	NVME_ANA_INACCESSIBLE		= 0x03,
442 	NVME_ANA_PERSISTENT_LOSS	= 0x04,
443 	NVME_ANA_CHANGE			= 0x0f,
444 };
445 
446 struct nvme_ana_group_desc {
447 	__le32	grpid;
448 	__le32	nnsids;
449 	__le64	chgcnt;
450 	__u8	state;
451 	__u8	rsvd17[15];
452 	__le32	nsids[];
453 };
454 
455 /* flag for the log specific field of the ANA log */
456 #define NVME_ANA_LOG_RGO	(1 << 0)
457 
458 struct nvme_ana_rsp_hdr {
459 	__le64	chgcnt;
460 	__le16	ngrps;
461 	__le16	rsvd10[3];
462 };
463 
464 enum {
465 	NVME_SMART_CRIT_SPARE		= 1 << 0,
466 	NVME_SMART_CRIT_TEMPERATURE	= 1 << 1,
467 	NVME_SMART_CRIT_RELIABILITY	= 1 << 2,
468 	NVME_SMART_CRIT_MEDIA		= 1 << 3,
469 	NVME_SMART_CRIT_VOLATILE_MEMORY	= 1 << 4,
470 };
471 
472 enum {
473 	NVME_AER_ERROR			= 0,
474 	NVME_AER_SMART			= 1,
475 	NVME_AER_NOTICE			= 2,
476 	NVME_AER_CSS			= 6,
477 	NVME_AER_VS			= 7,
478 };
479 
480 enum {
481 	NVME_AER_NOTICE_NS_CHANGED	= 0x00,
482 	NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
483 	NVME_AER_NOTICE_ANA		= 0x03,
484 };
485 
486 enum {
487 	NVME_AEN_CFG_NS_ATTR		= 1 << 8,
488 	NVME_AEN_CFG_FW_ACT		= 1 << 9,
489 	NVME_AEN_CFG_ANA_CHANGE		= 1 << 11,
490 };
491 
492 struct nvme_lba_range_type {
493 	__u8			type;
494 	__u8			attributes;
495 	__u8			rsvd2[14];
496 	__u64			slba;
497 	__u64			nlb;
498 	__u8			guid[16];
499 	__u8			rsvd48[16];
500 };
501 
502 enum {
503 	NVME_LBART_TYPE_FS	= 0x01,
504 	NVME_LBART_TYPE_RAID	= 0x02,
505 	NVME_LBART_TYPE_CACHE	= 0x03,
506 	NVME_LBART_TYPE_SWAP	= 0x04,
507 
508 	NVME_LBART_ATTRIB_TEMP	= 1 << 0,
509 	NVME_LBART_ATTRIB_HIDE	= 1 << 1,
510 };
511 
512 struct nvme_reservation_status {
513 	__le32	gen;
514 	__u8	rtype;
515 	__u8	regctl[2];
516 	__u8	resv5[2];
517 	__u8	ptpls;
518 	__u8	resv10[13];
519 	struct {
520 		__le16	cntlid;
521 		__u8	rcsts;
522 		__u8	resv3[5];
523 		__le64	hostid;
524 		__le64	rkey;
525 	} regctl_ds[];
526 };
527 
528 enum nvme_async_event_type {
529 	NVME_AER_TYPE_ERROR	= 0,
530 	NVME_AER_TYPE_SMART	= 1,
531 	NVME_AER_TYPE_NOTICE	= 2,
532 };
533 
534 /* I/O commands */
535 
536 enum nvme_opcode {
537 	nvme_cmd_flush		= 0x00,
538 	nvme_cmd_write		= 0x01,
539 	nvme_cmd_read		= 0x02,
540 	nvme_cmd_write_uncor	= 0x04,
541 	nvme_cmd_compare	= 0x05,
542 	nvme_cmd_write_zeroes	= 0x08,
543 	nvme_cmd_dsm		= 0x09,
544 	nvme_cmd_resv_register	= 0x0d,
545 	nvme_cmd_resv_report	= 0x0e,
546 	nvme_cmd_resv_acquire	= 0x11,
547 	nvme_cmd_resv_release	= 0x15,
548 };
549 
550 /*
551  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
552  *
553  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
554  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
555  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
556  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
557  *                            request subtype
558  */
559 enum {
560 	NVME_SGL_FMT_ADDRESS		= 0x00,
561 	NVME_SGL_FMT_OFFSET		= 0x01,
562 	NVME_SGL_FMT_TRANSPORT_A	= 0x0A,
563 	NVME_SGL_FMT_INVALIDATE		= 0x0f,
564 };
565 
566 /*
567  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
568  *
569  * For struct nvme_sgl_desc:
570  *   @NVME_SGL_FMT_DATA_DESC:		data block descriptor
571  *   @NVME_SGL_FMT_SEG_DESC:		sgl segment descriptor
572  *   @NVME_SGL_FMT_LAST_SEG_DESC:	last sgl segment descriptor
573  *
574  * For struct nvme_keyed_sgl_desc:
575  *   @NVME_KEY_SGL_FMT_DATA_DESC:	keyed data block descriptor
576  *
577  * Transport-specific SGL types:
578  *   @NVME_TRANSPORT_SGL_DATA_DESC:	Transport SGL data dlock descriptor
579  */
580 enum {
581 	NVME_SGL_FMT_DATA_DESC		= 0x00,
582 	NVME_SGL_FMT_SEG_DESC		= 0x02,
583 	NVME_SGL_FMT_LAST_SEG_DESC	= 0x03,
584 	NVME_KEY_SGL_FMT_DATA_DESC	= 0x04,
585 	NVME_TRANSPORT_SGL_DATA_DESC	= 0x05,
586 };
587 
588 struct nvme_sgl_desc {
589 	__le64	addr;
590 	__le32	length;
591 	__u8	rsvd[3];
592 	__u8	type;
593 };
594 
595 struct nvme_keyed_sgl_desc {
596 	__le64	addr;
597 	__u8	length[3];
598 	__u8	key[4];
599 	__u8	type;
600 };
601 
602 union nvme_data_ptr {
603 	struct {
604 		__le64	prp1;
605 		__le64	prp2;
606 	};
607 	struct nvme_sgl_desc	sgl;
608 	struct nvme_keyed_sgl_desc ksgl;
609 };
610 
611 /*
612  * Lowest two bits of our flags field (FUSE field in the spec):
613  *
614  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
615  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
616  *
617  * Highest two bits in our flags field (PSDT field in the spec):
618  *
619  * @NVME_CMD_PSDT_SGL_METABUF:	Use SGLS for this transfer,
620  *	If used, MPTR contains addr of single physical buffer (byte aligned).
621  * @NVME_CMD_PSDT_SGL_METASEG:	Use SGLS for this transfer,
622  *	If used, MPTR contains an address of an SGL segment containing
623  *	exactly 1 SGL descriptor (qword aligned).
624  */
625 enum {
626 	NVME_CMD_FUSE_FIRST	= (1 << 0),
627 	NVME_CMD_FUSE_SECOND	= (1 << 1),
628 
629 	NVME_CMD_SGL_METABUF	= (1 << 6),
630 	NVME_CMD_SGL_METASEG	= (1 << 7),
631 	NVME_CMD_SGL_ALL	= NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
632 };
633 
634 struct nvme_common_command {
635 	__u8			opcode;
636 	__u8			flags;
637 	__u16			command_id;
638 	__le32			nsid;
639 	__le32			cdw2[2];
640 	__le64			metadata;
641 	union nvme_data_ptr	dptr;
642 	__le32			cdw10[6];
643 };
644 
645 struct nvme_rw_command {
646 	__u8			opcode;
647 	__u8			flags;
648 	__u16			command_id;
649 	__le32			nsid;
650 	__u64			rsvd2;
651 	__le64			metadata;
652 	union nvme_data_ptr	dptr;
653 	__le64			slba;
654 	__le16			length;
655 	__le16			control;
656 	__le32			dsmgmt;
657 	__le32			reftag;
658 	__le16			apptag;
659 	__le16			appmask;
660 };
661 
662 enum {
663 	NVME_RW_LR			= 1 << 15,
664 	NVME_RW_FUA			= 1 << 14,
665 	NVME_RW_DSM_FREQ_UNSPEC		= 0,
666 	NVME_RW_DSM_FREQ_TYPICAL	= 1,
667 	NVME_RW_DSM_FREQ_RARE		= 2,
668 	NVME_RW_DSM_FREQ_READS		= 3,
669 	NVME_RW_DSM_FREQ_WRITES		= 4,
670 	NVME_RW_DSM_FREQ_RW		= 5,
671 	NVME_RW_DSM_FREQ_ONCE		= 6,
672 	NVME_RW_DSM_FREQ_PREFETCH	= 7,
673 	NVME_RW_DSM_FREQ_TEMP		= 8,
674 	NVME_RW_DSM_LATENCY_NONE	= 0 << 4,
675 	NVME_RW_DSM_LATENCY_IDLE	= 1 << 4,
676 	NVME_RW_DSM_LATENCY_NORM	= 2 << 4,
677 	NVME_RW_DSM_LATENCY_LOW		= 3 << 4,
678 	NVME_RW_DSM_SEQ_REQ		= 1 << 6,
679 	NVME_RW_DSM_COMPRESSED		= 1 << 7,
680 	NVME_RW_PRINFO_PRCHK_REF	= 1 << 10,
681 	NVME_RW_PRINFO_PRCHK_APP	= 1 << 11,
682 	NVME_RW_PRINFO_PRCHK_GUARD	= 1 << 12,
683 	NVME_RW_PRINFO_PRACT		= 1 << 13,
684 	NVME_RW_DTYPE_STREAMS		= 1 << 4,
685 };
686 
687 struct nvme_dsm_cmd {
688 	__u8			opcode;
689 	__u8			flags;
690 	__u16			command_id;
691 	__le32			nsid;
692 	__u64			rsvd2[2];
693 	union nvme_data_ptr	dptr;
694 	__le32			nr;
695 	__le32			attributes;
696 	__u32			rsvd12[4];
697 };
698 
699 enum {
700 	NVME_DSMGMT_IDR		= 1 << 0,
701 	NVME_DSMGMT_IDW		= 1 << 1,
702 	NVME_DSMGMT_AD		= 1 << 2,
703 };
704 
705 #define NVME_DSM_MAX_RANGES	256
706 
707 struct nvme_dsm_range {
708 	__le32			cattr;
709 	__le32			nlb;
710 	__le64			slba;
711 };
712 
713 struct nvme_write_zeroes_cmd {
714 	__u8			opcode;
715 	__u8			flags;
716 	__u16			command_id;
717 	__le32			nsid;
718 	__u64			rsvd2;
719 	__le64			metadata;
720 	union nvme_data_ptr	dptr;
721 	__le64			slba;
722 	__le16			length;
723 	__le16			control;
724 	__le32			dsmgmt;
725 	__le32			reftag;
726 	__le16			apptag;
727 	__le16			appmask;
728 };
729 
730 /* Features */
731 
732 struct nvme_feat_auto_pst {
733 	__le64 entries[32];
734 };
735 
736 enum {
737 	NVME_HOST_MEM_ENABLE	= (1 << 0),
738 	NVME_HOST_MEM_RETURN	= (1 << 1),
739 };
740 
741 /* Admin commands */
742 
743 enum nvme_admin_opcode {
744 	nvme_admin_delete_sq		= 0x00,
745 	nvme_admin_create_sq		= 0x01,
746 	nvme_admin_get_log_page		= 0x02,
747 	nvme_admin_delete_cq		= 0x04,
748 	nvme_admin_create_cq		= 0x05,
749 	nvme_admin_identify		= 0x06,
750 	nvme_admin_abort_cmd		= 0x08,
751 	nvme_admin_set_features		= 0x09,
752 	nvme_admin_get_features		= 0x0a,
753 	nvme_admin_async_event		= 0x0c,
754 	nvme_admin_ns_mgmt		= 0x0d,
755 	nvme_admin_activate_fw		= 0x10,
756 	nvme_admin_download_fw		= 0x11,
757 	nvme_admin_ns_attach		= 0x15,
758 	nvme_admin_keep_alive		= 0x18,
759 	nvme_admin_directive_send	= 0x19,
760 	nvme_admin_directive_recv	= 0x1a,
761 	nvme_admin_dbbuf		= 0x7C,
762 	nvme_admin_format_nvm		= 0x80,
763 	nvme_admin_security_send	= 0x81,
764 	nvme_admin_security_recv	= 0x82,
765 	nvme_admin_sanitize_nvm		= 0x84,
766 };
767 
768 enum {
769 	NVME_QUEUE_PHYS_CONTIG	= (1 << 0),
770 	NVME_CQ_IRQ_ENABLED	= (1 << 1),
771 	NVME_SQ_PRIO_URGENT	= (0 << 1),
772 	NVME_SQ_PRIO_HIGH	= (1 << 1),
773 	NVME_SQ_PRIO_MEDIUM	= (2 << 1),
774 	NVME_SQ_PRIO_LOW	= (3 << 1),
775 	NVME_FEAT_ARBITRATION	= 0x01,
776 	NVME_FEAT_POWER_MGMT	= 0x02,
777 	NVME_FEAT_LBA_RANGE	= 0x03,
778 	NVME_FEAT_TEMP_THRESH	= 0x04,
779 	NVME_FEAT_ERR_RECOVERY	= 0x05,
780 	NVME_FEAT_VOLATILE_WC	= 0x06,
781 	NVME_FEAT_NUM_QUEUES	= 0x07,
782 	NVME_FEAT_IRQ_COALESCE	= 0x08,
783 	NVME_FEAT_IRQ_CONFIG	= 0x09,
784 	NVME_FEAT_WRITE_ATOMIC	= 0x0a,
785 	NVME_FEAT_ASYNC_EVENT	= 0x0b,
786 	NVME_FEAT_AUTO_PST	= 0x0c,
787 	NVME_FEAT_HOST_MEM_BUF	= 0x0d,
788 	NVME_FEAT_TIMESTAMP	= 0x0e,
789 	NVME_FEAT_KATO		= 0x0f,
790 	NVME_FEAT_HCTM		= 0x10,
791 	NVME_FEAT_NOPSC		= 0x11,
792 	NVME_FEAT_RRL		= 0x12,
793 	NVME_FEAT_PLM_CONFIG	= 0x13,
794 	NVME_FEAT_PLM_WINDOW	= 0x14,
795 	NVME_FEAT_SW_PROGRESS	= 0x80,
796 	NVME_FEAT_HOST_ID	= 0x81,
797 	NVME_FEAT_RESV_MASK	= 0x82,
798 	NVME_FEAT_RESV_PERSIST	= 0x83,
799 	NVME_FEAT_WRITE_PROTECT	= 0x84,
800 	NVME_LOG_ERROR		= 0x01,
801 	NVME_LOG_SMART		= 0x02,
802 	NVME_LOG_FW_SLOT	= 0x03,
803 	NVME_LOG_CHANGED_NS	= 0x04,
804 	NVME_LOG_CMD_EFFECTS	= 0x05,
805 	NVME_LOG_ANA		= 0x0c,
806 	NVME_LOG_DISC		= 0x70,
807 	NVME_LOG_RESERVATION	= 0x80,
808 	NVME_FWACT_REPL		= (0 << 3),
809 	NVME_FWACT_REPL_ACTV	= (1 << 3),
810 	NVME_FWACT_ACTV		= (2 << 3),
811 };
812 
813 /* NVMe Namespace Write Protect State */
814 enum {
815 	NVME_NS_NO_WRITE_PROTECT = 0,
816 	NVME_NS_WRITE_PROTECT,
817 	NVME_NS_WRITE_PROTECT_POWER_CYCLE,
818 	NVME_NS_WRITE_PROTECT_PERMANENT,
819 };
820 
821 #define NVME_MAX_CHANGED_NAMESPACES	1024
822 
823 struct nvme_identify {
824 	__u8			opcode;
825 	__u8			flags;
826 	__u16			command_id;
827 	__le32			nsid;
828 	__u64			rsvd2[2];
829 	union nvme_data_ptr	dptr;
830 	__u8			cns;
831 	__u8			rsvd3;
832 	__le16			ctrlid;
833 	__u32			rsvd11[5];
834 };
835 
836 #define NVME_IDENTIFY_DATA_SIZE 4096
837 
838 struct nvme_features {
839 	__u8			opcode;
840 	__u8			flags;
841 	__u16			command_id;
842 	__le32			nsid;
843 	__u64			rsvd2[2];
844 	union nvme_data_ptr	dptr;
845 	__le32			fid;
846 	__le32			dword11;
847 	__le32                  dword12;
848 	__le32                  dword13;
849 	__le32                  dword14;
850 	__le32                  dword15;
851 };
852 
853 struct nvme_host_mem_buf_desc {
854 	__le64			addr;
855 	__le32			size;
856 	__u32			rsvd;
857 };
858 
859 struct nvme_create_cq {
860 	__u8			opcode;
861 	__u8			flags;
862 	__u16			command_id;
863 	__u32			rsvd1[5];
864 	__le64			prp1;
865 	__u64			rsvd8;
866 	__le16			cqid;
867 	__le16			qsize;
868 	__le16			cq_flags;
869 	__le16			irq_vector;
870 	__u32			rsvd12[4];
871 };
872 
873 struct nvme_create_sq {
874 	__u8			opcode;
875 	__u8			flags;
876 	__u16			command_id;
877 	__u32			rsvd1[5];
878 	__le64			prp1;
879 	__u64			rsvd8;
880 	__le16			sqid;
881 	__le16			qsize;
882 	__le16			sq_flags;
883 	__le16			cqid;
884 	__u32			rsvd12[4];
885 };
886 
887 struct nvme_delete_queue {
888 	__u8			opcode;
889 	__u8			flags;
890 	__u16			command_id;
891 	__u32			rsvd1[9];
892 	__le16			qid;
893 	__u16			rsvd10;
894 	__u32			rsvd11[5];
895 };
896 
897 struct nvme_abort_cmd {
898 	__u8			opcode;
899 	__u8			flags;
900 	__u16			command_id;
901 	__u32			rsvd1[9];
902 	__le16			sqid;
903 	__u16			cid;
904 	__u32			rsvd11[5];
905 };
906 
907 struct nvme_download_firmware {
908 	__u8			opcode;
909 	__u8			flags;
910 	__u16			command_id;
911 	__u32			rsvd1[5];
912 	union nvme_data_ptr	dptr;
913 	__le32			numd;
914 	__le32			offset;
915 	__u32			rsvd12[4];
916 };
917 
918 struct nvme_format_cmd {
919 	__u8			opcode;
920 	__u8			flags;
921 	__u16			command_id;
922 	__le32			nsid;
923 	__u64			rsvd2[4];
924 	__le32			cdw10;
925 	__u32			rsvd11[5];
926 };
927 
928 struct nvme_get_log_page_command {
929 	__u8			opcode;
930 	__u8			flags;
931 	__u16			command_id;
932 	__le32			nsid;
933 	__u64			rsvd2[2];
934 	union nvme_data_ptr	dptr;
935 	__u8			lid;
936 	__u8			lsp; /* upper 4 bits reserved */
937 	__le16			numdl;
938 	__le16			numdu;
939 	__u16			rsvd11;
940 	__le32			lpol;
941 	__le32			lpou;
942 	__u32			rsvd14[2];
943 };
944 
945 struct nvme_directive_cmd {
946 	__u8			opcode;
947 	__u8			flags;
948 	__u16			command_id;
949 	__le32			nsid;
950 	__u64			rsvd2[2];
951 	union nvme_data_ptr	dptr;
952 	__le32			numd;
953 	__u8			doper;
954 	__u8			dtype;
955 	__le16			dspec;
956 	__u8			endir;
957 	__u8			tdtype;
958 	__u16			rsvd15;
959 
960 	__u32			rsvd16[3];
961 };
962 
963 /*
964  * Fabrics subcommands.
965  */
966 enum nvmf_fabrics_opcode {
967 	nvme_fabrics_command		= 0x7f,
968 };
969 
970 enum nvmf_capsule_command {
971 	nvme_fabrics_type_property_set	= 0x00,
972 	nvme_fabrics_type_connect	= 0x01,
973 	nvme_fabrics_type_property_get	= 0x04,
974 };
975 
976 struct nvmf_common_command {
977 	__u8	opcode;
978 	__u8	resv1;
979 	__u16	command_id;
980 	__u8	fctype;
981 	__u8	resv2[35];
982 	__u8	ts[24];
983 };
984 
985 /*
986  * The legal cntlid range a NVMe Target will provide.
987  * Note that cntlid of value 0 is considered illegal in the fabrics world.
988  * Devices based on earlier specs did not have the subsystem concept;
989  * therefore, those devices had their cntlid value set to 0 as a result.
990  */
991 #define NVME_CNTLID_MIN		1
992 #define NVME_CNTLID_MAX		0xffef
993 #define NVME_CNTLID_DYNAMIC	0xffff
994 
995 #define MAX_DISC_LOGS	255
996 
997 /* Discovery log page entry */
998 struct nvmf_disc_rsp_page_entry {
999 	__u8		trtype;
1000 	__u8		adrfam;
1001 	__u8		subtype;
1002 	__u8		treq;
1003 	__le16		portid;
1004 	__le16		cntlid;
1005 	__le16		asqsz;
1006 	__u8		resv8[22];
1007 	char		trsvcid[NVMF_TRSVCID_SIZE];
1008 	__u8		resv64[192];
1009 	char		subnqn[NVMF_NQN_FIELD_LEN];
1010 	char		traddr[NVMF_TRADDR_SIZE];
1011 	union tsas {
1012 		char		common[NVMF_TSAS_SIZE];
1013 		struct rdma {
1014 			__u8	qptype;
1015 			__u8	prtype;
1016 			__u8	cms;
1017 			__u8	resv3[5];
1018 			__u16	pkey;
1019 			__u8	resv10[246];
1020 		} rdma;
1021 	} tsas;
1022 };
1023 
1024 /* Discovery log page header */
1025 struct nvmf_disc_rsp_page_hdr {
1026 	__le64		genctr;
1027 	__le64		numrec;
1028 	__le16		recfmt;
1029 	__u8		resv14[1006];
1030 	struct nvmf_disc_rsp_page_entry entries[0];
1031 };
1032 
1033 struct nvmf_connect_command {
1034 	__u8		opcode;
1035 	__u8		resv1;
1036 	__u16		command_id;
1037 	__u8		fctype;
1038 	__u8		resv2[19];
1039 	union nvme_data_ptr dptr;
1040 	__le16		recfmt;
1041 	__le16		qid;
1042 	__le16		sqsize;
1043 	__u8		cattr;
1044 	__u8		resv3;
1045 	__le32		kato;
1046 	__u8		resv4[12];
1047 };
1048 
1049 struct nvmf_connect_data {
1050 	uuid_t		hostid;
1051 	__le16		cntlid;
1052 	char		resv4[238];
1053 	char		subsysnqn[NVMF_NQN_FIELD_LEN];
1054 	char		hostnqn[NVMF_NQN_FIELD_LEN];
1055 	char		resv5[256];
1056 };
1057 
1058 struct nvmf_property_set_command {
1059 	__u8		opcode;
1060 	__u8		resv1;
1061 	__u16		command_id;
1062 	__u8		fctype;
1063 	__u8		resv2[35];
1064 	__u8		attrib;
1065 	__u8		resv3[3];
1066 	__le32		offset;
1067 	__le64		value;
1068 	__u8		resv4[8];
1069 };
1070 
1071 struct nvmf_property_get_command {
1072 	__u8		opcode;
1073 	__u8		resv1;
1074 	__u16		command_id;
1075 	__u8		fctype;
1076 	__u8		resv2[35];
1077 	__u8		attrib;
1078 	__u8		resv3[3];
1079 	__le32		offset;
1080 	__u8		resv4[16];
1081 };
1082 
1083 struct nvme_dbbuf {
1084 	__u8			opcode;
1085 	__u8			flags;
1086 	__u16			command_id;
1087 	__u32			rsvd1[5];
1088 	__le64			prp1;
1089 	__le64			prp2;
1090 	__u32			rsvd12[6];
1091 };
1092 
1093 struct streams_directive_params {
1094 	__le16	msl;
1095 	__le16	nssa;
1096 	__le16	nsso;
1097 	__u8	rsvd[10];
1098 	__le32	sws;
1099 	__le16	sgs;
1100 	__le16	nsa;
1101 	__le16	nso;
1102 	__u8	rsvd2[6];
1103 };
1104 
1105 struct nvme_command {
1106 	union {
1107 		struct nvme_common_command common;
1108 		struct nvme_rw_command rw;
1109 		struct nvme_identify identify;
1110 		struct nvme_features features;
1111 		struct nvme_create_cq create_cq;
1112 		struct nvme_create_sq create_sq;
1113 		struct nvme_delete_queue delete_queue;
1114 		struct nvme_download_firmware dlfw;
1115 		struct nvme_format_cmd format;
1116 		struct nvme_dsm_cmd dsm;
1117 		struct nvme_write_zeroes_cmd write_zeroes;
1118 		struct nvme_abort_cmd abort;
1119 		struct nvme_get_log_page_command get_log_page;
1120 		struct nvmf_common_command fabrics;
1121 		struct nvmf_connect_command connect;
1122 		struct nvmf_property_set_command prop_set;
1123 		struct nvmf_property_get_command prop_get;
1124 		struct nvme_dbbuf dbbuf;
1125 		struct nvme_directive_cmd directive;
1126 	};
1127 };
1128 
nvme_is_write(struct nvme_command * cmd)1129 static inline bool nvme_is_write(struct nvme_command *cmd)
1130 {
1131 	/*
1132 	 * What a mess...
1133 	 *
1134 	 * Why can't we simply have a Fabrics In and Fabrics out command?
1135 	 */
1136 	if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1137 		return cmd->fabrics.fctype & 1;
1138 	return cmd->common.opcode & 1;
1139 }
1140 
1141 enum {
1142 	/*
1143 	 * Generic Command Status:
1144 	 */
1145 	NVME_SC_SUCCESS			= 0x0,
1146 	NVME_SC_INVALID_OPCODE		= 0x1,
1147 	NVME_SC_INVALID_FIELD		= 0x2,
1148 	NVME_SC_CMDID_CONFLICT		= 0x3,
1149 	NVME_SC_DATA_XFER_ERROR		= 0x4,
1150 	NVME_SC_POWER_LOSS		= 0x5,
1151 	NVME_SC_INTERNAL		= 0x6,
1152 	NVME_SC_ABORT_REQ		= 0x7,
1153 	NVME_SC_ABORT_QUEUE		= 0x8,
1154 	NVME_SC_FUSED_FAIL		= 0x9,
1155 	NVME_SC_FUSED_MISSING		= 0xa,
1156 	NVME_SC_INVALID_NS		= 0xb,
1157 	NVME_SC_CMD_SEQ_ERROR		= 0xc,
1158 	NVME_SC_SGL_INVALID_LAST	= 0xd,
1159 	NVME_SC_SGL_INVALID_COUNT	= 0xe,
1160 	NVME_SC_SGL_INVALID_DATA	= 0xf,
1161 	NVME_SC_SGL_INVALID_METADATA	= 0x10,
1162 	NVME_SC_SGL_INVALID_TYPE	= 0x11,
1163 
1164 	NVME_SC_SGL_INVALID_OFFSET	= 0x16,
1165 	NVME_SC_SGL_INVALID_SUBTYPE	= 0x17,
1166 
1167 	NVME_SC_NS_WRITE_PROTECTED	= 0x20,
1168 
1169 	NVME_SC_LBA_RANGE		= 0x80,
1170 	NVME_SC_CAP_EXCEEDED		= 0x81,
1171 	NVME_SC_NS_NOT_READY		= 0x82,
1172 	NVME_SC_RESERVATION_CONFLICT	= 0x83,
1173 
1174 	/*
1175 	 * Command Specific Status:
1176 	 */
1177 	NVME_SC_CQ_INVALID		= 0x100,
1178 	NVME_SC_QID_INVALID		= 0x101,
1179 	NVME_SC_QUEUE_SIZE		= 0x102,
1180 	NVME_SC_ABORT_LIMIT		= 0x103,
1181 	NVME_SC_ABORT_MISSING		= 0x104,
1182 	NVME_SC_ASYNC_LIMIT		= 0x105,
1183 	NVME_SC_FIRMWARE_SLOT		= 0x106,
1184 	NVME_SC_FIRMWARE_IMAGE		= 0x107,
1185 	NVME_SC_INVALID_VECTOR		= 0x108,
1186 	NVME_SC_INVALID_LOG_PAGE	= 0x109,
1187 	NVME_SC_INVALID_FORMAT		= 0x10a,
1188 	NVME_SC_FW_NEEDS_CONV_RESET	= 0x10b,
1189 	NVME_SC_INVALID_QUEUE		= 0x10c,
1190 	NVME_SC_FEATURE_NOT_SAVEABLE	= 0x10d,
1191 	NVME_SC_FEATURE_NOT_CHANGEABLE	= 0x10e,
1192 	NVME_SC_FEATURE_NOT_PER_NS	= 0x10f,
1193 	NVME_SC_FW_NEEDS_SUBSYS_RESET	= 0x110,
1194 	NVME_SC_FW_NEEDS_RESET		= 0x111,
1195 	NVME_SC_FW_NEEDS_MAX_TIME	= 0x112,
1196 	NVME_SC_FW_ACIVATE_PROHIBITED	= 0x113,
1197 	NVME_SC_OVERLAPPING_RANGE	= 0x114,
1198 	NVME_SC_NS_INSUFFICENT_CAP	= 0x115,
1199 	NVME_SC_NS_ID_UNAVAILABLE	= 0x116,
1200 	NVME_SC_NS_ALREADY_ATTACHED	= 0x118,
1201 	NVME_SC_NS_IS_PRIVATE		= 0x119,
1202 	NVME_SC_NS_NOT_ATTACHED		= 0x11a,
1203 	NVME_SC_THIN_PROV_NOT_SUPP	= 0x11b,
1204 	NVME_SC_CTRL_LIST_INVALID	= 0x11c,
1205 
1206 	/*
1207 	 * I/O Command Set Specific - NVM commands:
1208 	 */
1209 	NVME_SC_BAD_ATTRIBUTES		= 0x180,
1210 	NVME_SC_INVALID_PI		= 0x181,
1211 	NVME_SC_READ_ONLY		= 0x182,
1212 	NVME_SC_ONCS_NOT_SUPPORTED	= 0x183,
1213 
1214 	/*
1215 	 * I/O Command Set Specific - Fabrics commands:
1216 	 */
1217 	NVME_SC_CONNECT_FORMAT		= 0x180,
1218 	NVME_SC_CONNECT_CTRL_BUSY	= 0x181,
1219 	NVME_SC_CONNECT_INVALID_PARAM	= 0x182,
1220 	NVME_SC_CONNECT_RESTART_DISC	= 0x183,
1221 	NVME_SC_CONNECT_INVALID_HOST	= 0x184,
1222 
1223 	NVME_SC_DISCOVERY_RESTART	= 0x190,
1224 	NVME_SC_AUTH_REQUIRED		= 0x191,
1225 
1226 	/*
1227 	 * Media and Data Integrity Errors:
1228 	 */
1229 	NVME_SC_WRITE_FAULT		= 0x280,
1230 	NVME_SC_READ_ERROR		= 0x281,
1231 	NVME_SC_GUARD_CHECK		= 0x282,
1232 	NVME_SC_APPTAG_CHECK		= 0x283,
1233 	NVME_SC_REFTAG_CHECK		= 0x284,
1234 	NVME_SC_COMPARE_FAILED		= 0x285,
1235 	NVME_SC_ACCESS_DENIED		= 0x286,
1236 	NVME_SC_UNWRITTEN_BLOCK		= 0x287,
1237 
1238 	/*
1239 	 * Path-related Errors:
1240 	 */
1241 	NVME_SC_ANA_PERSISTENT_LOSS	= 0x301,
1242 	NVME_SC_ANA_INACCESSIBLE	= 0x302,
1243 	NVME_SC_ANA_TRANSITION		= 0x303,
1244 	NVME_SC_HOST_PATH_ERROR		= 0x370,
1245 
1246 	NVME_SC_DNR			= 0x4000,
1247 };
1248 
1249 struct nvme_completion {
1250 	/*
1251 	 * Used by Admin and Fabrics commands to return data:
1252 	 */
1253 	union nvme_result {
1254 		__le16	u16;
1255 		__le32	u32;
1256 		__le64	u64;
1257 	} result;
1258 	__le16	sq_head;	/* how much of this queue may be reclaimed */
1259 	__le16	sq_id;		/* submission queue that generated this entry */
1260 	__u16	command_id;	/* of the command which completed */
1261 	__le16	status;		/* did the command fail, and if so, why? */
1262 };
1263 
1264 #define NVME_VS(major, minor, tertiary) \
1265 	(((major) << 16) | ((minor) << 8) | (tertiary))
1266 
1267 #define NVME_MAJOR(ver)		((ver) >> 16)
1268 #define NVME_MINOR(ver)		(((ver) >> 8) & 0xff)
1269 #define NVME_TERTIARY(ver)	((ver) & 0xff)
1270 
1271 #endif /* _LINUX_NVME_H */
1272