| /linux-4.19.296/include/linux/ |
| D | clk.h | 20 struct clk;
58 struct clk *clk; member
75 struct clk *clk; member
92 struct clk *clk; member
106 int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
113 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
123 long clk_get_accuracy(struct clk *clk);
133 int clk_set_phase(struct clk *clk, int degrees);
142 int clk_get_phase(struct clk *clk);
153 int clk_set_duty_cycle(struct clk *clk, unsigned int num, unsigned int den);
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| /linux-4.19.296/drivers/clk/imx/ |
| D | clk-imx27.c | 48 static struct clk *clk[IMX27_CLK_MAX]; variable
51 static struct clk ** const uart_clks[] __initconst = {
52 &clk[IMX27_CLK_PER1_GATE],
53 &clk[IMX27_CLK_UART1_IPG_GATE],
54 &clk[IMX27_CLK_UART2_IPG_GATE],
55 &clk[IMX27_CLK_UART3_IPG_GATE],
56 &clk[IMX27_CLK_UART4_IPG_GATE],
57 &clk[IMX27_CLK_UART5_IPG_GATE],
58 &clk[IMX27_CLK_UART6_IPG_GATE],
66 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
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| D | clk-vf610.c | 117 static struct clk *clk[VF610_CLK_END]; variable
135 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
138 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
141 if (IS_ERR(clk)) in vf610_get_fixed_clock()
142 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
143 return clk; in vf610_get_fixed_clock()
188 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
189 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
190 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); in vf610_clocks_init()
191 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); in vf610_clocks_init()
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| D | clk-imx51-imx53.c | 132 static struct clk *clk[IMX5_CLK_END]; variable
135 static struct clk ** const uart_clks_mx51[] __initconst = {
136 &clk[IMX5_CLK_UART1_IPG_GATE],
137 &clk[IMX5_CLK_UART1_PER_GATE],
138 &clk[IMX5_CLK_UART2_IPG_GATE],
139 &clk[IMX5_CLK_UART2_PER_GATE],
140 &clk[IMX5_CLK_UART3_IPG_GATE],
141 &clk[IMX5_CLK_UART3_PER_GATE],
145 static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
146 &clk[IMX5_CLK_UART1_IPG_GATE],
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| D | clk-imx21.c | 42 static struct clk *clk[IMX21_CLK_MAX]; variable
49 clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx21_clocks_init()
50 clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); in _mx21_clocks_init()
51 clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); in _mx21_clocks_init()
52 clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); in _mx21_clocks_init()
53 clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx21_clocks_init()
55 clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in _mx21_clocks_init()
56 clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in _mx21_clocks_init()
57 clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); in _mx21_clocks_init()
58 clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx21_clocks_init()
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| D | clk-imx6q.c | 96 static struct clk *clk[IMX6QDL_CLK_END]; variable
147 static struct clk ** const uart_clks[] __initconst = {
148 &clk[IMX6QDL_CLK_UART_IPG],
149 &clk[IMX6QDL_CLK_UART_SERIAL],
256 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL], in mmdc_ch1_disable()
257 clk[IMX6QDL_CLK_PLL3_USB_OTG]); in mmdc_ch1_disable()
263 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]); in mmdc_ch1_disable()
280 clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]); in mmdc_ch1_reenable()
339 (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) == in init_ldb_clks()
340 clk[IMX6QDL_CLK_PLL2_PFD2_396M])) { in init_ldb_clks()
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| D | clk-imx31.c | 63 static struct clk *clk[clk_max]; variable
66 static struct clk ** const uart_clks[] __initconst = {
67 &clk[ipg],
68 &clk[uart1_gate],
69 &clk[uart2_gate],
70 &clk[uart3_gate],
71 &clk[uart4_gate],
72 &clk[uart5_gate],
78 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
79 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
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| D | clk-imx35.c | 87 static struct clk *clk[clk_max]; variable
89 static struct clk ** const uart_clks[] __initconst = {
90 &clk[ipg],
91 &clk[uart1_gate],
92 &clk[uart2_gate],
93 &clk[uart3_gate],
119 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
120 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
121 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
122 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
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| D | clk-imx25.c | 87 static struct clk *clk[clk_max]; variable
89 static struct clk ** const uart_clks[] __initconst = {
90 &clk[uart_ipg_per],
91 &clk[uart1_ipg],
92 &clk[uart2_ipg],
93 &clk[uart3_ipg],
94 &clk[uart4_ipg],
95 &clk[uart5_ipg],
103 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
104 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
[all …]
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| D | clk-imx1.c | 38 static struct clk *clk[IMX1_CLK_MAX]; variable
53 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx1_clocks_init_dt()
54 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768); in mx1_clocks_init_dt()
55 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); in mx1_clocks_init_dt()
56 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); in mx1_clocks_init_dt()
57 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); in mx1_clocks_init_dt()
58 …clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)… in mx1_clocks_init_dt()
59 clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0); in mx1_clocks_init_dt()
60 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in mx1_clocks_init_dt()
61 clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); in mx1_clocks_init_dt()
[all …]
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| /linux-4.19.296/drivers/clk/ux500/ |
| D | u8500_of_clk.c | 19 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
20 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
21 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
23 #define PRCC_SHOW(clk, base, bit) \ argument
24 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
25 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
26 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
27 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
28 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
30 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, in ux500_twocell_get()
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| D | clk-sysctrl.c | 39 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_prepare() local
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
42 clk->reg_bits[0]); in clk_sysctrl_prepare()
44 if (!ret && clk->enable_delay_us) in clk_sysctrl_prepare()
45 usleep_range(clk->enable_delay_us, clk->enable_delay_us); in clk_sysctrl_prepare()
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_unprepare() local
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare()
54 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n", in clk_sysctrl_unprepare()
61 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_recalc_rate() local
62 return clk->rate; in clk_sysctrl_recalc_rate()
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| /linux-4.19.296/drivers/media/v4l2-core/ |
| D | v4l2-clk.c | 30 struct v4l2_clk *clk; in v4l2_clk_find() local
32 list_for_each_entry(clk, &clk_list, list) in v4l2_clk_find()
33 if (!strcmp(dev_id, clk->dev_id)) in v4l2_clk_find()
34 return clk; in v4l2_clk_find()
41 struct v4l2_clk *clk; in v4l2_clk_get() local
42 struct clk *ccf_clk = clk_get(dev, id); in v4l2_clk_get()
49 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in v4l2_clk_get()
50 if (!clk) { in v4l2_clk_get()
54 clk->clk = ccf_clk; in v4l2_clk_get()
56 return clk; in v4l2_clk_get()
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| /linux-4.19.296/drivers/sh/clk/ |
| D | cpg.c | 19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_write()
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| D | core.c | 39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), in clk_rate_mult_range_round()
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| /linux-4.19.296/drivers/clk/mmp/ |
| D | clk-mmp2.c | 79 struct clk *clk; in mmp2_clk_init() local
80 struct clk *vctcxo; in mmp2_clk_init()
103 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in mmp2_clk_init()
104 clk_register_clkdev(clk, "clk32", NULL); in mmp2_clk_init()
109 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000); in mmp2_clk_init()
110 clk_register_clkdev(clk, "pll1", NULL); in mmp2_clk_init()
112 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000); in mmp2_clk_init()
113 clk_register_clkdev(clk, "usb_pll", NULL); in mmp2_clk_init()
115 clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); in mmp2_clk_init()
116 clk_register_clkdev(clk, "pll2", NULL); in mmp2_clk_init()
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| D | clk-pxa168.c | 71 struct clk *clk; in pxa168_clk_init() local
72 struct clk *uart_pll; in pxa168_clk_init()
95 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in pxa168_clk_init()
96 clk_register_clkdev(clk, "clk32", NULL); in pxa168_clk_init()
98 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); in pxa168_clk_init()
99 clk_register_clkdev(clk, "vctcxo", NULL); in pxa168_clk_init()
101 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa168_clk_init()
102 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
104 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
106 clk_register_clkdev(clk, "pll1_2", NULL); in pxa168_clk_init()
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| D | clk-pxa910.c | 69 struct clk *clk; in pxa910_clk_init() local
70 struct clk *uart_pll; in pxa910_clk_init()
100 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in pxa910_clk_init()
101 clk_register_clkdev(clk, "clk32", NULL); in pxa910_clk_init()
103 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); in pxa910_clk_init()
104 clk_register_clkdev(clk, "vctcxo", NULL); in pxa910_clk_init()
106 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa910_clk_init()
107 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
109 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
111 clk_register_clkdev(clk, "pll1_2", NULL); in pxa910_clk_init()
[all …]
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| /linux-4.19.296/drivers/clk/spear/ |
| D | spear3xx_clock.c | 143 struct clk *clk; in spear300_clk_init() local
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
147 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
151 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); in spear300_clk_init()
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
159 clk_register_clkdev(clk, NULL, "a9000000.gpio"); in spear300_clk_init()
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
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| D | spear1310_clock.c | 387 struct clk *clk, *clk1; in spear1310_clk_init() local
389 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1310_clk_init()
390 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
392 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1310_clk_init()
393 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1310_clk_init()
395 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1310_clk_init()
396 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1310_clk_init()
398 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1310_clk_init()
399 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1310_clk_init()
401 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1310_clk_init()
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| D | spear6xx_clock.c | 118 struct clk *clk, *clk1; in spear6xx_clk_init() local
120 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear6xx_clk_init()
121 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
123 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); in spear6xx_clk_init()
124 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
127 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
129 clk_register_clkdev(clk, NULL, "rtc-spear"); in spear6xx_clk_init()
132 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, in spear6xx_clk_init()
134 clk_register_clkdev(clk, "pll3_clk", NULL); in spear6xx_clk_init()
136 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", in spear6xx_clk_init()
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| D | spear1340_clock.c | 444 struct clk *clk, *clk1; in spear1340_clk_init() local
446 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1340_clk_init()
447 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1340_clk_init()
449 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1340_clk_init()
450 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1340_clk_init()
452 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1340_clk_init()
453 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1340_clk_init()
455 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1340_clk_init()
456 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1340_clk_init()
458 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1340_clk_init()
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| /linux-4.19.296/drivers/clk/zte/ |
| D | clk-zx296702.c | 21 static struct clk *topclk[ZX296702_TOPCLK_END];
22 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
23 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
199 static inline struct clk *zx_divtbl(const char *name, const char *parent, in zx_divtbl()
207 static inline struct clk *zx_div(const char *name, const char *parent, in zx_div()
214 static inline struct clk *zx_mux(const char *name, const char * const *parents, in zx_mux()
221 static inline struct clk *zx_gate(const char *name, const char *parent, in zx_gate()
230 struct clk **clk = topclk; in zx296702_top_clocks_init() local
236 clk[ZX296702_OSC] = in zx296702_top_clocks_init()
238 clk[ZX296702_PLL_A9] = in zx296702_top_clocks_init()
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| /linux-4.19.296/drivers/clk/ti/ |
| D | clkt_dflt.c | 58 static int _wait_idlest_generic(struct clk_hw_omap *clk, in _wait_idlest_generic() argument
93 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) in _omap2_module_wait_ready() argument
101 if (clk->ops->find_companion) { in _omap2_module_wait_ready()
102 clk->ops->find_companion(clk, &companion_reg, &other_bit); in _omap2_module_wait_ready()
108 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); in _omap2_module_wait_ready()
113 _wait_idlest_generic(clk, &idlest_reg, (1 << idlest_bit), in _omap2_module_wait_ready()
114 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
142 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, in omap2_clk_dflt_find_companion() argument
146 memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg)); in omap2_clk_dflt_find_companion()
154 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
[all …]
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| /linux-4.19.296/drivers/clk/mediatek/ |
| D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
4 obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
5 obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
6 obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
7 obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
8 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
9 obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
10 obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
11 obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
[all …]
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