Searched refs:clk_phase (Results 1 – 4 of 4) sorted by relevance
54 u32 clk_phase[2]; in socfpga_clk_prepare() local56 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()57 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { in socfpga_clk_prepare()58 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()60 clk_phase[i] = 0; in socfpga_clk_prepare()63 clk_phase[i] = 1; in socfpga_clk_prepare()66 clk_phase[i] = 2; in socfpga_clk_prepare()69 clk_phase[i] = 3; in socfpga_clk_prepare()72 clk_phase[i] = 4; in socfpga_clk_prepare()75 clk_phase[i] = 5; in socfpga_clk_prepare()[all …]
125 u32 clk_phase[2]; in socfpga_clk_prepare() local127 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()135 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()137 clk_phase[i] = 0; in socfpga_clk_prepare()140 clk_phase[i] = 1; in socfpga_clk_prepare()143 clk_phase[i] = 2; in socfpga_clk_prepare()146 clk_phase[i] = 3; in socfpga_clk_prepare()149 clk_phase[i] = 4; in socfpga_clk_prepare()152 clk_phase[i] = 5; in socfpga_clk_prepare()155 clk_phase[i] = 6; in socfpga_clk_prepare()[all …]
62 u32 clk_phase[2]; member
162 DECLARE_EVENT_CLASS(clk_phase,181 DEFINE_EVENT(clk_phase, clk_set_phase,188 DEFINE_EVENT(clk_phase, clk_set_phase_complete,