Searched refs:clk_pol (Results 1 – 6 of 6) sorted by relevance
6 unsigned int clk_pol:1; member
37 int clk_pol; member
528 u8 serial, u8 clk_pol, u8 clk_gated) in lgs8gxx_set_mpeg_mode() argument540 t |= clk_pol ? TS_CLK_INVERTED : TS_CLK_NORMAL; in lgs8gxx_set_mpeg_mode()
996 stv0367ter_set_clk_pol(state, state->config->clk_pol); in stv0367ter_init()2309 switch (state->config->clk_pol) { in stv0367cab_init()
38 unsigned clk_pol:1; /* true = rising edge */ member