1 /* 2 * Renesas Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2015 Glider bvba 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 */ 10 11 #ifndef __CLK_RENESAS_CPG_MSSR_H__ 12 #define __CLK_RENESAS_CPG_MSSR_H__ 13 14 /* 15 * Definitions of CPG Core Clocks 16 * 17 * These include: 18 * - Clock outputs exported to DT 19 * - External input clocks 20 * - Internal CPG clocks 21 */ 22 23 struct cpg_core_clk { 24 /* Common */ 25 const char *name; 26 unsigned int id; 27 unsigned int type; 28 /* Depending on type */ 29 unsigned int parent; /* Core Clocks only */ 30 unsigned int div; 31 unsigned int mult; 32 unsigned int offset; 33 }; 34 35 enum clk_types { 36 /* Generic */ 37 CLK_TYPE_IN, /* External Clock Input */ 38 CLK_TYPE_FF, /* Fixed Factor Clock */ 39 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ 40 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ 41 42 /* Custom definitions start here */ 43 CLK_TYPE_CUSTOM, 44 }; 45 46 #define DEF_TYPE(_name, _id, _type...) \ 47 { .name = _name, .id = _id, .type = _type } 48 #define DEF_BASE(_name, _id, _type, _parent...) \ 49 DEF_TYPE(_name, _id, _type, .parent = _parent) 50 51 #define DEF_INPUT(_name, _id) \ 52 DEF_TYPE(_name, _id, CLK_TYPE_IN) 53 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ 54 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 55 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ 56 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) 57 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ 58 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) 59 60 /* 61 * Definitions of Module Clocks 62 */ 63 64 struct mssr_mod_clk { 65 const char *name; 66 unsigned int id; 67 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */ 68 }; 69 70 /* Convert from sparse base-100 to packed index space */ 71 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32)) 72 73 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x)) 74 75 #define DEF_MOD(_name, _mod, _parent...) \ 76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent } 77 78 79 struct device_node; 80 81 /** 82 * SoC-specific CPG/MSSR Description 83 * 84 * @core_clks: Array of Core Clock definitions 85 * @num_core_clks: Number of entries in core_clks[] 86 * @last_dt_core_clk: ID of the last Core Clock exported to DT 87 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 88 * 89 * @mod_clks: Array of Module Clock definitions 90 * @num_mod_clks: Number of entries in mod_clks[] 91 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 92 * 93 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 94 * should not be disabled without a knowledgeable driver 95 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 96 * 97 * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power 98 * Management, in addition to Module Clocks 99 * @num_core_pm_clks: Number of entries in core_pm_clks[] 100 * 101 * @init: Optional callback to perform SoC-specific initialization 102 * @cpg_clk_register: Optional callback to handle special Core Clock types 103 */ 104 105 struct cpg_mssr_info { 106 /* Core Clocks */ 107 const struct cpg_core_clk *core_clks; 108 unsigned int num_core_clks; 109 unsigned int last_dt_core_clk; 110 unsigned int num_total_core_clks; 111 112 /* Module Clocks */ 113 const struct mssr_mod_clk *mod_clks; 114 unsigned int num_mod_clks; 115 unsigned int num_hw_mod_clks; 116 117 /* Critical Module Clocks that should not be disabled */ 118 const unsigned int *crit_mod_clks; 119 unsigned int num_crit_mod_clks; 120 121 /* Core Clocks suitable for PM, in addition to the Module Clocks */ 122 const unsigned int *core_pm_clks; 123 unsigned int num_core_pm_clks; 124 125 /* Callbacks */ 126 int (*init)(struct device *dev); 127 struct clk *(*cpg_clk_register)(struct device *dev, 128 const struct cpg_core_clk *core, 129 const struct cpg_mssr_info *info, 130 struct clk **clks, void __iomem *base, 131 struct raw_notifier_head *notifiers); 132 }; 133 134 extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; 135 extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; 136 extern const struct cpg_mssr_info r8a77470_cpg_mssr_info; 137 extern const struct cpg_mssr_info r8a7790_cpg_mssr_info; 138 extern const struct cpg_mssr_info r8a7791_cpg_mssr_info; 139 extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; 140 extern const struct cpg_mssr_info r8a7794_cpg_mssr_info; 141 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; 142 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; 143 extern const struct cpg_mssr_info r8a77965_cpg_mssr_info; 144 extern const struct cpg_mssr_info r8a77970_cpg_mssr_info; 145 extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; 146 extern const struct cpg_mssr_info r8a77990_cpg_mssr_info; 147 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; 148 149 150 /* 151 * Helpers for fixing up clock tables depending on SoC revision 152 */ 153 154 struct mssr_mod_reparent { 155 unsigned int clk, parent; 156 }; 157 158 159 extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks, 160 unsigned int num_core_clks, 161 unsigned int first_clk, 162 unsigned int last_clk); 163 extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 164 unsigned int num_mod_clks, 165 const unsigned int *clks, unsigned int n); 166 extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks, 167 unsigned int num_mod_clks, 168 const struct mssr_mod_reparent *clks, 169 unsigned int n); 170 #endif 171