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/linux-4.19.296/drivers/clk/renesas/
Dclk-div6.c53 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_enable() local
56 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
57 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()
58 writel(val, clock->reg); in cpg_div6_clock_enable()
65 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_disable() local
68 val = readl(clock->reg); in cpg_div6_clock_disable()
78 writel(val, clock->reg); in cpg_div6_clock_disable()
83 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_is_enabled() local
85 return !(readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
91 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_recalc_rate() local
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Drcar-gen3-cpg.c265 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_enable() local
266 u32 val = readl(clock->csn.reg); in cpg_sd_clock_enable()
269 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; in cpg_sd_clock_enable()
271 writel(val, clock->csn.reg); in cpg_sd_clock_enable()
278 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_disable() local
280 writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg); in cpg_sd_clock_disable()
285 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_is_enabled() local
287 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK); in cpg_sd_clock_is_enabled()
293 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_recalc_rate() local
296 clock->div_table[clock->cur_div_idx].div); in cpg_sd_clock_recalc_rate()
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DKconfig2 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
30 bool "Legacy DT clock support"
42 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
45 bool "RZ/A1H clock support" if COMPILE_TEST
49 bool "R-Mobile APE6 clock support" if COMPILE_TEST
54 bool "R-Mobile A1 clock support" if COMPILE_TEST
59 bool "RZ/G1M clock support" if COMPILE_TEST
63 bool "RZ/G1E clock support" if COMPILE_TEST
67 bool "RZ/G1C clock support" if COMPILE_TEST
71 bool "R-Car M1A clock support" if COMPILE_TEST
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Dclk-mstp.c78 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_endisable() local
79 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_endisable()
80 u32 bitmask = BIT(clock->bit_index); in cpg_mstp_clock_endisable()
113 group->smstpcr, clock->bit_index); in cpg_mstp_clock_endisable()
132 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_is_enabled() local
133 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_is_enabled()
141 return !(value & BIT(clock->bit_index)); in cpg_mstp_clock_is_enabled()
155 struct mstp_clock *clock; in cpg_mstp_clock_register() local
158 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in cpg_mstp_clock_register()
159 if (!clock) in cpg_mstp_clock_register()
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Drenesas-cpg-mssr.c151 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_endisable() local
152 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_endisable()
153 unsigned int reg = clock->index / 32; in cpg_mstp_clock_endisable()
154 unsigned int bit = clock->index % 32; in cpg_mstp_clock_endisable()
204 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_is_enabled() local
205 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_is_enabled()
208 value = readl(priv->base + MSTPSR(clock->index / 32)); in cpg_mstp_clock_is_enabled()
210 return !(value & BIT(clock->index % 32)); in cpg_mstp_clock_is_enabled()
343 struct mstp_clock *clock = NULL; in cpg_mssr_register_mod_clk() local
367 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in cpg_mssr_register_mod_clk()
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/linux-4.19.296/drivers/clk/bcm/
DKconfig2 bool "Broadcom BCM63xx clock support"
7 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
11 bool "Broadcom Kona CCU clock support"
15 Enable common clock framework support for Broadcom SoCs
16 using "Kona" style clock control units, including those
22 Enable common clock framework support for Broadcom SoCs
26 bool "Broadcom Cygnus clock support"
31 Enable common clock framework support for the Broadcom Cygnus SoC
34 bool "Broadcom Hurricane 2 clock support"
39 Enable common clock framework support for the Broadcom Hurricane 2
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Dclk-bcm2835.c909 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_is_on() local
910 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_is_on()
911 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_is_on()
920 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_choose_div() local
921 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_choose_div()
953 static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, in bcm2835_clock_rate_from_divisor() argument
957 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_rate_from_divisor()
983 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_get_rate() local
984 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_get_rate()
985 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_get_rate()
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/linux-4.19.296/include/linux/
Dposix-timers.h31 #define CPUCLOCK_PID(clock) ((pid_t) ~((clock) >> 3)) argument
32 #define CPUCLOCK_PERTHREAD(clock) \ argument
33 (((clock) & (clockid_t) CPUCLOCK_PERTHREAD_MASK) != 0)
36 #define CPUCLOCK_WHICH(clock) ((clock) & (clockid_t) CPUCLOCK_CLOCK_MASK) argument
46 const clockid_t clock) in make_process_cpuclock() argument
48 return ((~pid) << 3) | clock; in make_process_cpuclock()
51 const clockid_t clock) in make_thread_cpuclock() argument
53 return make_process_cpuclock(tid, clock | CPUCLOCK_PERTHREAD_MASK); in make_thread_cpuclock()
/linux-4.19.296/drivers/clk/ti/
Dadpll.c205 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
213 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
223 cl = clkdev_create(clock, con_id, NULL); in ti_adpll_setup_clock()
234 d->outputs.clks[output_index] = clock; in ti_adpll_setup_clock()
250 struct clk *clock; in ti_adpll_init_divider() local
257 clock = clk_register_divider(d->dev, child_name, parent_name, 0, in ti_adpll_init_divider()
260 if (IS_ERR(clock)) { in ti_adpll_init_divider()
262 name, PTR_ERR(clock)); in ti_adpll_init_divider()
263 return PTR_ERR(clock); in ti_adpll_init_divider()
266 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_divider()
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Dclk-814x.c91 struct clk *clock; in dm814x_adpll_enable_init_clocks() local
93 clock = clk_get(NULL, init_clocks[i]); in dm814x_adpll_enable_init_clocks()
94 if (WARN(IS_ERR(clock), "could not find init clock %s\n", in dm814x_adpll_enable_init_clocks()
97 err = clk_prepare_enable(clock); in dm814x_adpll_enable_init_clocks()
DKconfig6 ADPLL clock driver for the dm814x SoC using common clock framework.
/linux-4.19.296/drivers/ptp/
DKconfig2 # PTP clock support configuration
5 menu "PTP clock support"
8 tristate "PTP clock support"
22 devices. If you want to use a PTP clock, then you should
23 also enable at least one clock driver as well.
29 tristate "Broadcom DTE as PTP clock"
36 (DTE) in the Broadcom SoC's as a PTP clock.
38 The clock can be used in both wired and wireless networks
45 tristate "Freescale QorIQ 1588 timer as PTP clock"
51 timer as a PTP clock. This clock is only useful if your PTP
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/linux-4.19.296/drivers/clk/samsung/
DKconfig3 bool "Samsung Exynos clock controller support" if COMPILE_TEST
9 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
13 tristate "Samsung Exynos AUDSS clock controller support"
17 Support for the Audio Subsystem CLKCON clock controller present
23 bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
26 Build the s3c2410 clock driver based on the common clock framework.
33 Temporary symbol to build the dclk driver based on the common clock
37 bool "Samsung S3C2412 clock controller support" if COMPILE_TEST
41 bool "Samsung S3C2443 clock controller support" if COMPILE_TEST
/linux-4.19.296/drivers/clk/
DKconfig16 The common clock framework is a single definition of struct
18 implementation of the clock API in include/linux/clk.h.
46 clock.
58 This driver supports RK805, RK808 and RK818 crystal oscillator clock. These
69 This driver supports the hi655x PMIC clock. This
81 firmware providing all the clock controls.
91 firmware providing all the clock controls.
99 This driver supports Silicon Labs 5351A/B/C programmable clock
109 This driver supports the Silicon Labs 514 programmable clock
118 This driver supports the Silicon Labs 544 programmable clock
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/linux-4.19.296/drivers/clk/hisilicon/
DKconfig7 Build the clock driver for hi3516cv300.
15 Build the clock driver for hi3519.
22 Build the clock driver for hi3660.
30 Build the clock driver for hi3798cv200.
37 Build the Hisilicon Hi6220 clock driver based on the common clock framework.
52 Build the Hisilicon Hi6220 stub clock driver.
60 Build the Hisilicon Hi3660 stub clock driver.
/linux-4.19.296/drivers/clk/qcom/
DKconfig9 tristate "Support for Qualcomm's clock controllers"
44 memory and accepts clock requests, aggregates the requests and turns
57 memory and accepts clock requests, aggregates the requests and turns
76 Support for the global clock controller on apq8084 devices.
86 Support for the multimedia clock controller on apq8084 devices.
94 Support for the global clock controller on ipq4019 devices.
102 Support for the global clock controller on ipq806x devices.
111 Support for the LPASS clock controller on ipq806x devices.
119 Support for global clock controller on ipq8074 devices.
121 i2c, USB, SD/eMMC, etc. Select this for the root clock
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/linux-4.19.296/drivers/clk/keystone/
DKconfig5 Supports clock drivers for Keystone based SOCs. These SOCs have local
6 a power sleep control module that gate the clock to the IPs and PLLs.
9 tristate "TI System Control Interface clock drivers"
14 This adds the clock driver support over TI System Control Interface.
15 If you wish to use clock resources from the PMMC firmware, say Y.
/linux-4.19.296/drivers/media/rc/
Dir-hix5hd2.c70 struct clk *clock; member
91 ret = clk_prepare_enable(dev->clock); in hix5hd2_ir_enable()
93 clk_disable_unprepare(dev->clock); in hix5hd2_ir_enable()
247 priv->clock = devm_clk_get(dev, NULL); in hix5hd2_ir_probe()
248 if (IS_ERR(priv->clock)) { in hix5hd2_ir_probe()
250 ret = PTR_ERR(priv->clock); in hix5hd2_ir_probe()
253 ret = clk_prepare_enable(priv->clock); in hix5hd2_ir_probe()
256 priv->rate = clk_get_rate(priv->clock); in hix5hd2_ir_probe()
295 clk_disable_unprepare(priv->clock); in hix5hd2_ir_probe()
306 clk_disable_unprepare(priv->clock); in hix5hd2_ir_remove()
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/linux-4.19.296/drivers/i2c/busses/
Di2c-mpc.c84 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
280 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, in mpc_i2c_get_fdr_52xx() argument
288 if (clock == MPC_I2C_CLOCK_LEGACY) { in mpc_i2c_get_fdr_52xx()
295 divider = mpc5xxx_get_bus_frequency(node) / clock; in mpc_i2c_get_fdr_52xx()
316 u32 clock) in mpc_i2c_setup_52xx() argument
320 if (clock == MPC_I2C_CLOCK_PRESERVE) { in mpc_i2c_setup_52xx()
326 ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk); in mpc_i2c_setup_52xx()
338 u32 clock) in mpc_i2c_setup_52xx() argument
346 u32 clock) in mpc_i2c_setup_512x() argument
369 mpc_i2c_setup_52xx(node, i2c, clock); in mpc_i2c_setup_512x()
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Di2c-pca-isa.c41 static int clock = 59000; variable
156 pca_isa_data.i2c_clock = clock; in pca_isa_probe()
204 module_param(clock, int, 0);
205 MODULE_PARM_DESC(clock, "Clock rate in hertz.\n\t\t"
/linux-4.19.296/drivers/i2c/algos/
Di2c-algo-pca.c408 int clock; in pca_init() local
449 clock = pca_clock(pca_data); in pca_init()
451 adap->name, freqs[clock]); in pca_init()
454 pca_data->bus_settings.clock_freq = clock; in pca_init()
458 int clock; in pca_init() local
485 clock = pca_clock(pca_data) / 100; in pca_init()
513 if (clock < 648) { in pca_init()
515 thi = 1000000 - clock * raise_fall_time; in pca_init()
516 thi /= (I2C_PCA_OSC_PER * clock) - tlow; in pca_init()
518 tlow = (1000000 - clock * raise_fall_time) * min_tlow; in pca_init()
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/linux-4.19.296/include/linux/mfd/
Ddbx500-prcmu.h263 static inline int prcmu_request_clock(u8 clock, bool enable) in prcmu_request_clock() argument
265 return db8500_prcmu_request_clock(clock, enable); in prcmu_request_clock()
268 unsigned long prcmu_clock_rate(u8 clock);
269 long prcmu_round_clock_rate(u8 clock, unsigned long rate);
270 int prcmu_set_clock_rate(u8 clock, unsigned long rate);
443 static inline int prcmu_request_clock(u8 clock, bool enable) in prcmu_request_clock() argument
448 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) in prcmu_round_clock_rate() argument
453 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) in prcmu_set_clock_rate() argument
458 static inline unsigned long prcmu_clock_rate(u8 clock) in prcmu_clock_rate() argument
/linux-4.19.296/include/soc/fsl/qe/
Ducc.h42 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
44 int ucc_set_tdm_rxtx_clk(unsigned int tdm_num, enum qe_clock clock,
46 int ucc_set_tdm_rxtx_sync(unsigned int tdm_num, enum qe_clock clock,
/linux-4.19.296/drivers/clk/meson/
DKconfig27 Support for the clock controller on AmLogic S802 (Meson8),
37 Support for the clock controller on AmLogic S905 devices, aka gxbb.
46 Support for the clock controller on AmLogic A113D devices, aka axg.
55 Support for the audio clock controller on AmLogic A113D devices,
/linux-4.19.296/drivers/clk/versatile/
DKconfig21 Supports clock muxing (REFCLK/TIMCLK to TIMERCLKEN0-3) capabilities
25 bool "Clock driver for Versatile Express OSC clock generators"
30 Simple regmap-based driver driving clock generators on Versatile

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