Searched refs:con1 (Results 1 – 5 of 5) sorted by relevance
| /linux-4.19.296/drivers/iio/adc/ |
| D | exynos_adc.c | 231 u32 con1; in exynos_adc_v1_init_hw() local
237 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; in exynos_adc_v1_init_hw()
240 con1 |= ADC_V1_CON_RES; in exynos_adc_v1_init_hw()
241 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_v1_init_hw()
267 u32 con1; in exynos_adc_v1_start_conv() local
271 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
272 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
313 u32 con1; in exynos_adc_s3c2416_start_conv() local
316 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv()
317 con1 |= ADC_S3C2416_CON_RES_SEL; in exynos_adc_s3c2416_start_conv()
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| /linux-4.19.296/drivers/clk/samsung/ |
| D | clk-pll.c | 441 u32 con0, con1; in samsung_pll45xx_set_rate() local
453 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
455 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
473 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
474 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
475 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
490 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
592 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
604 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
606 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { in samsung_pll46xx_set_rate()
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| /linux-4.19.296/drivers/pwm/ |
| D | pwm-mtk-disp.c | 42 unsigned int con1; member
141 mtk_disp_pwm_update_bits(mdp, mdp->data->con1, in mtk_disp_pwm_config()
256 .con1 = 0xac,
266 .con1 = 0x14,
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| /linux-4.19.296/drivers/clk/mediatek/ |
| D | clk-pll.c | 120 u32 con1, val; in mtk_pll_set_rate_regs() local
145 con1 = readl(pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
148 con1 |= CON0_PCW_CHG; in mtk_pll_set_rate_regs()
150 writel(con1, pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
152 writel(con1 + 1, pll->tuner_addr); in mtk_pll_set_rate_regs()
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| /linux-4.19.296/drivers/media/dvb-frontends/ |
| D | itd1000.c | 130 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd; in itd1000_set_lpf_bw() local
138 itd1000_write_reg(state, CON1, con1 | (1 << 1)); in itd1000_set_lpf_bw()
149 itd1000_write_reg(state, CON1, con1 | (0 << 1)); in itd1000_set_lpf_bw()
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