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Searched refs:ctrl_reg (Results 1 – 21 of 21) sorted by relevance

/linux-4.19.296/drivers/regulator/
Dvctrl-regulator.c45 struct regulator *ctrl_reg; member
90 int ctrl_uV = regulator_get_voltage(vctrl->ctrl_reg); in vctrl_get_voltage()
100 struct regulator *ctrl_reg = vctrl->ctrl_reg; in vctrl_set_voltage() local
101 int orig_ctrl_uV = regulator_get_voltage(ctrl_reg); in vctrl_set_voltage()
108 ctrl_reg, in vctrl_set_voltage()
125 ret = regulator_set_voltage(ctrl_reg, in vctrl_set_voltage()
141 regulator_set_voltage(ctrl_reg, orig_ctrl_uV, orig_ctrl_uV); in vctrl_set_voltage()
157 struct regulator *ctrl_reg = vctrl->ctrl_reg; in vctrl_set_voltage_sel() local
166 ret = regulator_set_voltage(ctrl_reg, in vctrl_set_voltage_sel()
184 ret = regulator_set_voltage(ctrl_reg, in vctrl_set_voltage_sel()
[all …]
Dwm831x-ldo.c88 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL; in wm831x_gp_ldo_get_mode() local
99 ret = wm831x_reg_read(wm831x, ctrl_reg); in wm831x_gp_ldo_get_mode()
114 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL; in wm831x_gp_ldo_set_mode() local
128 ret = wm831x_set_bits(wm831x, ctrl_reg, in wm831x_gp_ldo_set_mode()
141 ret = wm831x_set_bits(wm831x, ctrl_reg, in wm831x_gp_ldo_set_mode()
Dqcom_spmi-regulator.c1444 u8 ctrl_reg[8], reg, mask; in spmi_regulator_init_registers() local
1448 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); in spmi_regulator_init_registers()
1458 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &= in spmi_regulator_init_registers()
1460 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |= in spmi_regulator_init_registers()
1469 ctrl_reg[SPMI_COMMON_IDX_MODE] &= in spmi_regulator_init_registers()
1471 ctrl_reg[SPMI_COMMON_IDX_MODE] |= in spmi_regulator_init_registers()
1477 ctrl_reg[SPMI_COMMON_IDX_MODE] &= in spmi_regulator_init_registers()
1479 ctrl_reg[SPMI_COMMON_IDX_MODE] |= in spmi_regulator_init_registers()
1488 ctrl_reg[SPMI_COMMON_IDX_MODE] &= in spmi_regulator_init_registers()
1490 ctrl_reg[SPMI_COMMON_IDX_MODE] |= in spmi_regulator_init_registers()
[all …]
/linux-4.19.296/drivers/rtc/
Drtc-pm8xxx.c88 unsigned int ctrl_reg, rtc_ctrl_reg; in pm8xxx_rtc_set_time() local
106 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_set_time()
110 if (ctrl_reg & regs->alarm_en) { in pm8xxx_rtc_set_time()
112 ctrl_reg &= ~regs->alarm_en; in pm8xxx_rtc_set_time()
113 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
168 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_set_time()
169 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
313 unsigned int ctrl_reg; in pm8xxx_rtc_alarm_irq_enable() local
317 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_alarm_irq_enable()
322 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_alarm_irq_enable()
[all …]
/linux-4.19.296/drivers/clk/microchip/
Dclk-core.c98 void __iomem *ctrl_reg; member
108 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
115 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
123 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
154 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
181 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
192 v = readl(pb->ctrl_reg); in pbclk_set_rate()
198 writel(v, pb->ctrl_reg); in pbclk_set_rate()
203 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
233 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; in pic32_periph_clk_register()
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Dclk-core.h29 const u32 ctrl_reg; member
46 const u32 ctrl_reg; member
53 const u32 ctrl_reg; member
Dclk-pic32mzda.c36 .ctrl_reg = (__reg), \
50 .ctrl_reg = (__reg), \
104 .ctrl_reg = 0x020,
/linux-4.19.296/drivers/bluetooth/
Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
266 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
308 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
309 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
310 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
313 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
314 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
513 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
514 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_interrupt()
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/linux-4.19.296/drivers/pci/hotplug/
Dshpchp.h175 struct ctrl_reg { struct
193 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), argument
194 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
195 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
196 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
197 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
198 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
199 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
200 CMD = offsetof(struct ctrl_reg, cmd),
201 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
[all …]
Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST), argument
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),
[all …]
/linux-4.19.296/drivers/misc/ibmasm/
Dlowlevel.h67 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
68 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
73 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
74 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/linux-4.19.296/drivers/clk/hisilicon/
Dclk-hix5hd2.c139 u32 ctrl_reg; member
151 void __iomem *ctrl_reg; member
177 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
206 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
208 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
221 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
224 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
239 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all …]
/linux-4.19.296/drivers/isdn/hisax/
Dnj_s.c103 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in reset_netjet_s()
104 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_s()
109 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ in reset_netjet_s()
111 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ in reset_netjet_s()
112 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_s()
195 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in njs_cs_init()
196 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in njs_cs_init()
199 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ in njs_cs_init()
200 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in njs_cs_init()
Dnj_u.c86 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in reset_netjet_u()
87 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_u()
89 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ in reset_netjet_u()
91 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_u()
156 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in nju_cs_init()
157 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in nju_cs_init()
160 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ in nju_cs_init()
161 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in nju_cs_init()
Denternow_pci.c156 cs->hw.njet.ctrl_reg = 0x07; in reset_enpci()
157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci()
160 cs->hw.njet.ctrl_reg = 0x30; in reset_enpci()
161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci()
334 cs->hw.njet.ctrl_reg = 0x07; // geändert von 0xff in en_cs_init()
335 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in en_cs_init()
339 cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */ in en_cs_init()
340 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in en_cs_init()
Delsa.c470 cs->hw.elsa.ctrl_reg |= 0x50; in reset_elsa()
471 cs->hw.elsa.ctrl_reg &= ~ELSA_ISDN_RESET; /* Reset On */ in reset_elsa()
472 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); in reset_elsa()
476 cs->hw.elsa.ctrl_reg |= ELSA_ISDN_RESET; /* Reset Off */ in reset_elsa()
477 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); in reset_elsa()
618 cs->hw.elsa.ctrl_reg |= ELSA_STAT_LED; in elsa_led_handler()
620 cs->hw.elsa.ctrl_reg &= ~ELSA_STAT_LED; in elsa_led_handler()
622 cs->hw.elsa.ctrl_reg ^= ELSA_STAT_LED; in elsa_led_handler()
626 cs->hw.elsa.ctrl_reg |= ELSA_LINE_LED; in elsa_led_handler()
628 cs->hw.elsa.ctrl_reg ^= ELSA_LINE_LED; in elsa_led_handler()
[all …]
Ddiva.c781 cs->hw.diva.ctrl_reg = 0; /* Reset On */ in reset_diva()
782 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); in reset_diva()
784 cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */ in reset_diva()
785 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); in reset_diva()
788 cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A; in reset_diva()
792 cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A; in reset_diva()
794 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); in reset_diva()
812 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ? in diva_led_handler()
815 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ? in diva_led_handler()
820 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ? in diva_led_handler()
[all …]
Dhisax.h578 u_char ctrl_reg; member
623 u_char ctrl_reg; member
680 unsigned char ctrl_reg; member
/linux-4.19.296/drivers/i2c/busses/
Di2c-cadence.c346 unsigned int ctrl_reg; in cdns_i2c_mrecv() local
353 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
354 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_mrecv()
371 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_mrecv()
373 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
412 unsigned int ctrl_reg; in cdns_i2c_msend() local
420 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_msend()
421 ctrl_reg &= ~CDNS_I2C_CR_RW; in cdns_i2c_msend()
422 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_msend()
429 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_msend()
[all …]
Di2c-mv64xxx.c607 unsigned long ctrl_reg; in mv64xxx_i2c_offload_xfer() local
613 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE | in mv64xxx_i2c_offload_xfer()
617 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT; in mv64xxx_i2c_offload_xfer()
623 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR | in mv64xxx_i2c_offload_xfer()
631 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD | in mv64xxx_i2c_offload_xfer()
642 ctrl_reg |= in mv64xxx_i2c_offload_xfer()
653 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); in mv64xxx_i2c_offload_xfer()
/linux-4.19.296/drivers/iio/accel/
Dsca3000.c402 u8 ctrl_reg) in sca3000_read_ctrl_reg() argument
415 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg); in sca3000_read_ctrl_reg()