Searched refs:ddrphycfg_parents (Results 1 – 5 of 5) sorted by relevance
| /linux-4.19.296/drivers/clk/mediatek/ |
| D | clk-mt7622.c | 138 static const char * const ddrphycfg_parents[] = { variable
527 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
569 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
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| D | clk-mt8135.c | 286 static const char * const ddrphycfg_parents[] __initconst = { variable
389 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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| D | clk-mt6797.c | 112 static const char * const ddrphycfg_parents[] = { variable
334 MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
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| D | clk-mt2701.c | 168 static const char * const ddrphycfg_parents[] = { variable
506 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
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| D | clk-mt8173.c | 155 static const char * const ddrphycfg_parents[] __initconst = { variable
552 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
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