| /linux-4.19.296/drivers/clk/socfpga/ |
| D | clk-periph.c | 36 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
37 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-periph-a10.c | 39 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
40 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
81 u32 div_reg[3]; in __socfpga_periph_init() local
91 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
93 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
94 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
95 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
97 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-gate-a10.c | 40 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
41 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
109 u32 div_reg[3]; in __socfpga_gate_init() local
141 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
143 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
144 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
145 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
147 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
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| D | clk-gate-s10.c | 21 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
22 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
35 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
71 unsigned long gate_idx, unsigned long div_reg, in s10_register_gate() argument
92 if (div_reg) in s10_register_gate()
93 socfpga_clk->div_reg = regbase + div_reg; in s10_register_gate()
95 socfpga_clk->div_reg = NULL; in s10_register_gate()
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| D | clk-gate.c | 106 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
107 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
110 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
183 u32 div_reg[3]; in __socfpga_gate_init() local
216 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
218 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_gate_init()
219 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
220 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
222 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
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| D | clk.h | 56 void __iomem *div_reg; member
69 void __iomem *div_reg; member
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| D | stratix10-clk.h | 55 unsigned long div_reg; member
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| D | clk-s10.c | 229 clks[i].gate_idx, clks[i].div_reg, in s10_clk_register_gate()
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| /linux-4.19.296/drivers/clk/bcm/ |
| D | clk-bcm2835.c | 488 u32 div_reg; member
991 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1077 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1853 .div_reg = CM_OTPDIV,
1864 .div_reg = CM_TIMERDIV,
1874 .div_reg = CM_TSENSDIV,
1880 .div_reg = CM_TECDIV,
1888 .div_reg = CM_H264DIV,
1895 .div_reg = CM_ISPDIV,
1907 .div_reg = CM_SDCDIV,
[all …]
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| /linux-4.19.296/drivers/clk/ |
| D | clk-vt8500.c | 31 void __iomem *div_reg; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
198 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
234 u32 en_reg, div_reg; in vtwm_device_clk_init() local
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
266 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
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| /linux-4.19.296/drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 240 u32 div_reg; member
256 void __iomem *div_reg; member
386 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
388 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
446 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
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| /linux-4.19.296/drivers/clk/mediatek/ |
| D | clk-mtk.h | 173 u32 div_reg; member
184 .div_reg = _reg, \
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| D | clk-mtk.c | 274 mcd->flags, base + mcd->div_reg, mcd->div_shift, in mtk_clk_register_dividers()
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| /linux-4.19.296/drivers/clk/samsung/ |
| D | clk-cpu.c | 71 static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) in wait_until_divider_stable() argument
76 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
80 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
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| /linux-4.19.296/drivers/clk/ingenic/ |
| D | cgu.c | 379 u32 div_reg, div; in ingenic_clk_recalc_rate() local
384 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
385 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
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