Home
last modified time | relevance | path

Searched refs:div_width (Results 1 – 9 of 9) sorted by relevance

/linux-4.19.296/drivers/clk/rockchip/
Dclk.h367 int div_shift, int div_width,
411 u8 div_width; member
434 .div_width = dw, \
452 .div_width = dw, \
470 .div_width = dw, \
510 .div_width = dw, \
529 .div_width = dw, \
545 .div_width = 16, \
562 .div_width = 16, \
580 .div_width = 16, \
[all …]
Dclk-ddr.c31 int div_width; member
103 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
139 ddrclk->div_width = div_width; in rockchip_clk_register_ddrclk()
Dclk.c49 u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
90 if (div_width > 0) { in rockchip_clk_register_branch()
100 div->width = div_width; in rockchip_clk_register_branch()
476 list->div_shift, list->div_width, in rockchip_clk_register_branches()
483 list->div_shift, list->div_width, in rockchip_clk_register_branches()
501 list->div_width, list->div_flags, in rockchip_clk_register_branches()
519 list->div_shift, list->div_width, in rockchip_clk_register_branches()
543 list->div_shift, list->div_width, in rockchip_clk_register_branches()
553 list->div_width, list->div_flags, in rockchip_clk_register_branches()
Dclk-half-divider.c163 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
202 if (div_width > 0) { in rockchip_clk_register_halfdiv()
210 div->width = div_width; in rockchip_clk_register_halfdiv()
/linux-4.19.296/drivers/clk/socfpga/
Dclk-gate-s10.c72 unsigned long div_offset, u8 div_width, in s10_register_gate() argument
97 socfpga_clk->width = div_width; in s10_register_gate()
Dstratix10-clk.h57 u8 div_width; member
Dclk-s10.c230 clks[i].div_offset, clks[i].div_width, in s10_clk_register_gate()
/linux-4.19.296/drivers/clk/mediatek/
Dclk-mtk.h175 unsigned char div_width; member
186 .div_width = _width, \
Dclk-mtk.c275 mcd->div_width, mcd->clk_divider_flags, lock); in mtk_clk_register_dividers()