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Searched refs:divp_shift (Results 1 – 6 of 6) sorted by relevance

/linux-4.19.296/drivers/clk/tegra/
Dclk-tegra124.c141 .divp_shift = 20,
237 .divp_shift = 20,
311 .divp_shift = 20,
401 .divp_shift = 20,
460 .divp_shift = 24,
499 .divp_shift = 16,
527 .divp_shift = 20,
592 .divp_shift = 20,
709 .divp_shift = 20,
Dclk-tegra114.c155 .divp_shift = 20,
217 .divp_shift = 20,
290 .divp_shift = 20,
337 .divp_shift = 20,
463 .divp_shift = 20,
561 .divp_shift = 24,
590 .divp_shift = 16,
Dclk-tegra210.c1334 #define divp_shift(p) ((p)->params->div_nmp->divp_shift) macro
1338 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1499 .divp_shift = 20,
1621 .divp_shift = 20,
1667 .divp_shift = 20,
1736 .divp_shift = 19,
1815 .divp_shift = 20,
1888 .divp_shift = 24,
1925 .divp_shift = 16,
1958 .divp_shift = 20,
[all …]
Dclk-pll.c265 #define divp_shift(p) (p)->params->div_nmp->divp_shift macro
269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
283 .divp_shift = PLL_BASE_DIVP_SHIFT,
678 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
709 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
971 val |= sel.p << divp_shift(pll); in clk_plle_enable()
1003 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1878 .divp_shift = PLLE_BASE_DIVP_SHIFT,
Dclk.h155 u8 divp_shift; member
Dclk-tegra30.c386 .divp_shift = 20,