Searched refs:divq (Results 1 – 3 of 3) sorted by relevance
| /linux-4.19.296/drivers/clk/ |
| D | clk-highbank.c | 109 unsigned long divf, divq, vco_freq, reg; in clk_pll_recalc_rate() local
116 divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
119 return vco_freq / (1 << divq); in clk_pll_recalc_rate()
125 u32 divq, divf; in clk_pll_calc() local
133 for (divq = 1; divq <= 6; divq++) { in clk_pll_calc()
134 if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ) in clk_pll_calc()
138 vco_freq = rate * (1 << divq); in clk_pll_calc()
142 *pdivq = divq; in clk_pll_calc()
149 u32 divq, divf; in clk_pll_round_rate() local
152 clk_pll_calc(rate, ref_freq, &divq, &divf); in clk_pll_round_rate()
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| /linux-4.19.296/drivers/clk/socfpga/ |
| D | clk-pll-a10.c | 49 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
55 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
57 do_div(vco_freq, (1 + divq)); in clk_pll_recalc_rate()
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| D | clk-pll.c | 52 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
62 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
64 do_div(vco_freq, (1 + divq)); in clk_pll_recalc_rate()
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