Searched refs:dt_id (Results 1 – 7 of 7) sorted by relevance
546 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },547 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },548 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },549 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },550 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },551 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },552 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },553 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },554 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },555 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },[all …]
648 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },649 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },650 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },651 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },652 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },653 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },654 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },655 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },656 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },657 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },[all …]
742 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },743 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },744 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },745 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },746 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },747 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },748 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },749 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },750 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },751 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },[all …]
429 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },430 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },431 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },432 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },433 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },434 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },435 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },436 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },437 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },438 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },[all …]
2287 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },2288 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },2289 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },2290 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },2291 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },2292 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },2293 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },2294 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },2295 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },2296 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },[all …]
340 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id, in tegra_register_devclks()354 return &clks[tegra_clk[clk_id].dt_id]; in tegra_lookup_dt_id()
769 int dt_id; member774 int dt_id; member