Home
last modified time | relevance | path

Searched refs:enable_mask (Results 1 – 25 of 128) sorted by relevance

123456

/linux-4.19.296/drivers/clk/qcom/
Dgcc-msm8660.c53 .enable_mask = BIT(8),
130 .enable_mask = BIT(11),
146 .enable_mask = BIT(9),
181 .enable_mask = BIT(11),
197 .enable_mask = BIT(9),
232 .enable_mask = BIT(11),
248 .enable_mask = BIT(9),
283 .enable_mask = BIT(11),
299 .enable_mask = BIT(9),
334 .enable_mask = BIT(11),
[all …]
Dgcc-sdm845.c174 .enable_mask = BIT(0),
189 .enable_mask = BIT(4),
983 .enable_mask = BIT(0),
998 .enable_mask = BIT(0),
1018 .enable_mask = BIT(0),
1036 .enable_mask = BIT(0),
1054 .enable_mask = BIT(0),
1072 .enable_mask = BIT(0),
1092 .enable_mask = BIT(10),
1107 .enable_mask = BIT(0),
[all …]
Dgcc-mdm9615.c66 .enable_mask = BIT(0),
77 .enable_mask = BIT(4),
104 .enable_mask = BIT(8),
131 .enable_mask = BIT(11),
214 .enable_mask = BIT(11),
230 .enable_mask = BIT(9),
265 .enable_mask = BIT(11),
281 .enable_mask = BIT(9),
316 .enable_mask = BIT(11),
332 .enable_mask = BIT(9),
[all …]
Dgcc-ipq806x.c53 .enable_mask = BIT(0),
80 .enable_mask = BIT(4),
107 .enable_mask = BIT(8),
134 .enable_mask = BIT(14),
291 .enable_mask = BIT(11),
307 .enable_mask = BIT(9),
342 .enable_mask = BIT(11),
358 .enable_mask = BIT(9),
393 .enable_mask = BIT(11),
409 .enable_mask = BIT(9),
[all …]
Dgcc-msm8960.c53 .enable_mask = BIT(4),
80 .enable_mask = BIT(8),
107 .enable_mask = BIT(14),
197 .enable_mask = BIT(11),
213 .enable_mask = BIT(9),
248 .enable_mask = BIT(11),
264 .enable_mask = BIT(9),
299 .enable_mask = BIT(11),
315 .enable_mask = BIT(9),
350 .enable_mask = BIT(11),
[all …]
Dmmcc-msm8960.c200 .enable_mask = BIT(2),
215 .enable_mask = BIT(0),
249 .enable_mask = BIT(2),
264 .enable_mask = BIT(0),
298 .enable_mask = BIT(2),
313 .enable_mask = BIT(0),
353 .enable_mask = BIT(2),
368 .enable_mask = BIT(0),
384 .enable_mask = BIT(8),
417 .enable_mask = BIT(2),
[all …]
Dmmcc-apq8084.c240 .enable_mask = BIT(0),
267 .enable_mask = BIT(1),
1112 .enable_mask = BIT(0),
1127 .enable_mask = BIT(0),
1144 .enable_mask = BIT(0),
1161 .enable_mask = BIT(0),
1178 .enable_mask = BIT(0),
1195 .enable_mask = BIT(0),
1212 .enable_mask = BIT(0),
1229 .enable_mask = BIT(0),
[all …]
Dgcc-msm8996.c195 .enable_mask = BIT(0),
232 .enable_mask = BIT(4),
1252 .enable_mask = BIT(0),
1267 .enable_mask = BIT(0),
1282 .enable_mask = BIT(0),
1297 .enable_mask = BIT(0),
1312 .enable_mask = BIT(0),
1325 .enable_mask = BIT(0),
1340 .enable_mask = BIT(0),
1355 .enable_mask = BIT(0),
[all …]
Dmmcc-msm8974.c205 .enable_mask = BIT(0),
232 .enable_mask = BIT(1),
946 .enable_mask = BIT(0),
962 .enable_mask = BIT(0),
979 .enable_mask = BIT(0),
995 .enable_mask = BIT(0),
1012 .enable_mask = BIT(0),
1029 .enable_mask = BIT(0),
1046 .enable_mask = BIT(0),
1063 .enable_mask = BIT(0),
[all …]
Dgcc-msm8998.c132 .enable_mask = BIT(0),
193 .enable_mask = BIT(1),
254 .enable_mask = BIT(2),
315 .enable_mask = BIT(3),
376 .enable_mask = BIT(4),
1162 .enable_mask = BIT(0),
1175 .enable_mask = BIT(0),
1192 .enable_mask = BIT(0),
1209 .enable_mask = BIT(0),
1222 .enable_mask = BIT(0),
[all …]
Dgcc-apq8084.c127 .enable_mask = BIT(0),
190 .enable_mask = BIT(1),
217 .enable_mask = BIT(4),
289 .enable_mask = BIT(0),
306 .enable_mask = BIT(0),
1332 .enable_mask = BIT(0),
1386 .enable_mask = BIT(12),
1403 .enable_mask = BIT(17),
1419 .enable_mask = BIT(0),
1436 .enable_mask = BIT(0),
[all …]
Dgcc-ipq8074.c412 .enable_mask = BIT(0),
457 .enable_mask = BIT(2),
490 .enable_mask = BIT(5),
524 .enable_mask = BIT(7),
572 .enable_mask = BIT(6),
604 .enable_mask = BIT(4),
670 .enable_mask = BIT(1),
1263 .enable_mask = BIT(1),
2037 .enable_mask = BIT(0),
2054 .enable_mask = BIT(0),
[all …]
Dmmcc-msm8996.c273 .enable_mask = BIT(0),
303 .enable_mask = BIT(1),
1241 .enable_mask = BIT(0),
1256 .enable_mask = BIT(0),
1271 .enable_mask = BIT(0),
1286 .enable_mask = BIT(0),
1300 .enable_mask = BIT(0),
1315 .enable_mask = BIT(0),
1330 .enable_mask = BIT(0),
1345 .enable_mask = BIT(0),
[all …]
Dgcc-msm8974.c83 .enable_mask = BIT(0),
146 .enable_mask = BIT(1),
173 .enable_mask = BIT(4),
1048 .enable_mask = BIT(26),
1064 .enable_mask = BIT(12),
1081 .enable_mask = BIT(17),
1097 .enable_mask = BIT(0),
1114 .enable_mask = BIT(0),
1131 .enable_mask = BIT(0),
1148 .enable_mask = BIT(0),
[all …]
Dgcc-msm8916.c285 .enable_mask = BIT(0),
312 .enable_mask = BIT(1),
339 .enable_mask = BIT(2),
366 .enable_mask = BIT(3),
1229 .enable_mask = BIT(0),
1246 .enable_mask = BIT(0),
1308 .enable_mask = BIT(0),
1339 .enable_mask = BIT(0),
1370 .enable_mask = BIT(0),
1405 .enable_mask = BIT(0),
[all …]
Dgcc-msm8994.c77 .enable_mask = BIT(0),
105 .enable_mask = BIT(4),
1059 .enable_mask = BIT(17),
1072 .enable_mask = BIT(0),
1090 .enable_mask = BIT(0),
1108 .enable_mask = BIT(0),
1126 .enable_mask = BIT(0),
1144 .enable_mask = BIT(0),
1162 .enable_mask = BIT(0),
1180 .enable_mask = BIT(0),
[all …]
Dclk-regmap.c33 return (val & rclk->enable_mask) == 0; in clk_is_enabled_regmap()
35 return (val & rclk->enable_mask) != 0; in clk_is_enabled_regmap()
56 val = rclk->enable_mask; in clk_enable_regmap()
59 rclk->enable_mask, val); in clk_enable_regmap()
78 val = rclk->enable_mask; in clk_disable_regmap()
82 regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask, in clk_disable_regmap()
Dgcc-ipq4019.c206 .enable_mask = BIT(0),
223 .enable_mask = BIT(0),
258 .enable_mask = BIT(0),
288 .enable_mask = BIT(0),
330 .enable_mask = BIT(0),
361 .enable_mask = BIT(0),
406 .enable_mask = BIT(0),
437 .enable_mask = BIT(0),
475 .enable_mask = BIT(0),
506 .enable_mask = BIT(0),
[all …]
Dvideocc-sdm845.c93 .enable_mask = BIT(0),
106 .enable_mask = BIT(0),
119 .enable_mask = BIT(0),
132 .enable_mask = BIT(0),
145 .enable_mask = BIT(0),
158 .enable_mask = BIT(0),
176 .enable_mask = BIT(0),
189 .enable_mask = BIT(0),
207 .enable_mask = BIT(0),
220 .enable_mask = BIT(0),
[all …]
Ddispcc-sdm845.c263 .enable_mask = BIT(0),
276 .enable_mask = BIT(0),
290 .enable_mask = BIT(0),
326 .enable_mask = BIT(0),
345 .enable_mask = BIT(0),
381 .enable_mask = BIT(0),
399 .enable_mask = BIT(0),
417 .enable_mask = BIT(0),
435 .enable_mask = BIT(0),
453 .enable_mask = BIT(0),
[all …]
/linux-4.19.296/drivers/regulator/
Dlp8788-ldo.c201 .enable_mask = LP8788_EN_DLDO1_M,
214 .enable_mask = LP8788_EN_DLDO2_M,
227 .enable_mask = LP8788_EN_DLDO3_M,
240 .enable_mask = LP8788_EN_DLDO4_M,
253 .enable_mask = LP8788_EN_DLDO5_M,
266 .enable_mask = LP8788_EN_DLDO6_M,
279 .enable_mask = LP8788_EN_DLDO7_M,
292 .enable_mask = LP8788_EN_DLDO8_M,
305 .enable_mask = LP8788_EN_DLDO9_M,
318 .enable_mask = LP8788_EN_DLDO10_M,
[all …]
Dbd71837-regulator.c253 .enable_mask = BD71837_BUCK_EN,
269 .enable_mask = BD71837_BUCK_EN,
285 .enable_mask = BD71837_BUCK_EN,
301 .enable_mask = BD71837_BUCK_EN,
317 .enable_mask = BD71837_BUCK_EN,
333 .enable_mask = BD71837_BUCK_EN,
348 .enable_mask = BD71837_BUCK_EN,
364 .enable_mask = BD71837_BUCK_EN,
380 .enable_mask = BD71837_LDO_EN,
396 .enable_mask = BD71837_LDO_EN,
[all …]
/linux-4.19.296/drivers/clk/mmp/
Dclk-apmu.c25 u32 enable_mask; member
38 data = readl_relaxed(apmu->base) | apmu->enable_mask; in clk_apmu_enable()
56 data = readl_relaxed(apmu->base) & ~apmu->enable_mask; in clk_apmu_disable()
69 void __iomem *base, u32 enable_mask, spinlock_t *lock) in mmp_clk_register_apmu() argument
86 apmu->enable_mask = enable_mask; in mmp_clk_register_apmu()
/linux-4.19.296/drivers/clk/ti/
Dapll.c64 v &= ~ad->enable_mask; in dra7_apll_enable()
65 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); in dra7_apll_enable()
103 v &= ~ad->enable_mask; in dra7_apll_disable()
104 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); in dra7_apll_disable()
117 v &= ad->enable_mask; in dra7_apll_is_enabled()
119 v >>= __ffs(ad->enable_mask); in dra7_apll_is_enabled()
224 ad->enable_mask = 0x3; in of_dra7_apll_setup()
247 v &= ad->enable_mask; in omap2_apll_is_enabled()
249 v >>= __ffs(ad->enable_mask); in omap2_apll_is_enabled()
273 v &= ~ad->enable_mask; in omap2_apll_enable()
[all …]
/linux-4.19.296/drivers/clk/sprd/
Dgate.c24 reg |= sg->enable_mask; in clk_gate_toggle()
26 reg &= ~sg->enable_mask; in clk_gate_toggle()
48 sg->enable_mask); in clk_sc_gate_toggle()
91 reg ^= sg->enable_mask; in sprd_gate_is_enabled()
93 reg &= sg->enable_mask; in sprd_gate_is_enabled()

123456