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Searched refs:hwirq (Results 1 – 25 of 147) sorted by relevance

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/linux-4.19.296/drivers/irqchip/
Dirq-or1k-pic.c32 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask()
37 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq)); in or1k_pic_unmask()
42 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_ack()
47 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask_ack()
48 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_mask_ack()
59 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_ack()
64 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
65 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
106 int hwirq; in pic_get_irq() local
108 hwirq = ffs(mfspr(SPR_PICSR) >> first); in pic_get_irq()
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Dirq-sifive-plic.c81 static inline void plic_toggle(int ctxid, int hwirq, int enable) in plic_toggle() argument
83 u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32); in plic_toggle()
84 u32 hwirq_mask = 1 << (hwirq % 32); in plic_toggle()
98 writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_toggle()
103 plic_toggle(handler->ctxid, d->hwirq, enable); in plic_irq_toggle()
128 irq_hw_number_t hwirq) in plic_irqdomain_map() argument
153 irq_hw_number_t hwirq; in plic_handle_irq() local
158 while ((hwirq = readl(claim))) { in plic_handle_irq()
159 int irq = irq_find_mapping(plic_irqdomain, hwirq); in plic_handle_irq()
163 hwirq); in plic_handle_irq()
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Dirq-mbigen.c78 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) in get_mbigen_vec_reg() argument
82 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_vec_reg()
83 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_vec_reg()
84 pin = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_vec_reg()
90 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, in get_mbigen_type_reg() argument
95 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_type_reg()
96 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_type_reg()
97 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_type_reg()
106 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, in get_mbigen_clear_reg() argument
109 unsigned int ofst = (hwirq / 32) * 4; in get_mbigen_clear_reg()
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Dirq-partition-percpu.c37 unsigned int cpu, unsigned int hwirq) in partition_check_cpu() argument
39 return cpumask_test_cpu(cpu, &part->parts[hwirq].mask); in partition_check_cpu()
48 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_mask()
59 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_unmask()
72 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_set_irqchip_state()
87 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_get_irqchip_state()
112 seq_printf(p, " %5s-%lu", chip->name, data->hwirq); in partition_irq_print_chip()
129 int hwirq; in partition_handle_irq() local
133 for_each_set_bit(hwirq, part->bitmap, part->nr_parts) { in partition_handle_irq()
134 if (partition_check_cpu(part, cpu, hwirq)) in partition_handle_irq()
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Dirq-sni-exiu.c46 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
55 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
65 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
76 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_enable()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_enable()
90 val |= BIT(d->hwirq); in exiu_irq_set_type()
92 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
97 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
99 val |= BIT(d->hwirq); in exiu_irq_set_type()
102 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_set_type()
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Dirq-xilinx-intc.c63 unsigned long mask = 1 << d->hwirq; in intc_enable_or_unmask()
65 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
79 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
80 xintc_write(CIE, 1 << d->hwirq); in intc_disable_or_mask()
85 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
86 xintc_write(IAR, 1 << d->hwirq); in intc_ack()
91 unsigned long mask = 1 << d->hwirq; in intc_mask_ack()
93 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
108 unsigned int hwirq, irq = -1; in xintc_get_irq() local
110 hwirq = xintc_read(IVR); in xintc_get_irq()
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Dirq-mmp.c70 int hwirq; in icu_mask_ack_irq() local
73 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
75 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
78 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
82 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
85 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
94 int hwirq; in icu_mask_irq() local
97 hwirq = d->irq - data->virq_base; in icu_mask_irq()
99 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
102 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
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Dirq-mvebu-odmi.c56 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()
59 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()
60 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()
84 unsigned int hwirq, odmin; in odmi_irq_domain_alloc() local
88 hwirq = find_first_zero_bit(odmis_bm, NODMIS_PER_FRAME * odmis_count); in odmi_irq_domain_alloc()
89 if (hwirq >= NODMIS_PER_FRAME * odmis_count) { in odmi_irq_domain_alloc()
94 __set_bit(hwirq, odmis_bm); in odmi_irq_domain_alloc()
97 odmi = &odmis[hwirq >> NODMIS_SHIFT]; in odmi_irq_domain_alloc()
98 odmin = hwirq & NODMIS_MASK; in odmi_irq_domain_alloc()
119 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, in odmi_irq_domain_alloc()
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Dirq-mips-cpu.c46 set_c0_status(IE_SW0 << d->hwirq); in unmask_mips_irq()
52 clear_c0_status(IE_SW0 << d->hwirq); in mask_mips_irq()
75 clear_c0_cause(C_SW0 << d->hwirq); in mips_mt_cpu_irq_startup()
88 clear_c0_cause(C_SW0 << d->hwirq); in mips_mt_cpu_irq_ack()
97 irq_hw_number_t hwirq = irqd_to_hwirq(d); in mips_mt_send_ipi() local
108 write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq)); in mips_mt_send_ipi()
189 unsigned int i, hwirq; in mips_cpu_ipi_alloc() local
193 hwirq = find_first_zero_bit(state->allocated, 2); in mips_cpu_ipi_alloc()
194 if (hwirq == 2) in mips_cpu_ipi_alloc()
196 bitmap_set(state->allocated, hwirq, 1); in mips_cpu_ipi_alloc()
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Dirq-vf610-mscm-ir.c92 irq_hw_number_t hwirq = data->hwirq; in vf610_mscm_ir_enable() local
96 irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); in vf610_mscm_ir_enable()
102 chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); in vf610_mscm_ir_enable()
109 irq_hw_number_t hwirq = data->hwirq; in vf610_mscm_ir_disable() local
112 writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); in vf610_mscm_ir_disable()
132 irq_hw_number_t hwirq; in vf610_mscm_ir_domain_alloc() local
142 hwirq = fwspec->param[0]; in vf610_mscm_ir_domain_alloc()
144 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, in vf610_mscm_ir_domain_alloc()
166 unsigned long *hwirq, in vf610_mscm_ir_domain_translate() argument
171 *hwirq = fwspec->param[0]; in vf610_mscm_ir_domain_translate()
Dirq-aspeed-vic.c120 unsigned int sidx = d->hwirq >> 5; in avic_ack_irq()
121 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_ack_irq()
131 unsigned int sidx = d->hwirq >> 5; in avic_mask_irq()
132 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_mask_irq()
140 unsigned int sidx = d->hwirq >> 5; in avic_unmask_irq()
141 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_unmask_irq()
150 unsigned int sidx = d->hwirq >> 5; in avic_mask_ack_irq()
151 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_mask_ack_irq()
170 irq_hw_number_t hwirq) in avic_map() argument
173 unsigned int sidx = hwirq >> 5; in avic_map()
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Dirq-mips-gic.c110 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); in gic_send_ipi() local
112 write_gic_wedge(GIC_WEDGE_RW | hwirq); in gic_send_ipi()
178 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); in gic_mask_irq()
186 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); in gic_unmask_irq()
198 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); in gic_ack_irq()
208 irq = GIC_HWIRQ_TO_SHARED(d->hwirq); in gic_set_type()
259 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); in gic_set_affinity()
329 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); in gic_mask_local_irq()
336 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); in gic_unmask_local_irq()
353 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); in gic_mask_local_irq_all_vpes()
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Dirq-imx-gpcv2.c74 unsigned int idx = d->hwirq / 32; in imx_gpcv2_irq_set_wake()
81 mask = 1 << d->hwirq % 32; in imx_gpcv2_irq_set_wake()
102 reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; in imx_gpcv2_irq_unmask()
104 val &= ~(1 << d->hwirq % 32); in imx_gpcv2_irq_unmask()
118 reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; in imx_gpcv2_irq_mask()
120 val |= 1 << (d->hwirq % 32); in imx_gpcv2_irq_mask()
142 unsigned long *hwirq, in imx_gpcv2_domain_translate() argument
153 *hwirq = fwspec->param[1]; in imx_gpcv2_domain_translate()
167 irq_hw_number_t hwirq; in imx_gpcv2_domain_alloc() local
172 err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type); in imx_gpcv2_domain_alloc()
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Dirq-lpc32xx.c54 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_mask()
63 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_unmask()
72 u32 mask = BIT(d->hwirq); in lpc32xx_irq_ack()
80 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_set_type()
130 u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq; in lpc32xx_handle_irq() local
132 while (hwirq) { in lpc32xx_handle_irq()
133 irq = __ffs(hwirq); in lpc32xx_handle_irq()
134 hwirq &= ~BIT(irq); in lpc32xx_handle_irq()
143 u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq; in lpc32xx_sic_handler() local
147 while (hwirq) { in lpc32xx_sic_handler()
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Dirq-mvebu-gicp.c62 msg[0].data = data->hwirq; in gicp_compose_msi_msg()
65 msg[1].data = data->hwirq; in gicp_compose_msi_msg()
85 unsigned int hwirq; in gicp_irq_domain_alloc() local
89 hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt); in gicp_irq_domain_alloc()
90 if (hwirq == gicp->spi_cnt) { in gicp_irq_domain_alloc()
94 __set_bit(hwirq, gicp->spi_bitmap); in gicp_irq_domain_alloc()
100 fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32; in gicp_irq_domain_alloc()
113 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, in gicp_irq_domain_alloc()
124 __clear_bit(hwirq, gicp->spi_bitmap); in gicp_irq_domain_alloc()
135 if (d->hwirq >= gicp->spi_cnt) { in gicp_irq_domain_free()
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Dirq-bcm2835.c102 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
107 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
240 u32 hwirq; in bcm2835_handle_irq() local
242 while ((hwirq = get_next_armctrl_hwirq()) != ~0) in bcm2835_handle_irq()
243 handle_domain_irq(intc.domain, hwirq, regs); in bcm2835_handle_irq()
248 u32 hwirq; in bcm2836_chained_handle_irq() local
250 while ((hwirq = get_next_armctrl_hwirq()) != ~0) in bcm2836_chained_handle_irq()
251 generic_handle_irq(irq_linear_revmap(intc.domain, hwirq)); in bcm2836_chained_handle_irq()
Dirq-nvic.c44 nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs) in nvic_handle_irq() argument
46 unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq); in nvic_handle_irq()
53 unsigned long *hwirq, unsigned int *type) in nvic_irq_domain_translate() argument
57 *hwirq = fwspec->param[0]; in nvic_irq_domain_translate()
66 irq_hw_number_t hwirq; in nvic_irq_domain_alloc() local
70 ret = nvic_irq_domain_translate(domain, fwspec, &hwirq, &type); in nvic_irq_domain_alloc()
75 irq_map_generic_chip(domain, virq + i, hwirq + i); in nvic_irq_domain_alloc()
Dirq-armada-370-xp.c174 irq_hw_number_t hwirq = irqd_to_hwirq(d); in armada_370_xp_irq_mask() local
176 if (!is_percpu_irq(hwirq)) in armada_370_xp_irq_mask()
177 writel(hwirq, main_int_base + in armada_370_xp_irq_mask()
180 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_mask()
186 irq_hw_number_t hwirq = irqd_to_hwirq(d); in armada_370_xp_irq_unmask() local
188 if (!is_percpu_irq(hwirq)) in armada_370_xp_irq_unmask()
189 writel(hwirq, main_int_base + in armada_370_xp_irq_unmask()
192 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_unmask()
214 msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START); in armada_370_xp_compose_msi_msg()
232 int hwirq, i; in armada_370_xp_msi_alloc() local
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Dirq-gic-v3-mbi.c43 irq_hw_number_t hwirq) in mbi_irq_gic_domain_alloc() argument
64 fwspec.param[1] = hwirq - 32; in mbi_irq_gic_domain_alloc()
75 static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq, in mbi_free_msi() argument
79 bitmap_release_region(mbi->bm, hwirq - mbi->spi_start, in mbi_free_msi()
88 int hwirq, offset, i, err = 0; in mbi_irq_domain_alloc() local
105 hwirq = mbi->spi_start + offset; in mbi_irq_domain_alloc()
108 err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i); in mbi_irq_domain_alloc()
112 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, in mbi_irq_domain_alloc()
120 mbi_free_msi(mbi, hwirq, nr_irqs); in mbi_irq_domain_alloc()
130 mbi_free_msi(mbi, d->hwirq, nr_irqs); in mbi_irq_domain_free()
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Dirq-crossbar.c79 irq_hw_number_t hwirq) in allocate_gic_irq() argument
91 cb->irq_map[i] = hwirq; in allocate_gic_irq()
110 cb->write(i, hwirq); in allocate_gic_irq()
119 irq_hw_number_t hwirq; in crossbar_domain_alloc() local
127 hwirq = fwspec->param[1]; in crossbar_domain_alloc()
128 if ((hwirq + nr_irqs) > cb->max_crossbar_sources) in crossbar_domain_alloc()
132 int err = allocate_gic_irq(d, virq + i, hwirq + i); in crossbar_domain_alloc()
137 irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i, in crossbar_domain_alloc()
166 cb->irq_map[d->hwirq] = IRQ_FREE; in crossbar_domain_free()
167 cb->write(d->hwirq, cb->safe_map); in crossbar_domain_free()
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Dirq-vt8500.c87 void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4); in vt8500_irq_mask()
91 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; in vt8500_irq_mask()
95 status |= (1 << (d->hwirq & 0x1f)); in vt8500_irq_mask()
98 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask()
100 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask()
110 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask()
112 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask()
121 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_set_type()
140 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_set_type()
/linux-4.19.296/drivers/pci/controller/
Dpcie-iproc-msi.c146 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_group() argument
148 return (hwirq % msi->nr_irqs); in hwirq_to_group()
152 unsigned long hwirq) in iproc_msi_addr_offset() argument
155 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; in iproc_msi_addr_offset()
157 return hwirq_to_group(msi, hwirq) * sizeof(u32); in iproc_msi_addr_offset()
195 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_cpu() argument
197 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
201 unsigned long hwirq) in hwirq_to_canonical_hwirq()
203 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
214 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
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Dpci-xgene-msi.c126 static u32 hwirq_to_reg_set(unsigned long hwirq) in hwirq_to_reg_set() argument
128 return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX)); in hwirq_to_reg_set()
131 static u32 hwirq_to_group(unsigned long hwirq) in hwirq_to_group() argument
133 return (hwirq % NR_HW_IRQS); in hwirq_to_group()
136 static u32 hwirq_to_msi_data(unsigned long hwirq) in hwirq_to_msi_data() argument
138 return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX); in hwirq_to_msi_data()
144 u32 reg_set = hwirq_to_reg_set(data->hwirq); in xgene_compose_msi_msg()
145 u32 group = hwirq_to_group(data->hwirq); in xgene_compose_msi_msg()
150 msg->data = hwirq_to_msi_data(data->hwirq); in xgene_compose_msi_msg()
162 static int hwirq_to_cpu(unsigned long hwirq) in hwirq_to_cpu() argument
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/linux-4.19.296/drivers/misc/cxl/
Dirq.c177 irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq)); in cxl_irq_afu() local
195 irq_off = hwirq - ctx->irqs.offset[r]; in cxl_irq_afu()
205 ctx->pe, irq, hwirq); in cxl_irq_afu()
209 trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq); in cxl_irq_afu()
211 afu_irq, ctx->pe, irq, hwirq); in cxl_irq_afu()
227 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, in cxl_map_irq() argument
234 virq = irq_create_mapping(NULL, hwirq); in cxl_map_irq()
241 cxl_ops->setup_irq(adapter, hwirq, virq); in cxl_map_irq()
243 pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq); in cxl_map_irq()
266 int hwirq, virq; in cxl_register_one_irq() local
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/linux-4.19.296/drivers/gpio/
Dgpio-xgene-sb.c69 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start) argument
88 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq); in xgene_gpio_sb_irq_set_type()
107 d->hwirq, lvl_type); in xgene_gpio_sb_irq_set_type()
145 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); in xgene_gpio_sb_domain_activate()
165 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); in xgene_gpio_sb_domain_deactivate()
174 unsigned long *hwirq, in xgene_gpio_sb_domain_translate() argument
182 *hwirq = fwspec->param[0]; in xgene_gpio_sb_domain_translate()
194 irq_hw_number_t hwirq; in xgene_gpio_sb_domain_alloc() local
197 hwirq = fwspec->param[0]; in xgene_gpio_sb_domain_alloc()
199 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, in xgene_gpio_sb_domain_alloc()
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