Searched refs:input_rate (Results 1 – 3 of 3) sorted by relevance
524 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()525 if (sel->input_rate == parent_rate && in _get_table_rate()529 if (sel->input_rate == 0) in _get_table_rate()540 cfg->input_rate = sel->input_rate; in _get_table_rate()942 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in clk_plle_enable() local947 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()1079 unsigned long flags = 0, input_rate; in clk_pllu_enable() local1089 input_rate = clk_hw_get_rate(osc); in clk_pllu_enable()1102 if (input_rate == utmi_parameters[i].osc_frequency) { in clk_pllu_enable()1110 input_rate); in clk_pllu_enable()[all …]
1039 unsigned long input_rate; in pllx_get_dyn_steps() local1043 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in pllx_get_dyn_steps()1045 input_rate = 38400000; in pllx_get_dyn_steps()1047 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()1049 switch (input_rate) { in pllx_get_dyn_steps()1066 __func__, input_rate); in pllx_get_dyn_steps()1392 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()1408 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg() argument1429 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); in tegra210_pll_fixed_mdiv_cfg()1438 cf = input_rate / cfg->m; in tegra210_pll_fixed_mdiv_cfg()[all …]
117 unsigned long input_rate; member839 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);