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Searched refs:ioread32 (Results 1 – 25 of 70) sorted by relevance

123

/linux-4.19.296/drivers/i2c/busses/
Di2c-pnx.c102 (ioread32(I2C_REG_STS(data)) & mstatus_active)) { in wait_timeout()
113 (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) { in wait_reset()
165 ioread32(I2C_REG_CTL(alg_data)), in i2c_pnx_start()
166 ioread32(I2C_REG_STS(alg_data))); in i2c_pnx_start()
168 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { in i2c_pnx_start()
180 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, in i2c_pnx_start()
207 __func__, ioread32(I2C_REG_STS(alg_data))); in i2c_pnx_stop()
214 (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) { in i2c_pnx_stop()
221 __func__, ioread32(I2C_REG_STS(alg_data))); in i2c_pnx_stop()
235 __func__, ioread32(I2C_REG_STS(alg_data))); in i2c_pnx_master_xmit()
[all …]
Di2c-eg20t.c198 val = ioread32(addr + offset); in pch_setbit()
206 val = ioread32(addr + offset); in pch_clrbit()
256 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr); in pch_i2c_init()
273 while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) { in pch_i2c_wait_for_bus_idle()
275 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); in pch_i2c_wait_for_bus_idle()
305 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); in pch_i2c_start()
316 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); in pch_i2c_stop()
347 if (ioread32(p + PCH_I2CSR) & PCH_GETACK) { in pch_i2c_wait_for_check_xfer()
362 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); in pch_i2c_repstart()
395 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL), in pch_i2c_writebytes()
[all …]
/linux-4.19.296/drivers/char/hw_random/
Diproc-rng200.c62 val = ioread32(rng_base + RNG_CTRL_OFFSET); in iproc_rng200_restart()
71 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); in iproc_rng200_restart()
75 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); in iproc_rng200_restart()
79 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); in iproc_rng200_restart()
83 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); in iproc_rng200_restart()
88 val = ioread32(rng_base + RNG_CTRL_OFFSET); in iproc_rng200_restart()
110 status = ioread32(priv->base + RNG_INT_STATUS_OFFSET); in iproc_rng200_read()
122 if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) & in iproc_rng200_read()
127 *(uint32_t *)buf = ioread32(priv->base + in iproc_rng200_read()
133 uint32_t rnd_number = ioread32(priv->base + in iproc_rng200_read()
[all …]
Damd-rng.c75 if (ioread32(priv->iobase + RNGDONE) == 0) { in amd_rng_read()
85 *data = ioread32(priv->iobase + RNGDATA); in amd_rng_read()
/linux-4.19.296/drivers/rtc/
Drtc-asm9260.c124 isr = ioread32(priv->iobase + HW_CIIR); in asm9260_rtc_irq()
145 ctime0 = ioread32(priv->iobase + HW_CTIME0); in asm9260_rtc_read_time()
146 ctime1 = ioread32(priv->iobase + HW_CTIME1); in asm9260_rtc_read_time()
147 ctime2 = ioread32(priv->iobase + HW_CTIME2); in asm9260_rtc_read_time()
149 if (ctime1 != ioread32(priv->iobase + HW_CTIME1)) { in asm9260_rtc_read_time()
154 ctime0 = ioread32(priv->iobase + HW_CTIME0); in asm9260_rtc_read_time()
155 ctime1 = ioread32(priv->iobase + HW_CTIME1); in asm9260_rtc_read_time()
156 ctime2 = ioread32(priv->iobase + HW_CTIME2); in asm9260_rtc_read_time()
199 alrm->time.tm_year = ioread32(priv->iobase + HW_ALYEAR); in asm9260_rtc_read_alarm()
200 alrm->time.tm_mon = ioread32(priv->iobase + HW_ALMON); in asm9260_rtc_read_alarm()
[all …]
/linux-4.19.296/drivers/cpufreq/
Dpcc-cpufreq.c162 ioread32(pcch_virt_addr + pcc_cpu_data->output_offset); in pcc_get_freq()
174 curr_freq = (((ioread32(&pcch_hdr->nominal) * (output_buffer & 0xff)) in pcc_get_freq()
221 / (ioread32(&pcch_hdr->nominal) * 1000)) << 8); in pcc_cpufreq_target()
462 mem_resource->minimum, ioread32(&pcch_hdr->signature), in pcc_cpufreq_probe()
464 ioread8(&pcch_hdr->minor), ioread32(&pcch_hdr->features), in pcc_cpufreq_probe()
466 ioread32(&pcch_hdr->latency)); in pcc_cpufreq_probe()
473 ioread32(&pcch_hdr->minimum_time), in pcc_cpufreq_probe()
474 ioread32(&pcch_hdr->maximum_time), in pcc_cpufreq_probe()
475 ioread32(&pcch_hdr->nominal), in pcc_cpufreq_probe()
476 ioread32(&pcch_hdr->throttled_frequency), in pcc_cpufreq_probe()
[all …]
/linux-4.19.296/drivers/gpio/
Dgpio-ml-ioh.c111 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
125 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr)); in ioh_gpio_get()
137 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_output()
142 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
161 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_input()
180 ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_save_reg_conf()
182 ioread32(&chip->reg->regs[chip->ch].pm); in ioh_gpio_save_reg_conf()
184 ioread32(&chip->reg->regs[chip->ch].ien); in ioh_gpio_save_reg_conf()
186 ioread32(&chip->reg->regs[chip->ch].imask); in ioh_gpio_save_reg_conf()
188 ioread32(&chip->reg->regs[chip->ch].im_0); in ioh_gpio_save_reg_conf()
[all …]
Dgpio-pch.c116 reg_val = ioread32(&chip->reg->po); in pch_gpio_set()
130 return (ioread32(&chip->reg->pi) >> nr) & 1; in pch_gpio_get()
143 reg_val = ioread32(&chip->reg->po); in pch_gpio_direction_output()
150 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); in pch_gpio_direction_output()
166 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); in pch_gpio_direction_input()
180 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); in pch_gpio_save_reg_conf()
181 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); in pch_gpio_save_reg_conf()
182 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); in pch_gpio_save_reg_conf()
183 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); in pch_gpio_save_reg_conf()
184 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); in pch_gpio_save_reg_conf()
[all …]
Dgpio-xgene.c56 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); in xgene_gpio_get()
68 setval = ioread32(chip->base + bank_offset); in __xgene_gpio_set()
94 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); in xgene_gpio_get_direction()
108 dirval = ioread32(chip->base + bank_offset); in xgene_gpio_dir_in()
129 dirval = ioread32(chip->base + bank_offset); in xgene_gpio_dir_out()
147 gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset); in xgene_gpio_suspend()
Dgpio-timberdale.c61 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
84 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
149 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
153 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
154 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
156 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
204 ipr = ioread32(tgpio->membase + TGPIO_IPR); in timbgpio_irq()
Dgpio-aspeed.c324 reg = ioread32(c1); in aspeed_gpio_change_cmd_source()
332 reg = ioread32(c0); in aspeed_gpio_change_cmd_source()
359 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
389 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
443 reg = ioread32(addr); in aspeed_gpio_dir_in()
471 reg = ioread32(addr); in aspeed_gpio_dir_out()
500 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
575 reg = ioread32(addr); in aspeed_gpio_irq_set_mask()
640 reg = ioread32(addr); in aspeed_gpio_set_type()
645 reg = ioread32(addr); in aspeed_gpio_set_type()
[all …]
/linux-4.19.296/drivers/ptp/
Dptp_pch.c153 val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH); in pch_eth_enable_set()
162 lo = ioread32(&regs->systime_lo); in pch_systime_read()
163 hi = ioread32(&regs->systime_hi); in pch_systime_read()
188 val = ioread32(&chip->regs->control) | PCH_TSC_RESET; in pch_block_reset()
199 val = ioread32(&chip->regs->ch_control); in pch_ch_control_read()
218 val = ioread32(&chip->regs->ch_event); in pch_ch_event_read()
237 val = ioread32(&chip->regs->src_uuid_lo); in pch_src_uuid_lo_read()
248 val = ioread32(&chip->regs->src_uuid_hi); in pch_src_uuid_hi_read()
260 lo = ioread32(&chip->regs->rx_snap_lo); in pch_rx_snap_read()
261 hi = ioread32(&chip->regs->rx_snap_hi); in pch_rx_snap_read()
[all …]
/linux-4.19.296/drivers/pci/switch/
Dswitchtec.c169 stuser->status = ioread32(&stdev->mmio_mrpc->status); in mrpc_complete_cmd()
179 stuser->return_code = ioread32(&stdev->mmio_mrpc->ret_value); in mrpc_complete_cmd()
220 status = ioread32(&stdev->mmio_mrpc->status); in mrpc_timeout_work()
239 ver = ioread32(&stdev->mmio_sys_info->device_version); in device_version_show()
251 ver = ioread32(&stdev->mmio_sys_info->firmware_version); in fw_version_show()
531 info.flash_length = ioread32(&fi->flash_length); in ioctl_flash_info()
543 info->address = ioread32(&pi->address); in set_fw_info_part()
544 info->length = ioread32(&pi->length); in set_fw_info_part()
560 active_addr = ioread32(&fi->active_cfg); in ioctl_flash_part_info()
566 active_addr = ioread32(&fi->active_cfg); in ioctl_flash_part_info()
[all …]
/linux-4.19.296/include/linux/uwb/
Dwhci.h90 return ioread32(addr); in le_readl()
108 value = ioread32(addr); in le_readq()
109 value |= (u64)ioread32(addr + 4) << 32; in le_readq()
/linux-4.19.296/drivers/misc/
Dpch_phub.c159 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); in pch_phub_read_modify_write_reg()
171 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); in pch_phub_save_reg_conf()
172 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); in pch_phub_save_reg_conf()
173 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); in pch_phub_save_reg_conf()
174 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); in pch_phub_save_reg_conf()
176 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); in pch_phub_save_reg_conf()
178 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); in pch_phub_save_reg_conf()
180 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); in pch_phub_save_reg_conf()
182 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); in pch_phub_save_reg_conf()
184 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); in pch_phub_save_reg_conf()
[all …]
Dphantom.c74 ioread32(dev->caddr + PHN_IRQCTL); /* PCI posting */ in phantom_status()
77 ioread32(dev->caddr + PHN_IRQCTL); /* PCI posting */ in phantom_status()
125 ioread32(dev->iaddr); /* PCI posting */ in phantom_ioctl()
145 ioread32(dev->iaddr); /* PCI posting */ in phantom_ioctl()
157 r.value = ioread32(dev->iaddr + r.reg); in phantom_ioctl()
175 rs.values[i] = ioread32(dev->iaddr + i); in phantom_ioctl()
293 ctl = ioread32(dev->iaddr + PHN_CONTROL); in phantom_isr()
315 ioread32(dev->iaddr); /* PCI posting */ in phantom_isr()
396 ioread32(pht->caddr + PHN_IRQCTL); /* PCI posting */ in phantom_probe()
448 ioread32(pht->caddr + PHN_IRQCTL); /* PCI posting */ in phantom_remove()
[all …]
/linux-4.19.296/drivers/ntb/hw/mscc/
Dntb_hw_switchtec.c48 low = ioread32(mmio); in _ioread64()
49 high = ioread32(mmio + sizeof(u32)); in _ioread64()
170 ps = ioread32(&ctl->partition_status) & 0xFFFF; in switchtec_ntb_part_op()
183 ioread32(&ctl->partition_status)); in switchtec_ntb_part_op()
263 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_clr_direct()
285 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_set_direct()
360 widx, ioread32(&ctl->bar_error)); in switchtec_ntb_mw_set_trans()
456 u32 pff = ioread32(&stdev->mmio_part_cfg[partition].vep_pff_inst_id); in switchtec_ntb_part_link_speed()
457 u32 linksta = ioread32(&stdev->mmio_pff_csr[pff].pci_cap_region[13]); in switchtec_ntb_part_link_speed()
787 return ioread32(&sndev->peer_shared->spad[sidx]); in switchtec_ntb_peer_spad_read()
[all …]
/linux-4.19.296/drivers/pci/controller/
Dpci-rcar-gen2.c156 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
183 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG); in rcar_pci_setup_errirq()
203 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG); in rcar_pci_setup()
207 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; in rcar_pci_setup()
242 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG); in rcar_pci_setup()
265 val = ioread32(reg + PCI_COMMAND); in rcar_pci_setup()
/linux-4.19.296/drivers/char/tpm/
Dtpm_crb.c125 if ((ioread32(reg) & mask) == value) in crb_wait_for_reg_32()
131 return ((ioread32(reg) & mask) == value); in crb_wait_for_reg_32()
278 if ((ioread32(&priv->regs_t->ctrl_start) & CRB_START_INVOKE) != in crb_status()
299 if (ioread32(&priv->regs_t->ctrl_sts) & CRB_CTRL_STS_ERROR) in crb_recv()
419 u32 cancel = ioread32(&priv->regs_t->ctrl_cancel); in crb_req_canceled()
586 pa_high = ioread32(&priv->regs_t->ctrl_cmd_pa_high); in crb_map_io()
587 pa_low = ioread32(&priv->regs_t->ctrl_cmd_pa_low); in crb_map_io()
589 cmd_size = ioread32(&priv->regs_t->ctrl_cmd_size); in crb_map_io()
616 rsp_size = ioread32(&priv->regs_t->ctrl_rsp_size); in crb_map_io()
/linux-4.19.296/drivers/ntb/hw/intel/
Dntb_hw_gen1.c306 return ioread32(mmio + (idx << 2)); in ndev_spad_read()
621 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4)); in ndev_ntb_debugfs_read()
625 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 5)); in ndev_ntb_debugfs_read()
639 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4)); in ndev_ntb_debugfs_read()
642 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 5)); in ndev_ntb_debugfs_read()
661 u.v32 = ioread32(mmio + XEON_PBAR4XLAT_OFFSET); in ndev_ntb_debugfs_read()
665 u.v32 = ioread32(mmio + XEON_PBAR5XLAT_OFFSET); in ndev_ntb_debugfs_read()
681 u.v32 = ioread32(mmio + XEON_PBAR4LMT_OFFSET); in ndev_ntb_debugfs_read()
685 u.v32 = ioread32(mmio + XEON_PBAR5LMT_OFFSET); in ndev_ntb_debugfs_read()
708 u.v32 = ioread32(mmio + XEON_SBAR4BASE_OFFSET); in ndev_ntb_debugfs_read()
[all …]
Dntb_hw_intel.h230 low = ioread32(mmio); in _ioread64()
231 high = ioread32(mmio + sizeof(u32)); in _ioread64()
/linux-4.19.296/drivers/thunderbolt/
Dnhi.c76 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); in ring_interrupt_active()
85 ivr = ioread32(ivr_base + step); in ring_interrupt_active()
92 old = ioread32(ring->nhi->iobase + reg); in ring_interrupt_active()
124 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i); in nhi_disable_interrupts()
341 val = ioread32(ring->nhi->iobase + reg); in __ring_interrupt_mask()
775 val = ioread32(nhi->iobase + REG_INMAIL_CMD); in nhi_mailbox_cmd()
782 val = ioread32(nhi->iobase + REG_INMAIL_CMD); in nhi_mailbox_cmd()
807 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD); in nhi_mailbox_mode()
832 value = ioread32(nhi->iobase in nhi_interrupt_work()
1048 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff; in nhi_probe()
/linux-4.19.296/drivers/clk/axs10x/
Dpll_clock.c109 return ioread32(clk->base + reg); in axs10x_pll_read()
197 if (!(ioread32(clk->lock) & PLL_LOCK)) in axs10x_pll_set_rate()
200 if (ioread32(clk->lock) & PLL_ERROR) in axs10x_pll_set_rate()
/linux-4.19.296/include/asm-generic/
Diomap.h32 extern unsigned int ioread32(void __iomem *);
/linux-4.19.296/drivers/virtio/
Dvirtio_pci_legacy.c29 return ioread32(vp_dev->ioaddr + VIRTIO_PCI_HOST_FEATURES); in vp_get_features()
132 if (!num || ioread32(vp_dev->ioaddr + VIRTIO_PCI_QUEUE_PFN)) in setup_vq()

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