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Searched refs:mdiv (Results 1 – 20 of 20) sorted by relevance

/linux-4.19.296/drivers/clk/bcm/
Dclk-ns2.c62 .mdiv = REG_VAL(0x18, 0, 8),
68 .mdiv = REG_VAL(0x18, 8, 8),
74 .mdiv = REG_VAL(0x14, 0, 8),
80 .mdiv = REG_VAL(0x14, 8, 8),
86 .mdiv = REG_VAL(0x14, 16, 8),
92 .mdiv = REG_VAL(0x14, 24, 8),
124 .mdiv = REG_VAL(0x18, 0, 8),
130 .mdiv = REG_VAL(0x18, 8, 8),
136 .mdiv = REG_VAL(0x14, 0, 8),
142 .mdiv = REG_VAL(0x14, 8, 8),
[all …]
Dclk-sr.c63 .mdiv = REG_VAL(0x18, 0, 9),
69 .mdiv = REG_VAL(0x18, 10, 9),
75 .mdiv = REG_VAL(0x18, 20, 9),
81 .mdiv = REG_VAL(0x1c, 0, 9),
87 .mdiv = REG_VAL(0x1c, 10, 9),
93 .mdiv = REG_VAL(0x1c, 20, 9),
123 .mdiv = REG_VAL(0x18, 0, 9),
129 .mdiv = REG_VAL(0x18, 10, 9),
135 .mdiv = REG_VAL(0x18, 20, 9),
141 .mdiv = REG_VAL(0x1c, 0, 9),
[all …]
Dclk-cygnus.c76 .mdiv = REG_VAL(0x20, 0, 8),
82 .mdiv = REG_VAL(0x20, 10, 8),
88 .mdiv = REG_VAL(0x20, 20, 8),
94 .mdiv = REG_VAL(0x24, 0, 8),
100 .mdiv = REG_VAL(0x24, 10, 8),
106 .mdiv = REG_VAL(0x24, 20, 8),
134 .mdiv = REG_VAL(0x8, 0, 8),
140 .mdiv = REG_VAL(0x8, 10, 8),
146 .mdiv = REG_VAL(0x8, 20, 8),
152 .mdiv = REG_VAL(0xc, 0, 8),
[all …]
Dclk-iproc-armpll.c119 int mdiv; in __get_mdiv() local
127 mdiv = 1; in __get_mdiv()
132 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK; in __get_mdiv()
133 if (mdiv == 0) in __get_mdiv()
134 mdiv = 256; in __get_mdiv()
139 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK; in __get_mdiv()
140 if (mdiv == 0) in __get_mdiv()
141 mdiv = 256; in __get_mdiv()
145 mdiv = -EFAULT; in __get_mdiv()
148 return mdiv; in __get_mdiv()
[all …]
Dclk-nsp.c61 .mdiv = REG_VAL(0x18, 16, 8),
67 .mdiv = REG_VAL(0x18, 8, 8),
73 .mdiv = REG_VAL(0x18, 0, 8),
79 .mdiv = REG_VAL(0x1c, 16, 8),
85 .mdiv = REG_VAL(0x1c, 8, 8),
91 .mdiv = REG_VAL(0x1c, 0, 8),
118 .mdiv = REG_VAL(0x8, 24, 8),
124 .mdiv = REG_VAL(0x8, 16, 8),
130 .mdiv = REG_VAL(0x8, 8, 8),
Dclk-iproc-pll.c627 unsigned int mdiv; in iproc_clk_recalc_rate() local
633 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_recalc_rate()
634 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); in iproc_clk_recalc_rate()
635 if (mdiv == 0) in iproc_clk_recalc_rate()
636 mdiv = 256; in iproc_clk_recalc_rate()
639 rate = parent_rate / (mdiv * 2); in iproc_clk_recalc_rate()
641 rate = parent_rate / mdiv; in iproc_clk_recalc_rate()
687 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_set_rate()
689 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
691 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
[all …]
Dclk-iproc.h197 struct iproc_clk_reg_op mdiv; member
/linux-4.19.296/drivers/clk/samsung/
Dclk-pll.c111 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
115 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()
119 fvco *= (mdiv + 8); in samsung_pll2126_recalc_rate()
144 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
148 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()
152 fvco *= (2 * (mdiv + 8)); in samsung_pll3000_recalc_rate()
181 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
185 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; in samsung_pll35xx_recalc_rate()
189 fvco *= mdiv; in samsung_pll35xx_recalc_rate()
203 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
[all …]
Dclk-pll.h53 .mdiv = (_m), \
62 .mdiv = (_m), \
71 .mdiv = (_m), \
80 .mdiv = (_m), \
90 .mdiv = (_m), \
100 .mdiv = (_m), \
111 .mdiv = (_m), \
125 unsigned int mdiv; member
/linux-4.19.296/drivers/clk/st/
Dclkgen-fsyn.c39 unsigned long mdiv; member
62 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; member
97 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
148 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
497 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); in quadfs_fsynth_program_rate()
582 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; in clk_fs660c32_dig_get_rate()
606 fs_tmp.mdiv = (unsigned long) m; in clk_fs660c32_get_pe()
616 fs->mdiv = m; in clk_fs660c32_get_pe()
662 fs_tmp.mdiv = fs->mdiv; in clk_fs660c32_dig_get_params()
695 params->mdiv = CLKGEN_READ(fs, mdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
[all …]
Dclkgen-pll.c50 struct clkgen_field mdiv; member
175 unsigned long mdiv; member
/linux-4.19.296/drivers/clk/socfpga/
Dclk-pll-s10.c33 unsigned long mdiv; in clk_pll_recalc_rate() local
47 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; in clk_pll_recalc_rate()
48 vco_freq = (unsigned long long)vco_freq * (mdiv + 6); in clk_pll_recalc_rate()
/linux-4.19.296/drivers/media/dvb-frontends/
Dhorus3a.c181 u8 mdiv = 0; in horus3a_set_params() local
199 mdiv = 1; in horus3a_set_params()
202 mdiv = 0; in horus3a_set_params()
305 data[4] = (u8)(mdiv << 7); in horus3a_set_params()
Dstb0899_drv.c571 u8 mdiv = 0; in stb0899_set_mclk() local
574 mdiv = ((6 * Mclk) / state->config->xtal_freq) - 1; in stb0899_set_mclk()
575 dprintk(state->verbose, FE_DEBUG, 1, "mdiv=%d", mdiv); in stb0899_set_mclk()
577 stb0899_write_reg(state, STB0899_NCOARSE, mdiv); in stb0899_set_mclk()
/linux-4.19.296/drivers/iio/frequency/
Dadf4350.c135 u16 mdiv, r_cnt = 0; in adf4350_set_freq() local
143 mdiv = 75; in adf4350_set_freq()
146 mdiv = 23; in adf4350_set_freq()
182 } while (mdiv > st->r0_int); in adf4350_set_freq()
/linux-4.19.296/drivers/i2c/busses/
Di2c-octeon-core.c661 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; in octeon_i2c_set_clock() local
689 mdiv = mdiv_idx; in octeon_i2c_set_clock()
696 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); in octeon_i2c_set_clock()
/linux-4.19.296/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c353 u32 ctrl, mdiv, msel, npdiv; in lpc18xx_pll0_recalc_rate() local
356 mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); in lpc18xx_pll0_recalc_rate()
367 msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK); in lpc18xx_pll0_recalc_rate()
/linux-4.19.296/drivers/cpufreq/
Dtegra186-cpufreq.c183 data->mdiv / 1000; in init_vhint_table()
/linux-4.19.296/include/soc/tegra/
Dbpmp-abi.h1598 uint16_t mdiv; /**< input divider value */ member
/linux-4.19.296/drivers/clk/tegra/
Dclk-pll.c1162 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv() local
1165 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1166 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()