| /linux-4.19.296/drivers/clk/ |
| D | clk-multiplier.c | 17 static unsigned long __get_mult(struct clk_multiplier *mult, in __get_mult() argument
21 if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST) in __get_mult()
30 struct clk_multiplier *mult = to_clk_multiplier(hw); in clk_multiplier_recalc_rate() local
33 val = clk_readl(mult->reg) >> mult->shift; in clk_multiplier_recalc_rate()
34 val &= GENMASK(mult->width - 1, 0); in clk_multiplier_recalc_rate()
36 if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS) in clk_multiplier_recalc_rate()
55 struct clk_multiplier *mult = to_clk_multiplier(hw); in __bestmult() local
66 !(mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)) in __bestmult()
104 struct clk_multiplier *mult = to_clk_multiplier(hw); in clk_multiplier_round_rate() local
106 mult->width, mult->flags); in clk_multiplier_round_rate()
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| D | clk-fixed-factor.c | 33 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
46 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
50 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
74 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor() argument
86 fix->mult = mult; in clk_hw_register_fixed_factor()
109 unsigned int mult, unsigned int div) in clk_register_fixed_factor() argument
113 hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult, in clk_register_fixed_factor()
157 u32 div, mult; in _of_fixed_factor_clk_setup() local
166 if (of_property_read_u32(node, "clock-mult", &mult)) { in _of_fixed_factor_clk_setup()
179 mult, div); in _of_fixed_factor_clk_setup()
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| D | clk-gemini.c | 278 unsigned int mult, div; in gemini_clk_probe() local
328 mult = 1; in gemini_clk_probe()
331 mult = 3; in gemini_clk_probe()
334 hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div); in gemini_clk_probe()
359 mult = 1; in gemini_clk_probe()
397 unsigned int mult, div; in gemini_cc_init() local
444 mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK); in gemini_cc_init()
448 mult *= 2; in gemini_cc_init()
449 hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div); in gemini_cc_init()
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| /linux-4.19.296/drivers/clk/sunxi-ng/ |
| D | ccu_mult.c | 17 unsigned long mult, min, max; member
21 struct _ccu_mult *mult) in ccu_mult_find_best() argument
26 if (_mult < mult->min) in ccu_mult_find_best()
27 _mult = mult->min; in ccu_mult_find_best()
29 if (_mult > mult->max) in ccu_mult_find_best()
30 _mult = mult->max; in ccu_mult_find_best()
32 mult->mult = _mult; in ccu_mult_find_best()
44 _cm.min = cm->mult.min; in ccu_mult_round_rate()
46 if (cm->mult.max) in ccu_mult_round_rate()
47 _cm.max = cm->mult.max; in ccu_mult_round_rate()
[all …]
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| /linux-4.19.296/drivers/clk/sunxi/ |
| D | clk-sun4i-pll3.c | 32 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
56 mult = kzalloc(sizeof(*mult), GFP_KERNEL); in sun4i_a10_pll3_setup()
57 if (!mult) in sun4i_a10_pll3_setup()
60 mult->reg = reg; in sun4i_a10_pll3_setup()
61 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup()
62 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup()
63 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
68 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup()
88 kfree(mult); in sun4i_a10_pll3_setup()
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| D | clk-a10-pll2.c | 52 struct clk_multiplier *mult; in sun4i_pll2_setup() local
91 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); in sun4i_pll2_setup()
92 if (!mult) in sun4i_pll2_setup()
95 mult->reg = reg; in sun4i_pll2_setup()
96 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup()
97 mult->width = 7; in sun4i_pll2_setup()
98 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup()
100 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
106 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup()
176 kfree(mult); in sun4i_pll2_setup()
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| /linux-4.19.296/drivers/clk/mvebu/ |
| D | orion.c | 62 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
67 *mult = 1; in mv88f5181_get_clk_ratio()
70 *mult = 1; in mv88f5181_get_clk_ratio()
73 *mult = 0; in mv88f5181_get_clk_ratio()
130 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
135 *mult = 1; in mv88f5182_get_clk_ratio()
138 *mult = 1; in mv88f5182_get_clk_ratio()
141 *mult = 0; in mv88f5182_get_clk_ratio()
187 int *mult, int *div) in mv88f5281_get_clk_ratio() argument
192 *mult = 1; in mv88f5281_get_clk_ratio()
[all …]
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| D | mv98dx3236.c | 120 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument
128 *mult = mv98dx4251_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
131 *mult = mv98dx3236_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
137 *mult = mv98dx4251_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
140 *mult = mv98dx3236_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
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| D | armada-39x.c | 94 void __iomem *sar, int id, int *mult, int *div) in armada_39x_get_clk_ratio() argument
98 *mult = 1; in armada_39x_get_clk_ratio()
102 *mult = 1; in armada_39x_get_clk_ratio()
106 *mult = 1; in armada_39x_get_clk_ratio()
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| D | armada-370.c | 116 void __iomem *sar, int id, int *mult, int *div) in a370_get_clk_ratio() argument
123 *mult = a370_nbclk_ratios[opt][0]; in a370_get_clk_ratio()
127 *mult = a370_hclk_ratios[opt][0]; in a370_get_clk_ratio()
131 *mult = a370_dramclk_ratios[opt][0]; in a370_get_clk_ratio()
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| D | kirkwood.c | 129 void __iomem *sar, int id, int *mult, int *div) in kirkwood_get_clk_ratio() argument
135 *mult = kirkwood_cpu_l2_ratios[opt][0]; in kirkwood_get_clk_ratio()
143 *mult = kirkwood_cpu_ddr_ratios[opt][0]; in kirkwood_get_clk_ratio()
169 void __iomem *sar, int id, int *mult, int *div) in mv88f6180_get_clk_ratio() argument
175 *mult = 1; in mv88f6180_get_clk_ratio()
183 *mult = mv88f6180_cpu_ddr_ratios[opt][0]; in mv88f6180_get_clk_ratio()
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| D | armada-xp.c | 138 void __iomem *sar, int id, int *mult, int *div) in axp_get_clk_ratio() argument
151 *mult = axp_nbclk_ratios[opt][0]; in axp_get_clk_ratio()
155 *mult = axp_hclk_ratios[opt][0]; in axp_get_clk_ratio()
159 *mult = axp_dramclk_ratios[opt][0]; in axp_get_clk_ratio()
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| /linux-4.19.296/drivers/clk/renesas/ |
| D | rcar-gen2-cpg.c | 60 unsigned int mult; in cpg_z_clk_recalc_rate() local
64 mult = 32 - val; in cpg_z_clk_recalc_rate()
66 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
73 unsigned int mult; in cpg_z_clk_round_rate() local
78 mult = div_u64((u64)rate * 32, prate); in cpg_z_clk_round_rate()
79 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
81 return *parent_rate / 32 * mult; in cpg_z_clk_round_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
92 mult = div_u64((u64)rate * 32, parent_rate); in cpg_z_clk_set_rate()
93 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
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| D | clk-rcar-gen2.c | 62 unsigned int mult; in cpg_z_clk_recalc_rate() local
66 mult = 32 - val; in cpg_z_clk_recalc_rate()
68 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
75 unsigned int mult; in cpg_z_clk_round_rate() local
80 mult = div_u64((u64)rate * 32, prate); in cpg_z_clk_round_rate()
81 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
83 return *parent_rate / 32 * mult; in cpg_z_clk_round_rate()
90 unsigned int mult; in cpg_z_clk_set_rate() local
94 mult = div_u64((u64)rate * 32, parent_rate); in cpg_z_clk_set_rate()
95 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
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| D | rcar-gen3-cpg.c | 93 unsigned int mult; in cpg_z_clk_recalc_rate() local
97 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
100 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); in cpg_z_clk_recalc_rate()
108 unsigned int mult; in cpg_z_clk_round_rate() local
110 mult = div_u64(rate * 32ULL, prate); in cpg_z_clk_round_rate()
111 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
113 return (u64)prate * mult / 32; in cpg_z_clk_round_rate()
120 unsigned int mult; in cpg_z_clk_set_rate() local
125 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); in cpg_z_clk_set_rate()
126 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
[all …]
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| D | clk-sh73a0.c | 83 unsigned int mult = 1; in sh73a0_cpg_register_clock() local
114 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
118 mult *= 2; in sh73a0_cpg_register_clock()
126 mult = __raw_readl(dsi_reg); in sh73a0_cpg_register_clock()
127 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock()
128 mult = 1; in sh73a0_cpg_register_clock()
130 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock()
156 mult, div); in sh73a0_cpg_register_clock()
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| D | clk-rz.c | 57 unsigned mult; in rz_cpg_register_clock() local
64 mult = cpg_mode ? (32 / 4) : 30; in rz_cpg_register_clock()
66 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); in rz_cpg_register_clock()
84 mult = frqcr_tab[val]; in rz_cpg_register_clock()
85 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3); in rz_cpg_register_clock()
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| D | clk-r8a73a4.c | 69 unsigned int mult = 1; in r8a73a4_cpg_register_clock() local
101 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock()
109 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock()
154 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock()
164 mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); in r8a73a4_cpg_register_clock()
183 mult, div); in r8a73a4_cpg_register_clock()
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| D | clk-r8a7740.c | 71 unsigned int mult = 1; in r8a7740_cpg_register_clock() local
103 mult = ((value >> 24) & 0x7f) + 1; in r8a7740_cpg_register_clock()
107 mult = ((value >> 24) & 0x7f) + 1; in r8a7740_cpg_register_clock()
112 mult = ((value >> 24) & 0x3f) + 1; in r8a7740_cpg_register_clock()
139 mult, div); in r8a7740_cpg_register_clock()
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| D | clk-r8a7779.c | 98 unsigned int mult = 1; in r8a7779_cpg_register_clock() local
103 mult = plla_mult; in r8a7779_cpg_register_clock()
106 mult = config->z_mult; in r8a7779_cpg_register_clock()
119 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); in r8a7779_cpg_register_clock()
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| /linux-4.19.296/drivers/clk/ti/ |
| D | fixed-factor.c | 41 u32 div, mult; in of_ti_fixed_factor_clk_setup() local
49 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { in of_ti_fixed_factor_clk_setup()
60 mult, div); in of_ti_fixed_factor_clk_setup()
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| /linux-4.19.296/drivers/cpufreq/ |
| D | longhaul.c | 108 static unsigned int calc_speed(int mult) in calc_speed() argument
111 khz = (mult/10)*fsb; in calc_speed()
112 if (mult%10) in calc_speed()
249 int speed, mult; in longhaul_setstate() local
259 mult = mults[mults_index & 0x1f]; in longhaul_setstate()
260 if (mult == -1) in longhaul_setstate()
263 speed = calc_speed(mult); in longhaul_setstate()
275 fsb, mult/10, mult%10, print_speed(speed/1000)); in longhaul_setstate()
406 static int guess_fsb(int mult) in guess_fsb() argument
414 f_max = ((speeds[i] * mult) + 50) / 100; in guess_fsb()
[all …]
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| D | speedstep-lib.c | 177 u32 msr_lo, msr_hi, mult; in pentium4_get_frequency() local
217 mult = msr_lo >> 24; in pentium4_get_frequency()
220 fsb, mult, (fsb * mult)); in pentium4_get_frequency()
222 ret = (fsb * mult); in pentium4_get_frequency()
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| /linux-4.19.296/drivers/clk/davinci/ |
| D | pll.c | 120 u32 mult; in davinci_pll_recalc_rate() local
122 mult = readl(pll->base + PLLM) & pll->pllm_mask; in davinci_pll_recalc_rate()
123 rate *= mult + 1; in davinci_pll_recalc_rate()
136 u32 mult; in davinci_pll_determine_rate() local
143 mult = rate / parent_rate; in davinci_pll_determine_rate()
144 best_rate = parent_rate * mult; in davinci_pll_determine_rate()
151 if (mult < pll->pllm_min || mult > pll->pllm_max) in davinci_pll_determine_rate()
162 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { in davinci_pll_determine_rate()
163 parent_rate = clk_hw_round_rate(parent, rate / mult); in davinci_pll_determine_rate()
164 r = parent_rate * mult; in davinci_pll_determine_rate()
[all …]
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| /linux-4.19.296/include/linux/ |
| D | clocksource.h | 83 u32 mult; member
184 static inline s64 clocksource_cyc2ns(u64 cycles, u32 mult, u32 shift) in clocksource_cyc2ns() argument
186 return ((u64) cycles * mult) >> shift; in clocksource_cyc2ns()
202 clocks_calc_max_nsecs(u32 mult, u32 shift, u32 maxadj, u64 mask, u64 *max_cycles);
204 clocks_calc_mult_shift(u32 *mult, u32 *shift, u32 from, u32 to, u32 minsec);
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