1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * linux/drivers/char/hpilo.h
4  *
5  * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
6  *	David Altobelli <david.altobelli@hp.com>
7  */
8 #ifndef __HPILO_H
9 #define __HPILO_H
10 
11 #define ILO_NAME "hpilo"
12 
13 /* max number of open channel control blocks per device, hw limited to 32 */
14 #define MAX_CCB	       24
15 /* min number of open channel control blocks per device, hw limited to 32 */
16 #define MIN_CCB		8
17 /* max number of supported devices */
18 #define MAX_ILO_DEV	1
19 /* max number of files */
20 #define MAX_OPEN	(MAX_CCB * MAX_ILO_DEV)
21 /* total wait time in usec */
22 #define MAX_WAIT_TIME	10000
23 /* per spin wait time in usec */
24 #define WAIT_TIME	10
25 /* spin counter for open/close delay */
26 #define MAX_WAIT	(MAX_WAIT_TIME / WAIT_TIME)
27 
28 /*
29  * Per device, used to track global memory allocations.
30  */
31 struct ilo_hwinfo {
32 	/* mmio registers on device */
33 	char __iomem *mmio_vaddr;
34 
35 	/* doorbell registers on device */
36 	char __iomem *db_vaddr;
37 
38 	/* shared memory on device used for channel control blocks */
39 	char __iomem *ram_vaddr;
40 
41 	/* files corresponding to this device */
42 	struct ccb_data *ccb_alloc[MAX_CCB];
43 
44 	struct pci_dev *ilo_dev;
45 
46 	/*
47 	 * open_lock      serializes ccb_cnt during open and close
48 	 * [ irq disabled ]
49 	 * -> alloc_lock  used when adding/removing/searching ccb_alloc,
50 	 *                which represents all ccbs open on the device
51 	 * --> fifo_lock  controls access to fifo queues shared with hw
52 	 *
53 	 * Locks must be taken in this order, but open_lock and alloc_lock
54 	 * are optional, they do not need to be held in order to take a
55 	 * lower level lock.
56 	 */
57 	spinlock_t open_lock;
58 	spinlock_t alloc_lock;
59 	spinlock_t fifo_lock;
60 
61 	struct cdev cdev;
62 };
63 
64 /* offset from mmio_vaddr for enabling doorbell interrupts */
65 #define DB_IRQ		0xB2
66 /* offset from mmio_vaddr for outbound communications */
67 #define DB_OUT		0xD4
68 /* DB_OUT reset bit */
69 #define DB_RESET	26
70 
71 /*
72  * Channel control block. Used to manage hardware queues.
73  * The format must match hw's version.  The hw ccb is 128 bytes,
74  * but the context area shouldn't be touched by the driver.
75  */
76 #define ILOSW_CCB_SZ	64
77 #define ILOHW_CCB_SZ 	128
78 struct ccb {
79 	union {
80 		char *send_fifobar;
81 		u64 send_fifobar_pa;
82 	} ccb_u1;
83 	union {
84 		char *send_desc;
85 		u64 send_desc_pa;
86 	} ccb_u2;
87 	u64 send_ctrl;
88 
89 	union {
90 		char *recv_fifobar;
91 		u64 recv_fifobar_pa;
92 	} ccb_u3;
93 	union {
94 		char *recv_desc;
95 		u64 recv_desc_pa;
96 	} ccb_u4;
97 	u64 recv_ctrl;
98 
99 	union {
100 		char __iomem *db_base;
101 		u64 padding5;
102 	} ccb_u5;
103 
104 	u64 channel;
105 
106 	/* unused context area (64 bytes) */
107 };
108 
109 /* ccb queue parameters */
110 #define SENDQ		1
111 #define RECVQ 		2
112 #define NR_QENTRY    	4
113 #define L2_QENTRY_SZ 	12
114 
115 /* ccb ctrl bitfields */
116 #define CTRL_BITPOS_L2SZ             0
117 #define CTRL_BITPOS_FIFOINDEXMASK    4
118 #define CTRL_BITPOS_DESCLIMIT        18
119 #define CTRL_BITPOS_A                30
120 #define CTRL_BITPOS_G                31
121 
122 /* ccb doorbell macros */
123 #define L2_DB_SIZE		14
124 #define ONE_DB_SIZE		(1 << L2_DB_SIZE)
125 
126 /*
127  * Per fd structure used to track the ccb allocated to that dev file.
128  */
129 struct ccb_data {
130 	/* software version of ccb, using virtual addrs */
131 	struct ccb  driver_ccb;
132 
133 	/* hardware version of ccb, using physical addrs */
134 	struct ccb  ilo_ccb;
135 
136 	/* hardware ccb is written to this shared mapped device memory */
137 	struct ccb __iomem *mapped_ccb;
138 
139 	/* dma'able memory used for send/recv queues */
140 	void       *dma_va;
141 	dma_addr_t  dma_pa;
142 	size_t      dma_size;
143 
144 	/* pointer to hardware device info */
145 	struct ilo_hwinfo *ilo_hw;
146 
147 	/* queue for this ccb to wait for recv data */
148 	wait_queue_head_t ccb_waitq;
149 
150 	/* usage count, to allow for shared ccb's */
151 	int	    ccb_cnt;
152 
153 	/* open wanted exclusive access to this ccb */
154 	int	    ccb_excl;
155 };
156 
157 /*
158  * FIFO queue structure, shared with hw.
159  */
160 #define ILO_START_ALIGN	4096
161 #define ILO_CACHE_SZ 	 128
162 struct fifo {
163     u64 nrents;	/* user requested number of fifo entries */
164     u64 imask;  /* mask to extract valid fifo index */
165     u64 merge;	/*  O/C bits to merge in during enqueue operation */
166     u64 reset;	/* set to non-zero when the target device resets */
167     u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
168 
169     u64 head;
170     u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
171 
172     u64 tail;
173     u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
174 
175     u64 fifobar[1];
176 };
177 
178 /* convert between struct fifo, and the fifobar, which is saved in the ccb */
179 #define FIFOHANDLESIZE (sizeof(struct fifo) - sizeof(u64))
180 #define FIFOBARTOHANDLE(_fifo) \
181 	((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
182 
183 /* the number of qwords to consume from the entry descriptor */
184 #define ENTRY_BITPOS_QWORDS      0
185 /* descriptor index number (within a specified queue) */
186 #define ENTRY_BITPOS_DESCRIPTOR  10
187 /* state bit, fifo entry consumed by consumer */
188 #define ENTRY_BITPOS_C           22
189 /* state bit, fifo entry is occupied */
190 #define ENTRY_BITPOS_O           23
191 
192 #define ENTRY_BITS_QWORDS        10
193 #define ENTRY_BITS_DESCRIPTOR    12
194 #define ENTRY_BITS_C             1
195 #define ENTRY_BITS_O             1
196 #define ENTRY_BITS_TOTAL	\
197 	(ENTRY_BITS_C + ENTRY_BITS_O + \
198 	 ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
199 
200 /* extract various entry fields */
201 #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
202 #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
203 #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
204 #define ENTRY_MASK_QWORDS \
205 	(((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
206 #define ENTRY_MASK_DESCRIPTOR \
207 	(((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
208 
209 #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
210 
211 #endif /* __HPILO_H */
212