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/linux-4.19.296/drivers/clk/mediatek/
Dclk-pll.c68 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
78 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
117 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, in mtk_pll_set_rate_regs() argument
142 val |= pcw << pll->data->pcw_shift; in mtk_pll_set_rate_regs()
170 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
202 *pcw = (u32)_pcw; in mtk_pll_calc_values()
209 u32 pcw = 0; in mtk_pll_set_rate() local
212 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_pll_set_rate()
213 mtk_pll_set_rate_regs(pll, pcw, postdiv); in mtk_pll_set_rate()
223 u32 pcw; in mtk_pll_recalc_rate() local
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