Searched refs:pll_bypass (Results 1 – 7 of 7) sorted by relevance
18 bool pll_bypass; /* Choose whether to bypass the PLL */ member
21 u8 pll_bypass:1; member
123 u8 pll_bypass; member
546 && !cfg->io.pll_bypass) { in dib0090_reset_digital()582 if (cfg->io.pll_bypass) { in dib0090_reset_digital()583 PllCfg |= (cfg->io.pll_bypass << 15); in dib0090_reset_digital()617 …>io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) { in dib0090_fw_reset_digital()653 if (cfg->io.pll_bypass) { in dib0090_fw_reset_digital()654 PllCfg |= (cfg->io.pll_bypass << 15); in dib0090_fw_reset_digital()
401 reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) | in dib7000m_reset_pll()442 clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3); in dib7000mc_reset_pll()
461 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15)); in dib7000p_reset_pll()471 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff); in dib7000p_reset_pll()
711 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); in dib8000_reset_pll()737 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); in dib8000_reset_pll()