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Searched refs:pll_prediv (Results 1 – 6 of 6) sorted by relevance

/linux-4.19.296/drivers/media/dvb-frontends/
Ddib0090.h23 u8 pll_prediv:6; member
Ddibx000_common.h119 u8 pll_prediv; member
Ddib8000.c703 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
734 (pll->pll_prediv)); in dib8000_reset_pll()
753 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; in dib8000_update_pll()
760 if ((pll == NULL) || (pll->pll_prediv == prediv && in dib8000_update_pll()
764 …iv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->p… in dib8000_update_pll()
773 (pll->pll_prediv & 0x3f)); in dib8000_update_pll()
779 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; in dib8000_update_pll()
799 …div: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv); in dib8000_update_pll()
801 if (state->cfg.pll->pll_prediv != oldprediv) { in dib8000_update_pll()
805 … %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll-… in dib8000_update_pll()
[all …]
Ddib7000p.c456 …e, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv)); in dib7000p_reset_pll()
470 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
503 if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { in dib7000p_update_pll()
504 …div: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pl… in dib7000p_update_pll()
509 …dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f… in dib7000p_update_pll()
514 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */ in dib7000p_update_pll()
Ddib0090.c545 … != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_s… in dib0090_reset_digital()
557 …<< 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv); in dib0090_reset_digital()
617 … != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pl… in dib0090_fw_reset_digital()
628 …<< 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv); in dib0090_fw_reset_digital()
Ddib7000m.c418 reg_910 |= (bw->pll_prediv << 5); in dib7000m_reset_pll()
434 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()