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Searched refs:prate (Results 1 – 25 of 86) sorted by relevance

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/linux-4.19.296/drivers/clk/spear/
Dclk-frac-synth.c44 static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, in frac_calc_rate() argument
50 prate /= 10000; in frac_calc_rate()
51 prate <<= 14; in frac_calc_rate()
52 prate /= (2 * rtbl[index].div); in frac_calc_rate()
53 prate *= 10000; in frac_calc_rate()
55 return prate; in frac_calc_rate()
59 unsigned long *prate) in clk_frac_round_rate() argument
64 return clk_round_rate_index(hw, drate, *prate, frac_calc_rate, in clk_frac_round_rate()
96 unsigned long prate) in clk_frac_set_rate() argument
103 clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt, in clk_frac_set_rate()
Dclk-vco-pll.c70 unsigned long prate, int index, unsigned long *pll_rate) in pll_calc_rate() argument
72 unsigned long rate = prate; in pll_calc_rate()
85 unsigned long *prate, int *index) in clk_pll_round_rate_index() argument
92 if (!prate) { in clk_pll_round_rate_index()
99 vco_prev_rate = *prate; in clk_pll_round_rate_index()
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, in clk_pll_round_rate_index()
106 *prate = vco_prev_rate; in clk_pll_round_rate_index()
117 unsigned long *prate) in clk_pll_round_rate() argument
121 return clk_pll_round_rate_index(hw, drate, prate, &unused); in clk_pll_round_rate()
145 unsigned long prate) in clk_pll_set_rate() argument
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Dclk-gpt-synth.c34 static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, in gpt_calc_rate() argument
40 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1)); in gpt_calc_rate()
42 return prate; in gpt_calc_rate()
46 unsigned long *prate) in clk_gpt_round_rate() argument
51 return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate, in clk_gpt_round_rate()
81 unsigned long prate) in clk_gpt_set_rate() argument
88 clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt, in clk_gpt_set_rate()
Dclk-aux-synth.c44 static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, in aux_calc_rate() argument
51 return (((prate / 10000) * rtbl[index].xscale) / in aux_calc_rate()
56 unsigned long *prate) in clk_aux_round_rate() argument
61 return clk_round_rate_index(hw, drate, *prate, aux_calc_rate, in clk_aux_round_rate()
100 unsigned long prate) in clk_aux_set_rate() argument
107 clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt, in clk_aux_set_rate()
/linux-4.19.296/drivers/clk/meson/
Dsclk-div.c38 unsigned long prate, int maxdiv) in sclk_div_getdiv() argument
40 int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); in sclk_div_getdiv()
46 unsigned long *prate, in sclk_div_bestdiv() argument
60 return sclk_div_getdiv(hw, rate, *prate, maxdiv); in sclk_div_bestdiv()
74 if (rate * i == *prate) in sclk_div_bestdiv()
90 *prate = best_parent; in sclk_div_bestdiv()
96 unsigned long *prate) in sclk_div_round_rate() argument
102 div = sclk_div_bestdiv(hw, rate, prate, sclk); in sclk_div_round_rate()
104 return DIV_ROUND_UP_ULL((u64)*prate, div); in sclk_div_round_rate()
163 unsigned long prate) in sclk_div_set_rate() argument
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Dclk-regmap.c54 unsigned long prate) in clk_regmap_div_recalc_rate() argument
68 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
73 unsigned long *prate) in clk_regmap_div_round_rate() argument
90 return divider_ro_round_rate(hw, rate, prate, div->table, in clk_regmap_div_round_rate()
94 return divider_round_rate(hw, rate, prate, div->table, div->width, in clk_regmap_div_round_rate()
Dgxbb-aoclk-32k.c110 unsigned long prate) in find_cec_32k_freq() argument
115 if (aoclk_cec_32k_table[i].parent_rate == prate && in find_cec_32k_freq()
123 unsigned long *prate) in aoclk_cec_32k_round_rate() argument
126 *prate); in aoclk_cec_32k_round_rate()
/linux-4.19.296/drivers/clk/qcom/
Dclk-alpha-pll.c382 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) in alpha_pll_calc_rate() argument
384 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); in alpha_pll_calc_rate()
388 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, in alpha_pll_round_rate() argument
395 remainder = do_div(quotient, prate); in alpha_pll_round_rate()
406 remainder = do_div(quotient, prate); in alpha_pll_round_rate()
412 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); in alpha_pll_round_rate()
432 u64 a = 0, prate = parent_rate; in clk_alpha_pll_recalc_rate() local
453 return alpha_pll_calc_rate(prate, l, a, alpha_width); in clk_alpha_pll_recalc_rate()
511 unsigned long prate, in __clk_alpha_pll_set_rate() argument
519 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); in __clk_alpha_pll_set_rate()
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Dclk-regmap-divider.c27 unsigned long *prate) in div_round_ro_rate() argument
37 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
42 unsigned long *prate) in div_round_rate() argument
46 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
Dclk-regmap-mux-div.c125 unsigned long prate, u32 src) in __mux_div_set_rate_and_parent() argument
187 unsigned long rate, unsigned long prate) in mux_div_set_rate() argument
191 return __mux_div_set_rate_and_parent(hw, rate, prate, md->src); in mux_div_set_rate()
195 unsigned long prate, u8 index) in mux_div_set_rate_and_parent() argument
199 return __mux_div_set_rate_and_parent(hw, rate, prate, in mux_div_set_rate_and_parent()
203 static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate) in mux_div_recalc_rate() argument
/linux-4.19.296/drivers/rtc/
Drtc-ac100.c128 unsigned long prate) in ac100_clkout_recalc_rate() argument
136 if (prate != AC100_RTC_32K_RATE) { in ac100_clkout_recalc_rate()
139 prate = divider_recalc_rate(hw, prate, div, in ac100_clkout_recalc_rate()
146 return divider_recalc_rate(hw, prate, div, NULL, in ac100_clkout_recalc_rate()
152 unsigned long prate) in ac100_clkout_round_rate() argument
157 if (prate == AC100_RTC_32K_RATE) in ac100_clkout_round_rate()
158 return divider_round_rate(hw, rate, &prate, NULL, in ac100_clkout_round_rate()
163 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); in ac100_clkout_round_rate()
186 unsigned long tmp, prate; in ac100_clkout_determine_rate() local
208 prate = clk_hw_get_rate(parent); in ac100_clkout_determine_rate()
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/linux-4.19.296/drivers/clk/samsung/
Dclk-cpu.c108 unsigned long drate, unsigned long *prate) in exynos_cpuclk_round_rate() argument
111 *prate = clk_hw_round_rate(parent, drate); in exynos_cpuclk_round_rate()
112 return *prate; in exynos_cpuclk_round_rate()
161 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_pre_rate_change()
162 if (cfg_data->prate == 0) in exynos_cpuclk_pre_rate_change()
238 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_post_rate_change()
239 if (cfg_data->prate == 0) in exynos_cpuclk_post_rate_change()
289 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos5433_cpuclk_pre_rate_change()
290 if (cfg_data->prate == 0) in exynos5433_cpuclk_pre_rate_change()
/linux-4.19.296/drivers/clk/axs10x/
Di2s_pll_clock.c88 static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate) in i2s_pll_get_cfg() argument
90 switch (prate) { in i2s_pll_get_cfg()
114 unsigned long *prate) in i2s_pll_round_rate() argument
117 const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate); in i2s_pll_round_rate()
121 dev_err(clk->dev, "invalid parent rate=%ld\n", *prate); in i2s_pll_round_rate()
/linux-4.19.296/drivers/clk/
Dclk-vt8500.c141 unsigned long *prate) in vt8500_dclk_round_rate() argument
149 divisor = *prate / rate; in vt8500_dclk_round_rate()
152 if (rate * divisor < *prate) in vt8500_dclk_round_rate()
163 return *prate / divisor; in vt8500_dclk_round_rate()
607 unsigned long *prate) in vtwm_pll_round_rate() argument
616 ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1); in vtwm_pll_round_rate()
618 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); in vtwm_pll_round_rate()
621 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); in vtwm_pll_round_rate()
623 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
626 ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); in vtwm_pll_round_rate()
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Dclk-divider.c333 unsigned long rate, unsigned long *prate, in divider_round_rate_parent() argument
339 div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags); in divider_round_rate_parent()
341 return DIV_ROUND_UP_ULL((u64)*prate, div); in divider_round_rate_parent()
346 unsigned long rate, unsigned long *prate, in divider_ro_round_rate_parent() argument
359 *prate = clk_hw_round_rate(parent, rate * div); in divider_ro_round_rate_parent()
362 return DIV_ROUND_UP_ULL((u64)*prate, div); in divider_ro_round_rate_parent()
368 unsigned long *prate) in clk_divider_round_rate() argument
379 return divider_ro_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
384 return divider_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
/linux-4.19.296/drivers/clk/imx/
Dclk-pllv3.c125 unsigned long *prate) in clk_pllv3_round_rate() argument
127 unsigned long parent_rate = *prate; in clk_pllv3_round_rate()
173 unsigned long *prate) in clk_pllv3_sys_round_rate() argument
175 unsigned long parent_rate = *prate; in clk_pllv3_sys_round_rate()
234 unsigned long *prate) in clk_pllv3_av_round_rate() argument
236 unsigned long parent_rate = *prate; in clk_pllv3_av_round_rate()
363 unsigned long *prate) in clk_pllv3_vf610_round_rate() argument
365 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate); in clk_pllv3_vf610_round_rate()
367 return clk_pllv3_vf610_mf_to_rate(*prate, mf); in clk_pllv3_vf610_round_rate()
Dclk-pfd.c71 unsigned long *prate) in clk_pfd_round_rate() argument
73 u64 tmp = *prate; in clk_pfd_round_rate()
83 tmp = *prate; in clk_pfd_round_rate()
/linux-4.19.296/drivers/clk/rockchip/
Dclk-pll.c73 unsigned long drate, unsigned long *prate) in rockchip_pll_round_rate() argument
162 unsigned long prate) in rockchip_rk3036_pll_recalc_rate() argument
166 u64 rate64 = prate; in rockchip_rk3036_pll_recalc_rate()
175 u64 frac_rate64 = prate * cur.frac; in rockchip_rk3036_pll_recalc_rate()
247 unsigned long prate) in rockchip_rk3036_pll_set_rate() argument
253 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate()
397 unsigned long prate) in rockchip_rk3066_pll_recalc_rate() argument
401 u64 rate64 = prate; in rockchip_rk3066_pll_recalc_rate()
408 return prate; in rockchip_rk3066_pll_recalc_rate()
480 unsigned long prate) in rockchip_rk3066_pll_set_rate() argument
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/linux-4.19.296/drivers/clk/zte/
Dclk.c82 unsigned long *prate) in zx_pll_round_rate() argument
245 unsigned long *prate) in zx_audio_round_rate() argument
249 if (rate * 2 > *prate) in zx_audio_round_rate()
252 reg = calc_reg(*prate, rate); in zx_audio_round_rate()
253 return calc_rate(reg, *prate); in zx_audio_round_rate()
408 unsigned long *prate) in zx_audio_div_round_rate() argument
413 audio_calc_reg(zx_audio_div, &divt, rate, *prate); in zx_audio_div_round_rate()
415 return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate); in zx_audio_div_round_rate()
/linux-4.19.296/drivers/clk/sunxi-ng/
Dccu_gate.c91 unsigned long *prate) in ccu_gate_round_rate() argument
104 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); in ccu_gate_round_rate()
107 return *prate / div; in ccu_gate_round_rate()
/linux-4.19.296/drivers/clk/mmp/
Dclk-frac.c28 unsigned long *prate) in clk_factor_round_rate() argument
36 rate = (((*prate / 10000) * factor->ftbl[i].den) / in clk_factor_round_rate()
75 unsigned long prate) in clk_factor_set_rate() argument
86 rate = (((prate / 10000) * factor->ftbl[i].den) / in clk_factor_set_rate()
/linux-4.19.296/drivers/clk/h8300/
Dclk-h8s2678.c37 unsigned long *prate) in pll_round_rate() argument
48 offset[i] = abs(rate - (*prate * (1 << i))); in pll_round_rate()
55 return *prate * (1 << m); in pll_round_rate()
/linux-4.19.296/drivers/clk/zynq/
Dpll.c64 unsigned long *prate) in zynq_pll_round_rate() argument
68 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynq_pll_round_rate()
74 return *prate * fbdiv; in zynq_pll_round_rate()
/linux-4.19.296/drivers/clk/renesas/
Dr9a06g032-clocks.c490 unsigned long rate, unsigned long prate) in r9a06g032_div_clamp_div() argument
493 u32 div = DIV_ROUND_UP(prate, rate + 1); in r9a06g032_div_clamp_div()
504 DIV_ROUND_UP(prate, clk->table[i]); in r9a06g032_div_clamp_div()
506 DIV_ROUND_UP(prate, clk->table[i + 1]) - in r9a06g032_div_clamp_div()
521 unsigned long rate, unsigned long *prate) in r9a06g032_div_round_rate() argument
524 u32 div = DIV_ROUND_UP(*prate, rate); in r9a06g032_div_round_rate()
527 hw->clk, rate, *prate, div); in r9a06g032_div_round_rate()
529 clk->min, DIV_ROUND_UP(*prate, clk->min), in r9a06g032_div_round_rate()
530 clk->max, DIV_ROUND_UP(*prate, clk->max)); in r9a06g032_div_round_rate()
532 div = r9a06g032_div_clamp_div(clk, rate, *prate); in r9a06g032_div_round_rate()
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/linux-4.19.296/drivers/clk/tegra/
Dclk-divider.c68 unsigned long *prate) in clk_frac_div_round_rate() argument
72 unsigned long output_rate = *prate; in clk_frac_div_round_rate()
79 return *prate; in clk_frac_div_round_rate()

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