1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53 #include <linux/timecounter.h>
54 #include <linux/ptp_clock_kernel.h>
55
56 enum {
57 MLX5_BOARD_ID_LEN = 64,
58 MLX5_MAX_NAME_LEN = 16,
59 };
60
61 enum {
62 /* one minute for the sake of bringup. Generally, commands must always
63 * complete and we may need to increase this timeout value
64 */
65 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
66 MLX5_CMD_WQ_MAX_NAME = 32,
67 };
68
69 enum {
70 CMD_OWNER_SW = 0x0,
71 CMD_OWNER_HW = 0x1,
72 CMD_STATUS_SUCCESS = 0,
73 };
74
75 enum mlx5_sqp_t {
76 MLX5_SQP_SMI = 0,
77 MLX5_SQP_GSI = 1,
78 MLX5_SQP_IEEE_1588 = 2,
79 MLX5_SQP_SNIFFER = 3,
80 MLX5_SQP_SYNC_UMR = 4,
81 };
82
83 enum {
84 MLX5_MAX_PORTS = 2,
85 };
86
87 enum {
88 MLX5_EQ_VEC_PAGES = 0,
89 MLX5_EQ_VEC_CMD = 1,
90 MLX5_EQ_VEC_ASYNC = 2,
91 MLX5_EQ_VEC_PFAULT = 3,
92 MLX5_EQ_VEC_COMP_BASE,
93 };
94
95 enum {
96 MLX5_MAX_IRQ_NAME = 32
97 };
98
99 enum {
100 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
101 MLX5_ATOMIC_MODE_CX = 2 << 16,
102 MLX5_ATOMIC_MODE_8B = 3 << 16,
103 MLX5_ATOMIC_MODE_16B = 4 << 16,
104 MLX5_ATOMIC_MODE_32B = 5 << 16,
105 MLX5_ATOMIC_MODE_64B = 6 << 16,
106 MLX5_ATOMIC_MODE_128B = 7 << 16,
107 MLX5_ATOMIC_MODE_256B = 8 << 16,
108 };
109
110 enum {
111 MLX5_REG_QPTS = 0x4002,
112 MLX5_REG_QETCR = 0x4005,
113 MLX5_REG_QTCT = 0x400a,
114 MLX5_REG_QPDPM = 0x4013,
115 MLX5_REG_QCAM = 0x4019,
116 MLX5_REG_DCBX_PARAM = 0x4020,
117 MLX5_REG_DCBX_APP = 0x4021,
118 MLX5_REG_FPGA_CAP = 0x4022,
119 MLX5_REG_FPGA_CTRL = 0x4023,
120 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
121 MLX5_REG_PCAP = 0x5001,
122 MLX5_REG_PMTU = 0x5003,
123 MLX5_REG_PTYS = 0x5004,
124 MLX5_REG_PAOS = 0x5006,
125 MLX5_REG_PFCC = 0x5007,
126 MLX5_REG_PPCNT = 0x5008,
127 MLX5_REG_PPTB = 0x500b,
128 MLX5_REG_PBMC = 0x500c,
129 MLX5_REG_PMAOS = 0x5012,
130 MLX5_REG_PUDE = 0x5009,
131 MLX5_REG_PMPE = 0x5010,
132 MLX5_REG_PELC = 0x500e,
133 MLX5_REG_PVLC = 0x500f,
134 MLX5_REG_PCMR = 0x5041,
135 MLX5_REG_PMLP = 0x5002,
136 MLX5_REG_PCAM = 0x507f,
137 MLX5_REG_NODE_DESC = 0x6001,
138 MLX5_REG_HOST_ENDIANNESS = 0x7004,
139 MLX5_REG_MCIA = 0x9014,
140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MTRC_CAP = 0x9040,
142 MLX5_REG_MTRC_CONF = 0x9041,
143 MLX5_REG_MTRC_STDB = 0x9042,
144 MLX5_REG_MTRC_CTRL = 0x9043,
145 MLX5_REG_MPCNT = 0x9051,
146 MLX5_REG_MTPPS = 0x9053,
147 MLX5_REG_MTPPSE = 0x9054,
148 MLX5_REG_MPEGC = 0x9056,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 };
154
155 enum mlx5_qpts_trust_state {
156 MLX5_QPTS_TRUST_PCP = 1,
157 MLX5_QPTS_TRUST_DSCP = 2,
158 };
159
160 enum mlx5_dcbx_oper_mode {
161 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
162 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
163 };
164
165 enum mlx5_dct_atomic_mode {
166 MLX5_ATOMIC_MODE_DCT_CX = 2,
167 };
168
169 enum {
170 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
171 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 };
173
174 enum mlx5_page_fault_resume_flags {
175 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
176 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
177 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
178 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
179 };
180
181 enum dbg_rsc_type {
182 MLX5_DBG_RSC_QP,
183 MLX5_DBG_RSC_EQ,
184 MLX5_DBG_RSC_CQ,
185 };
186
187 enum port_state_policy {
188 MLX5_POLICY_DOWN = 0,
189 MLX5_POLICY_UP = 1,
190 MLX5_POLICY_FOLLOW = 2,
191 MLX5_POLICY_INVALID = 0xffffffff
192 };
193
194 struct mlx5_field_desc {
195 struct dentry *dent;
196 int i;
197 };
198
199 struct mlx5_rsc_debug {
200 struct mlx5_core_dev *dev;
201 void *object;
202 enum dbg_rsc_type type;
203 struct dentry *root;
204 struct mlx5_field_desc fields[0];
205 };
206
207 enum mlx5_dev_event {
208 MLX5_DEV_EVENT_SYS_ERROR,
209 MLX5_DEV_EVENT_PORT_UP,
210 MLX5_DEV_EVENT_PORT_DOWN,
211 MLX5_DEV_EVENT_PORT_INITIALIZED,
212 MLX5_DEV_EVENT_LID_CHANGE,
213 MLX5_DEV_EVENT_PKEY_CHANGE,
214 MLX5_DEV_EVENT_GUID_CHANGE,
215 MLX5_DEV_EVENT_CLIENT_REREG,
216 MLX5_DEV_EVENT_PPS,
217 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
218 };
219
220 enum mlx5_port_status {
221 MLX5_PORT_UP = 1,
222 MLX5_PORT_DOWN = 2,
223 };
224
225 enum mlx5_eq_type {
226 MLX5_EQ_TYPE_COMP,
227 MLX5_EQ_TYPE_ASYNC,
228 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
229 MLX5_EQ_TYPE_PF,
230 #endif
231 };
232
233 struct mlx5_bfreg_info {
234 u32 *sys_pages;
235 int num_low_latency_bfregs;
236 unsigned int *count;
237
238 /*
239 * protect bfreg allocation data structs
240 */
241 struct mutex lock;
242 u32 ver;
243 bool lib_uar_4k;
244 u32 num_sys_pages;
245 u32 num_static_sys_pages;
246 u32 total_num_bfregs;
247 u32 num_dyn_bfregs;
248 };
249
250 struct mlx5_cmd_first {
251 __be32 data[4];
252 };
253
254 struct mlx5_cmd_msg {
255 struct list_head list;
256 struct cmd_msg_cache *parent;
257 u32 len;
258 struct mlx5_cmd_first first;
259 struct mlx5_cmd_mailbox *next;
260 };
261
262 struct mlx5_cmd_debug {
263 struct dentry *dbg_root;
264 struct dentry *dbg_in;
265 struct dentry *dbg_out;
266 struct dentry *dbg_outlen;
267 struct dentry *dbg_status;
268 struct dentry *dbg_run;
269 void *in_msg;
270 void *out_msg;
271 u8 status;
272 u16 inlen;
273 u16 outlen;
274 };
275
276 struct cmd_msg_cache {
277 /* protect block chain allocations
278 */
279 spinlock_t lock;
280 struct list_head head;
281 unsigned int max_inbox_size;
282 unsigned int num_ent;
283 };
284
285 enum {
286 MLX5_NUM_COMMAND_CACHES = 5,
287 };
288
289 struct mlx5_cmd_stats {
290 u64 sum;
291 u64 n;
292 struct dentry *root;
293 struct dentry *avg;
294 struct dentry *count;
295 /* protect command average calculations */
296 spinlock_t lock;
297 };
298
299 struct mlx5_cmd {
300 void *cmd_alloc_buf;
301 dma_addr_t alloc_dma;
302 int alloc_size;
303 void *cmd_buf;
304 dma_addr_t dma;
305 u16 cmdif_rev;
306 u8 log_sz;
307 u8 log_stride;
308 int max_reg_cmds;
309 int events;
310 u32 __iomem *vector;
311
312 /* protect command queue allocations
313 */
314 spinlock_t alloc_lock;
315
316 /* protect token allocations
317 */
318 spinlock_t token_lock;
319 u8 token;
320 unsigned long bitmask;
321 char wq_name[MLX5_CMD_WQ_MAX_NAME];
322 struct workqueue_struct *wq;
323 struct semaphore sem;
324 struct semaphore pages_sem;
325 int mode;
326 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
327 struct dma_pool *pool;
328 struct mlx5_cmd_debug dbg;
329 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
330 int checksum_disabled;
331 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
332 };
333
334 struct mlx5_port_caps {
335 int gid_table_len;
336 int pkey_table_len;
337 u8 ext_port_cap;
338 bool has_smi;
339 };
340
341 struct mlx5_cmd_mailbox {
342 void *buf;
343 dma_addr_t dma;
344 struct mlx5_cmd_mailbox *next;
345 };
346
347 struct mlx5_buf_list {
348 void *buf;
349 dma_addr_t map;
350 };
351
352 struct mlx5_frag_buf {
353 struct mlx5_buf_list *frags;
354 int npages;
355 int size;
356 u8 page_shift;
357 };
358
359 struct mlx5_frag_buf_ctrl {
360 struct mlx5_frag_buf frag_buf;
361 u32 sz_m1;
362 u16 frag_sz_m1;
363 u16 strides_offset;
364 u8 log_sz;
365 u8 log_stride;
366 u8 log_frag_strides;
367 };
368
369 struct mlx5_eq_tasklet {
370 struct list_head list;
371 struct list_head process_list;
372 struct tasklet_struct task;
373 /* lock on completion tasklet list */
374 spinlock_t lock;
375 };
376
377 struct mlx5_eq_pagefault {
378 struct work_struct work;
379 /* Pagefaults lock */
380 spinlock_t lock;
381 struct workqueue_struct *wq;
382 mempool_t *pool;
383 };
384
385 struct mlx5_cq_table {
386 /* protect radix tree */
387 spinlock_t lock;
388 struct radix_tree_root tree;
389 };
390
391 struct mlx5_eq {
392 struct mlx5_core_dev *dev;
393 struct mlx5_cq_table cq_table;
394 __be32 __iomem *doorbell;
395 u32 cons_index;
396 struct mlx5_frag_buf buf;
397 int size;
398 unsigned int irqn;
399 u8 eqn;
400 int nent;
401 u64 mask;
402 struct list_head list;
403 int index;
404 struct mlx5_rsc_debug *dbg;
405 enum mlx5_eq_type type;
406 union {
407 struct mlx5_eq_tasklet tasklet_ctx;
408 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
409 struct mlx5_eq_pagefault pf_ctx;
410 #endif
411 };
412 };
413
414 struct mlx5_core_psv {
415 u32 psv_idx;
416 struct psv_layout {
417 u32 pd;
418 u16 syndrome;
419 u16 reserved;
420 u16 bg;
421 u16 app_tag;
422 u32 ref_tag;
423 } psv;
424 };
425
426 struct mlx5_core_sig_ctx {
427 struct mlx5_core_psv psv_memory;
428 struct mlx5_core_psv psv_wire;
429 struct ib_sig_err err_item;
430 bool sig_status_checked;
431 bool sig_err_exists;
432 u32 sigerr_count;
433 };
434
435 enum {
436 MLX5_MKEY_MR = 1,
437 MLX5_MKEY_MW,
438 };
439
440 struct mlx5_core_mkey {
441 u64 iova;
442 u64 size;
443 u32 key;
444 u32 pd;
445 u32 type;
446 };
447
448 #define MLX5_24BIT_MASK ((1 << 24) - 1)
449
450 enum mlx5_res_type {
451 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
452 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
453 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
454 MLX5_RES_SRQ = 3,
455 MLX5_RES_XSRQ = 4,
456 MLX5_RES_XRQ = 5,
457 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
458 };
459
460 struct mlx5_core_rsc_common {
461 enum mlx5_res_type res;
462 atomic_t refcount;
463 struct completion free;
464 };
465
466 struct mlx5_core_srq {
467 struct mlx5_core_rsc_common common; /* must be first */
468 u32 srqn;
469 int max;
470 size_t max_gs;
471 size_t max_avail_gather;
472 int wqe_shift;
473 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
474
475 atomic_t refcount;
476 struct completion free;
477 };
478
479 struct mlx5_eq_table {
480 void __iomem *update_ci;
481 void __iomem *update_arm_ci;
482 struct list_head comp_eqs_list;
483 struct mlx5_eq pages_eq;
484 struct mlx5_eq async_eq;
485 struct mlx5_eq cmd_eq;
486 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
487 struct mlx5_eq pfault_eq;
488 #endif
489 int num_comp_vectors;
490 /* protect EQs list
491 */
492 spinlock_t lock;
493 };
494
495 struct mlx5_uars_page {
496 void __iomem *map;
497 bool wc;
498 u32 index;
499 struct list_head list;
500 unsigned int bfregs;
501 unsigned long *reg_bitmap; /* for non fast path bf regs */
502 unsigned long *fp_bitmap;
503 unsigned int reg_avail;
504 unsigned int fp_avail;
505 struct kref ref_count;
506 struct mlx5_core_dev *mdev;
507 };
508
509 struct mlx5_bfreg_head {
510 /* protect blue flame registers allocations */
511 struct mutex lock;
512 struct list_head list;
513 };
514
515 struct mlx5_bfreg_data {
516 struct mlx5_bfreg_head reg_head;
517 struct mlx5_bfreg_head wc_head;
518 };
519
520 struct mlx5_sq_bfreg {
521 void __iomem *map;
522 struct mlx5_uars_page *up;
523 bool wc;
524 u32 index;
525 unsigned int offset;
526 };
527
528 struct mlx5_core_health {
529 struct health_buffer __iomem *health;
530 __be32 __iomem *health_counter;
531 struct timer_list timer;
532 u32 prev;
533 int miss_counter;
534 bool sick;
535 /* wq spinlock to synchronize draining */
536 spinlock_t wq_lock;
537 struct workqueue_struct *wq;
538 unsigned long flags;
539 struct work_struct work;
540 struct delayed_work recover_work;
541 };
542
543 struct mlx5_qp_table {
544 /* protect radix tree
545 */
546 spinlock_t lock;
547 struct radix_tree_root tree;
548 };
549
550 struct mlx5_srq_table {
551 /* protect radix tree
552 */
553 spinlock_t lock;
554 struct radix_tree_root tree;
555 };
556
557 struct mlx5_mkey_table {
558 /* protect radix tree
559 */
560 rwlock_t lock;
561 struct radix_tree_root tree;
562 };
563
564 struct mlx5_vf_context {
565 int enabled;
566 u64 port_guid;
567 u64 node_guid;
568 enum port_state_policy policy;
569 };
570
571 struct mlx5_core_sriov {
572 struct mlx5_vf_context *vfs_ctx;
573 int num_vfs;
574 int enabled_vfs;
575 };
576
577 struct mlx5_irq_info {
578 cpumask_var_t mask;
579 char name[MLX5_MAX_IRQ_NAME];
580 };
581
582 struct mlx5_fc_stats {
583 struct rb_root counters;
584 struct list_head addlist;
585 /* protect addlist add/splice operations */
586 spinlock_t addlist_lock;
587
588 struct workqueue_struct *wq;
589 struct delayed_work work;
590 unsigned long next_query;
591 unsigned long sampling_interval; /* jiffies */
592 };
593
594 struct mlx5_mpfs;
595 struct mlx5_eswitch;
596 struct mlx5_lag;
597 struct mlx5_pagefault;
598
599 struct mlx5_rate_limit {
600 u32 rate;
601 u32 max_burst_sz;
602 u16 typical_pkt_sz;
603 };
604
605 struct mlx5_rl_entry {
606 struct mlx5_rate_limit rl;
607 u16 index;
608 u16 refcount;
609 };
610
611 struct mlx5_rl_table {
612 /* protect rate limit table */
613 struct mutex rl_lock;
614 u16 max_size;
615 u32 max_rate;
616 u32 min_rate;
617 struct mlx5_rl_entry *rl_entry;
618 };
619
620 enum port_module_event_status_type {
621 MLX5_MODULE_STATUS_PLUGGED = 0x1,
622 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
623 MLX5_MODULE_STATUS_ERROR = 0x3,
624 MLX5_MODULE_STATUS_NUM = 0x3,
625 };
626
627 enum port_module_event_error_type {
628 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
629 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
630 MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
631 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
632 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
633 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
634 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
635 MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
636 MLX5_MODULE_EVENT_ERROR_UNKNOWN,
637 MLX5_MODULE_EVENT_ERROR_NUM,
638 };
639
640 struct mlx5_port_module_event_stats {
641 u64 status_counters[MLX5_MODULE_STATUS_NUM];
642 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
643 };
644
645 struct mlx5_priv {
646 char name[MLX5_MAX_NAME_LEN];
647 struct mlx5_eq_table eq_table;
648 struct mlx5_irq_info *irq_info;
649
650 /* pages stuff */
651 struct workqueue_struct *pg_wq;
652 struct rb_root page_root;
653 int fw_pages;
654 atomic_t reg_pages;
655 struct list_head free_list;
656 int vfs_pages;
657
658 struct mlx5_core_health health;
659
660 struct mlx5_srq_table srq_table;
661
662 /* start: qp staff */
663 struct mlx5_qp_table qp_table;
664 struct dentry *qp_debugfs;
665 struct dentry *eq_debugfs;
666 struct dentry *cq_debugfs;
667 struct dentry *cmdif_debugfs;
668 /* end: qp staff */
669
670 /* start: mkey staff */
671 struct mlx5_mkey_table mkey_table;
672 /* end: mkey staff */
673
674 /* start: alloc staff */
675 /* protect buffer alocation according to numa node */
676 struct mutex alloc_mutex;
677 int numa_node;
678
679 struct mutex pgdir_mutex;
680 struct list_head pgdir_list;
681 /* end: alloc staff */
682 struct dentry *dbg_root;
683
684 /* protect mkey key part */
685 spinlock_t mkey_lock;
686 u8 mkey_key;
687
688 struct list_head dev_list;
689 struct list_head ctx_list;
690 spinlock_t ctx_lock;
691
692 struct list_head waiting_events_list;
693 bool is_accum_events;
694
695 struct mlx5_flow_steering *steering;
696 struct mlx5_mpfs *mpfs;
697 struct mlx5_eswitch *eswitch;
698 struct mlx5_core_sriov sriov;
699 struct mlx5_lag *lag;
700 unsigned long pci_dev_data;
701 struct mlx5_fc_stats fc_stats;
702 struct mlx5_rl_table rl_table;
703
704 struct mlx5_port_module_event_stats pme_stats;
705
706 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
707 void (*pfault)(struct mlx5_core_dev *dev,
708 void *context,
709 struct mlx5_pagefault *pfault);
710 void *pfault_ctx;
711 struct srcu_struct pfault_srcu;
712 #endif
713 struct mlx5_bfreg_data bfregs;
714 struct mlx5_uars_page *uar;
715 };
716
717 enum mlx5_device_state {
718 MLX5_DEVICE_STATE_UP,
719 MLX5_DEVICE_STATE_INTERNAL_ERROR,
720 };
721
722 enum mlx5_interface_state {
723 MLX5_INTERFACE_STATE_UP = BIT(0),
724 };
725
726 enum mlx5_pci_status {
727 MLX5_PCI_STATUS_DISABLED,
728 MLX5_PCI_STATUS_ENABLED,
729 };
730
731 enum mlx5_pagefault_type_flags {
732 MLX5_PFAULT_REQUESTOR = 1 << 0,
733 MLX5_PFAULT_WRITE = 1 << 1,
734 MLX5_PFAULT_RDMA = 1 << 2,
735 };
736
737 /* Contains the details of a pagefault. */
738 struct mlx5_pagefault {
739 u32 bytes_committed;
740 u32 token;
741 u8 event_subtype;
742 u8 type;
743 union {
744 /* Initiator or send message responder pagefault details. */
745 struct {
746 /* Received packet size, only valid for responders. */
747 u32 packet_size;
748 /*
749 * Number of resource holding WQE, depends on type.
750 */
751 u32 wq_num;
752 /*
753 * WQE index. Refers to either the send queue or
754 * receive queue, according to event_subtype.
755 */
756 u16 wqe_index;
757 } wqe;
758 /* RDMA responder pagefault details */
759 struct {
760 u32 r_key;
761 /*
762 * Received packet size, minimal size page fault
763 * resolution required for forward progress.
764 */
765 u32 packet_size;
766 u32 rdma_op_len;
767 u64 rdma_va;
768 } rdma;
769 };
770
771 struct mlx5_eq *eq;
772 struct work_struct work;
773 };
774
775 struct mlx5_td {
776 /* protects tirs list changes while tirs refresh */
777 struct mutex list_lock;
778 struct list_head tirs_list;
779 u32 tdn;
780 };
781
782 struct mlx5e_resources {
783 u32 pdn;
784 struct mlx5_td td;
785 struct mlx5_core_mkey mkey;
786 struct mlx5_sq_bfreg bfreg;
787 };
788
789 #define MLX5_MAX_RESERVED_GIDS 8
790
791 struct mlx5_rsvd_gids {
792 unsigned int start;
793 unsigned int count;
794 struct ida ida;
795 };
796
797 #define MAX_PIN_NUM 8
798 struct mlx5_pps {
799 u8 pin_caps[MAX_PIN_NUM];
800 struct work_struct out_work;
801 u64 start[MAX_PIN_NUM];
802 u8 enabled;
803 };
804
805 struct mlx5_clock {
806 rwlock_t lock;
807 struct cyclecounter cycles;
808 struct timecounter tc;
809 struct hwtstamp_config hwtstamp_config;
810 u32 nominal_c_mult;
811 unsigned long overflow_period;
812 struct delayed_work overflow_work;
813 struct mlx5_core_dev *mdev;
814 struct ptp_clock *ptp;
815 struct ptp_clock_info ptp_info;
816 struct mlx5_pps pps_info;
817 };
818
819 struct mlx5_fw_tracer;
820 struct mlx5_vxlan;
821
822 struct mlx5_core_dev {
823 struct pci_dev *pdev;
824 /* sync pci state */
825 struct mutex pci_status_mutex;
826 enum mlx5_pci_status pci_status;
827 u8 rev_id;
828 char board_id[MLX5_BOARD_ID_LEN];
829 struct mlx5_cmd cmd;
830 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
831 struct {
832 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
833 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
834 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
835 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
836 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
837 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
838 } caps;
839 phys_addr_t iseg_base;
840 struct mlx5_init_seg __iomem *iseg;
841 enum mlx5_device_state state;
842 /* sync interface state */
843 struct mutex intf_state_mutex;
844 unsigned long intf_state;
845 void (*event) (struct mlx5_core_dev *dev,
846 enum mlx5_dev_event event,
847 unsigned long param);
848 struct mlx5_priv priv;
849 struct mlx5_profile *profile;
850 atomic_t num_qps;
851 u32 issi;
852 struct mlx5e_resources mlx5e_res;
853 struct mlx5_vxlan *vxlan;
854 struct {
855 struct mlx5_rsvd_gids reserved_gids;
856 u32 roce_en;
857 } roce;
858 #ifdef CONFIG_MLX5_FPGA
859 struct mlx5_fpga_device *fpga;
860 #endif
861 #ifdef CONFIG_RFS_ACCEL
862 struct cpu_rmap *rmap;
863 #endif
864 struct mlx5_clock clock;
865 struct mlx5_ib_clock_info *clock_info;
866 struct page *clock_info_page;
867 struct mlx5_fw_tracer *tracer;
868 };
869
870 struct mlx5_db {
871 __be32 *db;
872 union {
873 struct mlx5_db_pgdir *pgdir;
874 struct mlx5_ib_user_db_page *user_page;
875 } u;
876 dma_addr_t dma;
877 int index;
878 };
879
880 enum {
881 MLX5_COMP_EQ_SIZE = 1024,
882 };
883
884 enum {
885 MLX5_PTYS_IB = 1 << 0,
886 MLX5_PTYS_EN = 1 << 2,
887 };
888
889 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
890
891 enum {
892 MLX5_CMD_ENT_STATE_PENDING_COMP,
893 };
894
895 struct mlx5_cmd_work_ent {
896 unsigned long state;
897 struct mlx5_cmd_msg *in;
898 struct mlx5_cmd_msg *out;
899 void *uout;
900 int uout_size;
901 mlx5_cmd_cbk_t callback;
902 struct delayed_work cb_timeout_work;
903 void *context;
904 int idx;
905 struct completion handling;
906 struct completion done;
907 struct mlx5_cmd *cmd;
908 struct work_struct work;
909 struct mlx5_cmd_layout *lay;
910 int ret;
911 int page_queue;
912 u8 status;
913 u8 token;
914 u64 ts1;
915 u64 ts2;
916 u16 op;
917 bool polling;
918 };
919
920 struct mlx5_pas {
921 u64 pa;
922 u8 log_sz;
923 };
924
925 enum phy_port_state {
926 MLX5_AAA_111
927 };
928
929 struct mlx5_hca_vport_context {
930 u32 field_select;
931 bool sm_virt_aware;
932 bool has_smi;
933 bool has_raw;
934 enum port_state_policy policy;
935 enum phy_port_state phys_state;
936 enum ib_port_state vport_state;
937 u8 port_physical_state;
938 u64 sys_image_guid;
939 u64 port_guid;
940 u64 node_guid;
941 u32 cap_mask1;
942 u32 cap_mask1_perm;
943 u32 cap_mask2;
944 u32 cap_mask2_perm;
945 u16 lid;
946 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
947 u8 lmc;
948 u8 subnet_timeout;
949 u16 sm_lid;
950 u8 sm_sl;
951 u16 qkey_violation_counter;
952 u16 pkey_violation_counter;
953 bool grh_required;
954 };
955
mlx5_buf_offset(struct mlx5_frag_buf * buf,int offset)956 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
957 {
958 return buf->frags->buf + offset;
959 }
960
961 #define STRUCT_FIELD(header, field) \
962 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
963 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
964
pci2mlx5_core_dev(struct pci_dev * pdev)965 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
966 {
967 return pci_get_drvdata(pdev);
968 }
969
970 extern struct dentry *mlx5_debugfs_root;
971
fw_rev_maj(struct mlx5_core_dev * dev)972 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
973 {
974 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
975 }
976
fw_rev_min(struct mlx5_core_dev * dev)977 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
978 {
979 return ioread32be(&dev->iseg->fw_rev) >> 16;
980 }
981
fw_rev_sub(struct mlx5_core_dev * dev)982 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
983 {
984 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
985 }
986
cmdif_rev(struct mlx5_core_dev * dev)987 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
988 {
989 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
990 }
991
mlx5_base_mkey(const u32 key)992 static inline u32 mlx5_base_mkey(const u32 key)
993 {
994 return key & 0xffffff00u;
995 }
996
mlx5_fill_fbc_offset(u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)997 static inline void mlx5_fill_fbc_offset(u8 log_stride, u8 log_sz,
998 u16 strides_offset,
999 struct mlx5_frag_buf_ctrl *fbc)
1000 {
1001 fbc->log_stride = log_stride;
1002 fbc->log_sz = log_sz;
1003 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
1004 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
1005 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
1006 fbc->strides_offset = strides_offset;
1007 }
1008
mlx5_fill_fbc(u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)1009 static inline void mlx5_fill_fbc(u8 log_stride, u8 log_sz,
1010 struct mlx5_frag_buf_ctrl *fbc)
1011 {
1012 mlx5_fill_fbc_offset(log_stride, log_sz, 0, fbc);
1013 }
1014
mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl * fbc,void * cqc)1015 static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc,
1016 void *cqc)
1017 {
1018 mlx5_fill_fbc(6 + MLX5_GET(cqc, cqc, cqe_sz),
1019 MLX5_GET(cqc, cqc, log_cq_size),
1020 fbc);
1021 }
1022
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)1023 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
1024 u32 ix)
1025 {
1026 unsigned int frag;
1027
1028 ix += fbc->strides_offset;
1029 frag = ix >> fbc->log_frag_strides;
1030
1031 return fbc->frag_buf.frags[frag].buf +
1032 ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
1033 }
1034
1035 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)1036 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
1037 {
1038 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
1039
1040 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
1041 }
1042
1043 int mlx5_cmd_init(struct mlx5_core_dev *dev);
1044 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
1045 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
1046 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
1047
1048 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1049 int out_size);
1050 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1051 void *out, int out_size, mlx5_cmd_cbk_t callback,
1052 void *context);
1053 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1054 void *out, int out_size);
1055 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
1056
1057 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1058 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
1059 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
1060 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1061 int mlx5_health_init(struct mlx5_core_dev *dev);
1062 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1063 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1064 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1065 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1066 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
1067 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1068 struct mlx5_frag_buf *buf, int node);
1069 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1070 int size, struct mlx5_frag_buf *buf);
1071 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1072 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1073 struct mlx5_frag_buf *buf, int node);
1074 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1075 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1076 gfp_t flags, int npages);
1077 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1078 struct mlx5_cmd_mailbox *head);
1079 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1080 struct mlx5_srq_attr *in);
1081 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1082 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1083 struct mlx5_srq_attr *out);
1084 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1085 u16 lwm, int is_srq);
1086 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
1087 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
1088 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1089 struct mlx5_core_mkey *mkey,
1090 u32 *in, int inlen,
1091 u32 *out, int outlen,
1092 mlx5_cmd_cbk_t callback, void *context);
1093 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1094 struct mlx5_core_mkey *mkey,
1095 u32 *in, int inlen);
1096 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1097 struct mlx5_core_mkey *mkey);
1098 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1099 u32 *out, int outlen);
1100 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1101 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1102 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1103 u16 opmod, u8 port);
1104 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1105 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1106 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1107 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1108 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1109 s32 npages);
1110 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1111 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1112 void mlx5_register_debugfs(void);
1113 void mlx5_unregister_debugfs(void);
1114
1115 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1116 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1117 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1118 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1119 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1120 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1121 unsigned int *irqn);
1122 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1123 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1124
1125 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1126 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1127 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1128 int size_in, void *data_out, int size_out,
1129 u16 reg_num, int arg, int write);
1130
1131 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1132 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1133 int node);
1134 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1135
1136 const char *mlx5_command_str(int command);
1137 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1138 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1139 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1140 int npsvs, u32 *sig_index);
1141 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1142 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1143 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1144 struct mlx5_odp_caps *odp_caps);
1145 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1146 u8 port_num, void *out, size_t sz);
1147 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1148 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1149 u32 wq_num, u8 type, int error);
1150 #endif
1151
1152 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1153 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1154 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1155 struct mlx5_rate_limit *rl);
1156 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1157 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1158 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1159 struct mlx5_rate_limit *rl_1);
1160 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1161 bool map_wc, bool fast_path);
1162 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1163
1164 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1165 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1166 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1167 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1168
fw_initializing(struct mlx5_core_dev * dev)1169 static inline int fw_initializing(struct mlx5_core_dev *dev)
1170 {
1171 return ioread32be(&dev->iseg->initializing) >> 31;
1172 }
1173
mlx5_mkey_to_idx(u32 mkey)1174 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1175 {
1176 return mkey >> 8;
1177 }
1178
mlx5_idx_to_mkey(u32 mkey_idx)1179 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1180 {
1181 return mkey_idx << 8;
1182 }
1183
mlx5_mkey_variant(u32 mkey)1184 static inline u8 mlx5_mkey_variant(u32 mkey)
1185 {
1186 return mkey & 0xff;
1187 }
1188
1189 enum {
1190 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1191 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1192 };
1193
1194 enum {
1195 MR_CACHE_LAST_STD_ENTRY = 20,
1196 MLX5_IMR_MTT_CACHE_ENTRY,
1197 MLX5_IMR_KSM_CACHE_ENTRY,
1198 MAX_MR_CACHE_ENTRIES
1199 };
1200
1201 enum {
1202 MLX5_INTERFACE_PROTOCOL_IB = 0,
1203 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1204 };
1205
1206 struct mlx5_interface {
1207 void * (*add)(struct mlx5_core_dev *dev);
1208 void (*remove)(struct mlx5_core_dev *dev, void *context);
1209 int (*attach)(struct mlx5_core_dev *dev, void *context);
1210 void (*detach)(struct mlx5_core_dev *dev, void *context);
1211 void (*event)(struct mlx5_core_dev *dev, void *context,
1212 enum mlx5_dev_event event, unsigned long param);
1213 void (*pfault)(struct mlx5_core_dev *dev,
1214 void *context,
1215 struct mlx5_pagefault *pfault);
1216 void * (*get_dev)(void *context);
1217 int protocol;
1218 struct list_head list;
1219 };
1220
1221 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1222 int mlx5_register_interface(struct mlx5_interface *intf);
1223 void mlx5_unregister_interface(struct mlx5_interface *intf);
1224 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1225
1226 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1227 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1228 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1229 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1230 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1231 u64 *values,
1232 int num_counters,
1233 size_t *offsets);
1234 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1235 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1236
1237 #ifndef CONFIG_MLX5_CORE_IPOIB
1238 static inline
mlx5_rdma_netdev_alloc(struct mlx5_core_dev * mdev,struct ib_device * ibdev,const char * name,void (* setup)(struct net_device *))1239 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1240 struct ib_device *ibdev,
1241 const char *name,
1242 void (*setup)(struct net_device *))
1243 {
1244 return ERR_PTR(-EOPNOTSUPP);
1245 }
1246 #else
1247 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1248 struct ib_device *ibdev,
1249 const char *name,
1250 void (*setup)(struct net_device *));
1251 #endif /* CONFIG_MLX5_CORE_IPOIB */
1252
1253 struct mlx5_profile {
1254 u64 mask;
1255 u8 log_max_qp;
1256 struct {
1257 int size;
1258 int limit;
1259 } mr_cache[MAX_MR_CACHE_ENTRIES];
1260 };
1261
1262 enum {
1263 MLX5_PCI_DEV_IS_VF = 1 << 0,
1264 };
1265
mlx5_core_is_pf(struct mlx5_core_dev * dev)1266 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1267 {
1268 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1269 }
1270
1271 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev))
1272 #define MLX5_VPORT_MANAGER(mdev) \
1273 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
1274 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
1275 mlx5_core_is_pf(mdev))
1276
mlx5_get_gid_table_len(u16 param)1277 static inline int mlx5_get_gid_table_len(u16 param)
1278 {
1279 if (param > 4) {
1280 pr_warn("gid table length is zero\n");
1281 return 0;
1282 }
1283
1284 return 8 * (1 << param);
1285 }
1286
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1287 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1288 {
1289 return !!(dev->priv.rl_table.max_size);
1290 }
1291
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1292 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1293 {
1294 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1295 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1296 }
1297
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1298 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1299 {
1300 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1301 }
1302
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1303 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1304 {
1305 return mlx5_core_is_mp_slave(dev) ||
1306 mlx5_core_is_mp_master(dev);
1307 }
1308
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1309 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1310 {
1311 if (!mlx5_core_mp_enabled(dev))
1312 return 1;
1313
1314 return MLX5_CAP_GEN(dev, native_port_num);
1315 }
1316
1317 enum {
1318 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1319 };
1320
1321 static inline const struct cpumask *
mlx5_get_vector_affinity_hint(struct mlx5_core_dev * dev,int vector)1322 mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector)
1323 {
1324 return dev->priv.irq_info[vector + MLX5_EQ_VEC_COMP_BASE].mask;
1325 }
1326
1327 #endif /* MLX5_DRIVER_H */
1328