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Searched refs:reg_val (Results 1 – 25 of 51) sorted by relevance

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/linux-4.19.296/drivers/media/dvb-frontends/
Daf9033_priv.h28 struct reg_val { struct
96 static const struct reg_val ofsm_init[] = {
211 static const struct reg_val tuner_init_tua9001[] = {
255 static const struct reg_val tuner_init_fc0011[] = {
318 static const struct reg_val tuner_init_fc0012[] = {
363 static const struct reg_val tuner_init_mxl5007t[] = {
400 static const struct reg_val tuner_init_tda18218[] = {
436 static const struct reg_val tuner_init_fc2580[] = {
476 static const struct reg_val ofsm_init_it9135_v1[] = {
591 static const struct reg_val tuner_init_it9135_38[] = {
[all …]
Dtc90522.c40 struct reg_val { struct
46 reg_write(struct tc90522_state *state, const struct reg_val *regs, int num) in reg_write() argument
100 struct reg_val set_tsid[] = { in tc90522s_set_tsid()
112 struct reg_val rv; in tc90522t_set_layers()
474 static const struct reg_val reset_sat = { 0x03, 0x01 };
475 static const struct reg_val reset_ter = { 0x01, 0x40 };
530 struct reg_val agc_sat[] = { in tc90522_set_if_agc()
536 struct reg_val agc_ter[] = { in tc90522_set_if_agc()
542 struct reg_val *rv; in tc90522_set_if_agc()
562 static const struct reg_val sleep_sat = { 0x17, 0x01 };
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/linux-4.19.296/drivers/clk/bcm/
Dclk-kona.c41 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
43 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
47 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) in bitfield_replace() argument
51 return (reg_val & ~mask) | (val << shift); in bitfield_replace()
136 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
138 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
336 u32 reg_val; in policy_init() local
338 reg_val = __ccu_read(ccu, offset); in policy_init()
339 reg_val |= mask; in policy_init()
340 __ccu_write(ccu, offset, reg_val); in policy_init()
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/linux-4.19.296/drivers/gpio/
Dgpio-pca953x.c293 u8 reg_val; in pca953x_gpio_direction_input() local
297 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); in pca953x_gpio_direction_input()
299 ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); in pca953x_gpio_direction_input()
303 chip->reg_direction[off / BANK_SZ] = reg_val; in pca953x_gpio_direction_input()
313 u8 reg_val; in pca953x_gpio_direction_output() local
319 reg_val = chip->reg_output[off / BANK_SZ] in pca953x_gpio_direction_output()
322 reg_val = chip->reg_output[off / BANK_SZ] in pca953x_gpio_direction_output()
325 ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); in pca953x_gpio_direction_output()
329 chip->reg_output[off / BANK_SZ] = reg_val; in pca953x_gpio_direction_output()
332 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); in pca953x_gpio_direction_output()
[all …]
Dgpio-sch.c66 u8 reg_val; in sch_gpio_reg_get() local
71 reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); in sch_gpio_reg_get()
73 return reg_val; in sch_gpio_reg_get()
80 u8 reg_val; in sch_gpio_reg_set() local
85 reg_val = inb(sch->iobase + offset); in sch_gpio_reg_set()
88 outb(reg_val | BIT(bit), sch->iobase + offset); in sch_gpio_reg_set()
90 outb((reg_val & ~BIT(bit)), sch->iobase + offset); in sch_gpio_reg_set()
Dgpio-pch.c111 u32 reg_val; in pch_gpio_set() local
116 reg_val = ioread32(&chip->reg->po); in pch_gpio_set()
118 reg_val |= (1 << nr); in pch_gpio_set()
120 reg_val &= ~(1 << nr); in pch_gpio_set()
122 iowrite32(reg_val, &chip->reg->po); in pch_gpio_set()
138 u32 reg_val; in pch_gpio_direction_output() local
143 reg_val = ioread32(&chip->reg->po); in pch_gpio_direction_output()
145 reg_val |= (1 << nr); in pch_gpio_direction_output()
147 reg_val &= ~(1 << nr); in pch_gpio_direction_output()
148 iowrite32(reg_val, &chip->reg->po); in pch_gpio_direction_output()
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Dgpio-ml-ioh.c106 u32 reg_val; in ioh_gpio_set() local
111 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
113 reg_val |= (1 << nr); in ioh_gpio_set()
115 reg_val &= ~(1 << nr); in ioh_gpio_set()
117 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
133 u32 reg_val; in ioh_gpio_direction_output() local
142 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
144 reg_val |= (1 << nr); in ioh_gpio_direction_output()
146 reg_val &= ~(1 << nr); in ioh_gpio_direction_output()
147 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
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Dgpio-adp5520.c27 uint8_t reg_val; in adp5520_gpio_get_value() local
37 adp5520_read(dev->master, ADP5520_GPIO_OUT, &reg_val); in adp5520_gpio_get_value()
39 adp5520_read(dev->master, ADP5520_GPIO_IN, &reg_val); in adp5520_gpio_get_value()
41 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value()
Dgpio-madera.c77 unsigned int reg_val = value ? MADERA_GP1_LVL : 0; in madera_gpio_direction_out() local
88 MADERA_GP1_LVL_MASK, reg_val); in madera_gpio_direction_out()
97 unsigned int reg_val = value ? MADERA_GP1_LVL : 0; in madera_gpio_set() local
102 MADERA_GP1_LVL_MASK, reg_val); in madera_gpio_set()
/linux-4.19.296/drivers/pci/controller/dwc/
Dpcie-hisi.c149 u32 reg_val; in hisi_pcie_cfg_read() local
150 void *walker = &reg_val; in hisi_pcie_cfg_read()
155 reg_val = dw_pcie_readl_dbi(pci, reg); in hisi_pcie_cfg_read()
162 *val = reg_val; in hisi_pcie_cfg_read()
173 u32 reg_val; in hisi_pcie_cfg_write() local
175 void *walker = &reg_val; in hisi_pcie_cfg_write()
183 reg_val = dw_pcie_readl_dbi(pci, reg); in hisi_pcie_cfg_write()
185 dw_pcie_writel_dbi(pci, reg, reg_val); in hisi_pcie_cfg_write()
187 reg_val = dw_pcie_readl_dbi(pci, reg); in hisi_pcie_cfg_write()
189 dw_pcie_writel_dbi(pci, reg, reg_val); in hisi_pcie_cfg_write()
Dpcie-kirin.c186 u32 reg_val; in kirin_pcie_phy_init() local
188 reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); in kirin_pcie_phy_init()
189 reg_val &= ~PHY_REF_PAD_BIT; in kirin_pcie_phy_init()
190 kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); in kirin_pcie_phy_init()
192 reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0); in kirin_pcie_phy_init()
193 reg_val &= ~PHY_PWR_DOWN_BIT; in kirin_pcie_phy_init()
194 kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0); in kirin_pcie_phy_init()
197 reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); in kirin_pcie_phy_init()
198 reg_val &= ~PHY_RST_ACK_BIT; in kirin_pcie_phy_init()
199 kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); in kirin_pcie_phy_init()
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/linux-4.19.296/drivers/nvmem/
Dsunxi_sid.c91 u32 reg_val; in sun8i_sid_register_readout() local
95 reg_val = (offset & SUN8I_SID_OFFSET_MASK) in sun8i_sid_register_readout()
97 reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ; in sun8i_sid_register_readout()
98 writel(reg_val, sid->base + SUN8I_SID_PRCTL); in sun8i_sid_register_readout()
100 ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val, in sun8i_sid_register_readout()
101 !(reg_val & SUN8I_SID_READ), 100, 250000); in sun8i_sid_register_readout()
/linux-4.19.296/drivers/ntb/hw/intel/
Dntb_hw_gen3.c95 u16 reg_val; in gen3_poll_link() local
103 GEN3_LINK_STATUS_OFFSET, &reg_val); in gen3_poll_link()
107 if (reg_val == ndev->lnk_sta) in gen3_poll_link()
110 ndev->lnk_sta = reg_val; in gen3_poll_link()
451 u64 base, limit, reg_val; in intel_ntb3_mw_set_trans() local
492 reg_val = ioread64(mmio + xlat_reg); in intel_ntb3_mw_set_trans()
493 if (reg_val != addr) { in intel_ntb3_mw_set_trans()
498 dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val); in intel_ntb3_mw_set_trans()
502 reg_val = ioread64(mmio + limit_reg); in intel_ntb3_mw_set_trans()
503 if (reg_val != limit) { in intel_ntb3_mw_set_trans()
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/linux-4.19.296/drivers/clk/
Dclk-axi-clkgen.c192 unsigned int reg_val; in axi_clkgen_mmcm_read() local
199 reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ; in axi_clkgen_mmcm_read()
200 reg_val |= (reg << 16); in axi_clkgen_mmcm_read()
202 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); in axi_clkgen_mmcm_read()
216 unsigned int reg_val = 0; in axi_clkgen_mmcm_write() local
224 axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val); in axi_clkgen_mmcm_write()
225 reg_val &= ~mask; in axi_clkgen_mmcm_write()
228 reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask); in axi_clkgen_mmcm_write()
230 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); in axi_clkgen_mmcm_write()
/linux-4.19.296/drivers/media/tuners/
Dmxl301rf.c137 struct reg_val { struct
142 static const struct reg_val set_idac[] = { argument
155 struct reg_val tune0[] = { in mxl301rf_set_params()
165 struct reg_val tune1[] = { in mxl301rf_set_params()
229 static const struct reg_val standby_data[] = {
/linux-4.19.296/drivers/memory/
Dmtk-smi.c212 u32 sec_con_val, reg_val; in mtk_smi_larb_config_port_gen1() local
226 reg_val = readl(common->smi_ao_base in mtk_smi_larb_config_port_gen1()
228 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); in mtk_smi_larb_config_port_gen1()
229 reg_val |= sec_con_val; in mtk_smi_larb_config_port_gen1()
230 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); in mtk_smi_larb_config_port_gen1()
231 writel(reg_val, in mtk_smi_larb_config_port_gen1()
/linux-4.19.296/drivers/regulator/
Dhi6421v530-regulator.c119 unsigned int reg_val; in hi6421v530_regulator_ldo_get_mode() local
122 regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val); in hi6421v530_regulator_ldo_get_mode()
124 if (reg_val & (info->mode_mask)) in hi6421v530_regulator_ldo_get_mode()
Dhi6421-regulator.c411 u32 reg_val; in hi6421_regulator_ldo_get_mode() local
413 regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val); in hi6421_regulator_ldo_get_mode()
414 if (reg_val & info->mode_mask) in hi6421_regulator_ldo_get_mode()
423 u32 reg_val; in hi6421_regulator_buck_get_mode() local
425 regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val); in hi6421_regulator_buck_get_mode()
426 if (reg_val & info->mode_mask) in hi6421_regulator_buck_get_mode()
Dpv88060-regulator.c270 int i, reg_val, err, ret = IRQ_NONE; in pv88060_irq_handler() local
272 err = regmap_read(chip->regmap, PV88060_REG_EVENT_A, &reg_val); in pv88060_irq_handler()
276 if (reg_val & PV88060_E_VDD_FLT) { in pv88060_irq_handler()
293 if (reg_val & PV88060_E_OVER_TEMP) { in pv88060_irq_handler()
Dpv88090-regulator.c268 int i, reg_val, err, ret = IRQ_NONE; in pv88090_irq_handler() local
270 err = regmap_read(chip->regmap, PV88090_REG_EVENT_A, &reg_val); in pv88090_irq_handler()
274 if (reg_val & PV88090_E_VDD_FLT) { in pv88090_irq_handler()
291 if (reg_val & PV88090_E_OVER_TEMP) { in pv88090_irq_handler()
/linux-4.19.296/include/linux/mfd/da9055/
Dcore.h83 unsigned char reg_val) in da9055_reg_update() argument
85 return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val); in da9055_reg_update()
/linux-4.19.296/drivers/iio/magnetometer/
Dbmc150_magn.c156 u8 reg_val; member
291 int ret, reg_val; in bmc150_magn_get_odr() local
294 ret = regmap_read(data->regmap, BMC150_MAGN_REG_OPMODE_ODR, &reg_val); in bmc150_magn_get_odr()
297 odr_val = (reg_val & BMC150_MAGN_MASK_ODR) >> BMC150_MAGN_SHIFT_ODR; in bmc150_magn_get_odr()
300 if (bmc150_magn_samp_freq_table[i].reg_val == odr_val) { in bmc150_magn_get_odr()
319 reg_val << in bmc150_magn_set_odr()
333 int ret, reg_val, max_odr; in bmc150_magn_set_max_odr() local
337 &reg_val); in bmc150_magn_set_max_odr()
340 rep_xy = BMC150_MAGN_REGVAL_TO_REPXY(reg_val); in bmc150_magn_set_max_odr()
344 &reg_val); in bmc150_magn_set_max_odr()
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/linux-4.19.296/include/linux/mfd/
Daxp20x.h654 unsigned int reg_val, result; in axp20x_read_variable_width() local
657 err = regmap_read(regmap, reg, &reg_val); in axp20x_read_variable_width()
661 result = reg_val << (width - 8); in axp20x_read_variable_width()
663 err = regmap_read(regmap, reg + 1, &reg_val); in axp20x_read_variable_width()
667 result |= reg_val; in axp20x_read_variable_width()
/linux-4.19.296/drivers/ptp/
Dptp_dte.c59 u32 reg_val[DTE_NUM_REGS_TO_RESTORE]; member
296 ptp_dte->reg_val[i] = in ptp_dte_suspend()
314 writel(ptp_dte->reg_val[i], in ptp_dte_resume()
317 writel(((ptp_dte->reg_val[i] & in ptp_dte_resume()
/linux-4.19.296/drivers/iio/health/
Dafe4403.c149 unsigned int reg_val; in afe440x_show_register() local
153 ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val); in afe440x_show_register()
157 if (reg_val >= afe440x_attr->table_size) in afe440x_show_register()
160 vals[0] = afe440x_attr->val_table[reg_val].integer; in afe440x_show_register()
161 vals[1] = afe440x_attr->val_table[reg_val].fract; in afe440x_show_register()

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