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Searched refs:regofs (Results 1 – 6 of 6) sorted by relevance

/linux-4.19.296/drivers/clk/mediatek/
Dreset.c26 int regofs; member
35 return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), in mtk_reset_assert()
44 return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), in mtk_reset_deassert()
67 unsigned int num_regs, int regofs) in mtk_register_reset_controller() argument
85 data->regofs = regofs; in mtk_register_reset_controller()
Dclk-mtk.h233 unsigned int num_regs, int regofs);
/linux-4.19.296/drivers/clk/sirf/
Dclk-common.c36 unsigned short regofs; /* register offset */ member
44 unsigned short regofs; /* register offset */ member
79 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - in pll_clk_recalc_rate()
87 u32 cfg0 = clkc_readl(clk->regofs); in pll_clk_recalc_rate()
151 clkc_writel(reg, clk->regofs); in pll_clk_set_rate()
153 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
156 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
219 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
226 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
233 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
[all …]
Dclk-atlas6.c22 .regofs = SIRFSOC_CLKC_MMC01_CFG,
30 .regofs = SIRFSOC_CLKC_MMC23_CFG,
38 .regofs = SIRFSOC_CLKC_MMC45_CFG,
53 .regofs = SIRFSOC_CLKC_NAND_CFG,
Dclk-atlas7.c216 u16 regofs; /* register offset */ member
235 u16 regofs; member
274 u32 regofs; member
359 u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 - in pll_clk_recalc_rate()
361 u32 regfreq = clkc_readl(clk->regofs); in pll_clk_recalc_rate()
362 u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC - in pll_clk_recalc_rate()
403 .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ,
417 .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ,
431 .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ,
445 .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ,
[all …]
Dclk-prima2.c22 .regofs = SIRFSOC_CLKC_MMC_CFG,
30 .regofs = SIRFSOC_CLKC_MMC_CFG,
38 .regofs = SIRFSOC_CLKC_MMC_CFG,