Home
last modified time | relevance | path

Searched refs:shift (Results 1 – 25 of 432) sorted by relevance

12345678910>>...18

/linux-4.19.296/drivers/bus/
Domap_l3_smx.h43 static const u64 shift = 1; variable
45 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
46 #define L3_STATUS_0_MPUIA_RSP (shift << 1)
47 #define L3_STATUS_0_MPUIA_INBAND (shift << 2)
48 #define L3_STATUS_0_IVAIA_BRST (shift << 6)
49 #define L3_STATUS_0_IVAIA_RSP (shift << 7)
50 #define L3_STATUS_0_IVAIA_INBAND (shift << 8)
51 #define L3_STATUS_0_SGXIA_BRST (shift << 9)
52 #define L3_STATUS_0_SGXIA_RSP (shift << 10)
53 #define L3_STATUS_0_SGXIA_MERROR (shift << 11)
[all …]
Dda8xx-mstpri.c58 int shift; member
65 .shift = 0,
70 .shift = 4,
75 .shift = 16,
80 .shift = 20,
85 .shift = 0,
90 .shift = 4,
95 .shift = 8,
100 .shift = 12,
105 .shift = 16,
[all …]
Dqcom-ebi2.c170 u16 shift; member
178 .shift = EBI2_XMEM_RECOVERY_SHIFT,
184 .shift = EBI2_XMEM_WR_HOLD_SHIFT,
190 .shift = EBI2_XMEM_WR_DELTA_SHIFT,
196 .shift = EBI2_XMEM_RD_DELTA_SHIFT,
202 .shift = EBI2_XMEM_WR_WAIT_SHIFT,
208 .shift = EBI2_XMEM_RD_WAIT_SHIFT,
214 .shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT,
220 .shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT,
226 .shift = EBI2_XMEM_RD_HOLD_SHIFT,
[all …]
/linux-4.19.296/include/linux/
Dbitops.h62 static inline __u64 rol64(__u64 word, unsigned int shift) in rol64() argument
64 return (word << (shift & 63)) | (word >> ((-shift) & 63)); in rol64()
72 static inline __u64 ror64(__u64 word, unsigned int shift) in ror64() argument
74 return (word >> (shift & 63)) | (word << ((-shift) & 63)); in ror64()
82 static inline __u32 rol32(__u32 word, unsigned int shift) in rol32() argument
84 return (word << (shift & 31)) | (word >> ((-shift) & 31)); in rol32()
92 static inline __u32 ror32(__u32 word, unsigned int shift) in ror32() argument
94 return (word >> (shift & 31)) | (word << ((-shift) & 31)); in ror32()
102 static inline __u16 rol16(__u16 word, unsigned int shift) in rol16() argument
104 return (word << (shift & 15)) | (word >> ((-shift) & 15)); in rol16()
[all …]
/linux-4.19.296/drivers/memory/tegra/
Dtegra30.c31 .shift = 0,
45 .shift = 0,
59 .shift = 16,
73 .shift = 16,
87 .shift = 0,
101 .shift = 0,
115 .shift = 16,
129 .shift = 16,
143 .shift = 0,
157 .shift = 0,
[all …]
Dtegra210.c28 .shift = 0,
42 .shift = 0,
56 .shift = 16,
70 .shift = 16,
84 .shift = 0,
98 .shift = 0,
112 .shift = 0,
126 .shift = 0,
140 .shift = 0,
154 .shift = 0,
[all …]
Dtegra114.c31 .shift = 0,
45 .shift = 0,
59 .shift = 16,
73 .shift = 16,
87 .shift = 0,
101 .shift = 0,
115 .shift = 0,
129 .shift = 0,
143 .shift = 16,
157 .shift = 0,
[all …]
Dtegra124.c73 .shift = 0,
87 .shift = 0,
101 .shift = 16,
115 .shift = 16,
129 .shift = 0,
143 .shift = 0,
157 .shift = 0,
171 .shift = 0,
185 .shift = 0,
199 .shift = 0,
[all …]
/linux-4.19.296/drivers/clk/imx/
Dclk.h55 void __iomem *reg, u8 shift, u32 exclusive_mask);
61 void __iomem *reg, u8 shift, u8 width,
64 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
69 void __iomem *reg, u8 shift, u8 width,
73 u8 shift, u8 width, const char * const *parents,
82 u8 shift, u8 width, const char * const *parents, in imx_clk_mux_ldb() argument
87 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); in imx_clk_mux_ldb()
98 void __iomem *reg, u8 shift, u8 width) in imx_clk_divider() argument
101 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider()
105 const char *parent, void __iomem *reg, u8 shift, u8 width, in imx_clk_divider_flags() argument
[all …]
Dclk-busy.c21 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
25 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
36 u8 shift; member
70 ret = clk_busy_wait(busy->reg, busy->shift); in clk_busy_divider_set_rate()
82 void __iomem *reg, u8 shift, u8 width, in imx_clk_busy_divider() argument
94 busy->shift = busy_shift; in imx_clk_busy_divider()
97 busy->div.shift = shift; in imx_clk_busy_divider()
121 u8 shift; member
145 ret = clk_busy_wait(busy->reg, busy->shift); in clk_busy_mux_set_parent()
155 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, in imx_clk_busy_mux() argument
[all …]
/linux-4.19.296/include/drm/
Ddrm_fixed.h99 unsigned shift, sign = (a >> 63) & 1; in drm_fixp_msbset() local
101 for (shift = 62; shift > 0; --shift) in drm_fixp_msbset()
102 if (((a >> shift) & 1) != sign) in drm_fixp_msbset()
103 return shift; in drm_fixp_msbset()
110 unsigned shift = drm_fixp_msbset(a) + drm_fixp_msbset(b); in drm_fixp_mul() local
113 if (shift > 61) { in drm_fixp_mul()
114 shift = shift - 61; in drm_fixp_mul()
115 a >>= (shift >> 1) + (shift & 1); in drm_fixp_mul()
116 b >>= shift >> 1; in drm_fixp_mul()
118 shift = 0; in drm_fixp_mul()
[all …]
/linux-4.19.296/drivers/clk/meson/
Dclkc.h14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
17 #define PARM_GET(width, shift, reg) \ argument
18 (((reg) & SETPMASK(width, shift)) >> (shift))
19 #define PARM_SET(width, shift, reg, val) \ argument
20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
26 u8 shift; member
35 return PARM_GET(p->width, p->shift, val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
42 val << p->shift); in meson_parm_write()
Daxg.c29 .shift = 0,
34 .shift = 9,
39 .shift = 16,
44 .shift = 0,
49 .shift = 31,
54 .shift = 29,
70 .shift = 0,
75 .shift = 9,
80 .shift = 16,
85 .shift = 31,
[all …]
Dgxbb.c182 .shift = 0,
187 .shift = 9,
192 .shift = 16,
197 .shift = 0,
202 .shift = 31,
207 .shift = 29,
234 .shift = 0,
239 .shift = 9,
244 .shift = 0,
249 .shift = 16,
[all …]
/linux-4.19.296/include/linux/mfd/
Dtmio.h28 #define sd_config_write8(base, shift, reg, val) \ argument
29 tmio_iowrite8((val), (base) + ((reg) << (shift)))
30 #define sd_config_write16(base, shift, reg, val) \ argument
31 tmio_iowrite16((val), (base) + ((reg) << (shift)))
32 #define sd_config_write32(base, shift, reg, val) \ argument
34 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
35 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
96 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
97 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
98 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
[all …]
/linux-4.19.296/drivers/reset/
Dreset-pistachio.c71 int shift; in pistachio_reset_assert() local
74 shift = pistachio_reset_shift(id); in pistachio_reset_assert()
75 if (shift < 0) in pistachio_reset_assert()
76 return shift; in pistachio_reset_assert()
77 mask = BIT(shift); in pistachio_reset_assert()
88 int shift; in pistachio_reset_deassert() local
91 shift = pistachio_reset_shift(id); in pistachio_reset_deassert()
92 if (shift < 0) in pistachio_reset_deassert()
93 return shift; in pistachio_reset_deassert()
94 mask = BIT(shift); in pistachio_reset_deassert()
/linux-4.19.296/drivers/clk/sunxi/
Dclk-sun6i-ar100.c29 int shift; in sun6i_get_ar100_factors() local
38 shift = 0; in sun6i_get_ar100_factors()
40 shift = 1; in sun6i_get_ar100_factors()
42 shift = 2; in sun6i_get_ar100_factors()
44 shift = 3; in sun6i_get_ar100_factors()
46 div >>= shift; in sun6i_get_ar100_factors()
51 req->rate = (req->parent_rate >> shift) / div; in sun6i_get_ar100_factors()
53 req->p = shift; in sun6i_get_ar100_factors()
/linux-4.19.296/drivers/clk/
Dclk-axm5516.c81 u32 shift; member
97 div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1)); in axxia_divclk_recalc_rate()
116 u32 shift; member
131 parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1); in axxia_clkmux_get_parent()
219 .shift = 0,
233 .shift = 4,
247 .shift = 8,
261 .shift = 12,
275 .shift = 0,
289 .shift = 4,
[all …]
Dclk-mux.c79 val = clk_readl(mux->reg) >> mux->shift; in clk_mux_get_parent()
98 reg = mux->mask << (mux->shift + 16); in clk_mux_set_parent()
101 reg &= ~(mux->mask << mux->shift); in clk_mux_set_parent()
103 val = val << mux->shift; in clk_mux_set_parent()
138 void __iomem *reg, u8 shift, u32 mask, in clk_hw_register_mux_table() argument
149 if (width + shift > 16) { in clk_hw_register_mux_table()
171 mux->shift = shift; in clk_hw_register_mux_table()
192 void __iomem *reg, u8 shift, u32 mask, in clk_register_mux_table() argument
198 flags, reg, shift, mask, clk_mux_flags, in clk_register_mux_table()
209 void __iomem *reg, u8 shift, u8 width, in clk_register_mux() argument
[all …]
/linux-4.19.296/drivers/regulator/
Dmax8998.c103 int *reg, int *shift) in max8998_get_enable_register() argument
110 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
114 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
118 *shift = 7 - (ldo - MAX8998_LDO14); in max8998_get_enable_register()
122 *shift = 7 - (ldo - MAX8998_BUCK1); in max8998_get_enable_register()
126 *shift = 7 - (ldo - MAX8998_EN32KHZ_AP); in max8998_get_enable_register()
130 *shift = 7 - (ldo - MAX8998_ESAFEOUT1); in max8998_get_enable_register()
143 int ret, reg, shift = 8; in max8998_ldo_is_enabled() local
146 ret = max8998_get_enable_register(rdev, &reg, &shift); in max8998_ldo_is_enabled()
154 return val & (1 << shift); in max8998_ldo_is_enabled()
[all …]
/linux-4.19.296/drivers/s390/char/
Ddefkeymap.map146 shift control keycode 65 = F13
147 shift control keycode 66 = F14
148 shift control keycode 67 = F15
149 shift control keycode 68 = F16
150 shift control keycode 69 = F17
151 shift control keycode 70 = F18
152 shift control keycode 71 = F19
153 shift control keycode 72 = F20
154 shift control keycode 73 = F21
155 shift control keycode 113 = F1
[all …]
/linux-4.19.296/drivers/clk/rockchip/
Dclk-muxgrf.c24 u32 shift; member
39 val >>= mux->shift; in rockchip_muxgrf_get_parent()
48 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); in rockchip_muxgrf_set_parent()
52 val <<= mux->shift; in rockchip_muxgrf_set_parent()
69 int shift, int width, int mux_flags) in rockchip_clk_register_muxgrf() argument
93 muxgrf_clock->shift = shift; in rockchip_clk_register_muxgrf()
/linux-4.19.296/drivers/clk/mxs/
Dclk.h25 int mxs_clk_wait(void __iomem *reg, u8 shift);
34 void __iomem *reg, u8 shift, u8 width, u8 busy);
37 void __iomem *reg, u8 shift, u8 width, u8 busy);
45 const char *parent_name, void __iomem *reg, u8 shift) in mxs_clk_gate() argument
48 reg, shift, CLK_GATE_SET_TO_DISABLE, in mxs_clk_gate()
53 u8 shift, u8 width, const char *const *parent_names, int num_parents) in mxs_clk_mux() argument
57 reg, shift, width, 0, &mxs_lock); in mxs_clk_mux()
/linux-4.19.296/lib/
Dts_bm.c71 int shift = bm->patlen - 1; in bm_find() local
78 while (shift < text_len) { in bm_find()
80 shift, text[shift]); in bm_find()
82 if ((icase ? toupper(text[shift-i]) in bm_find()
83 : text[shift-i]) in bm_find()
89 return consumed += (shift-(bm->patlen-1)); in bm_find()
91 next: bs = bm->bad_shift[text[shift-i]]; in bm_find()
94 shift = max_t(int, shift-i+bs, shift+bm->good_shift[i]); in bm_find()
/linux-4.19.296/drivers/clk/ti/
Dautoidle.c29 u8 shift; member
79 val &= ~(1 << clk->shift); in _allow_autoidle()
81 val |= (1 << clk->shift); in _allow_autoidle()
93 val |= (1 << clk->shift); in _deny_autoidle()
95 val &= ~(1 << clk->shift); in _deny_autoidle()
141 u32 shift; in of_ti_clk_autoidle_setup() local
146 if (of_property_read_u32(node, "ti,autoidle-shift", &shift)) in of_ti_clk_autoidle_setup()
154 clk->shift = shift; in of_ti_clk_autoidle_setup()

12345678910>>...18