1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4), 80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5), 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_UCTX = 0x0004, 85 MLX5_OBJ_TYPE_UMEM = 0x0005, 86 }; 87 88 enum { 89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 91 MLX5_CMD_OP_INIT_HCA = 0x102, 92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 93 MLX5_CMD_OP_ENABLE_HCA = 0x104, 94 MLX5_CMD_OP_DISABLE_HCA = 0x105, 95 MLX5_CMD_OP_QUERY_PAGES = 0x107, 96 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 97 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 98 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 99 MLX5_CMD_OP_SET_ISSI = 0x10b, 100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 108 MLX5_CMD_OP_CREATE_EQ = 0x301, 109 MLX5_CMD_OP_DESTROY_EQ = 0x302, 110 MLX5_CMD_OP_QUERY_EQ = 0x303, 111 MLX5_CMD_OP_GEN_EQE = 0x304, 112 MLX5_CMD_OP_CREATE_CQ = 0x400, 113 MLX5_CMD_OP_DESTROY_CQ = 0x401, 114 MLX5_CMD_OP_QUERY_CQ = 0x402, 115 MLX5_CMD_OP_MODIFY_CQ = 0x403, 116 MLX5_CMD_OP_CREATE_QP = 0x500, 117 MLX5_CMD_OP_DESTROY_QP = 0x501, 118 MLX5_CMD_OP_RST2INIT_QP = 0x502, 119 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 120 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 121 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 123 MLX5_CMD_OP_2ERR_QP = 0x507, 124 MLX5_CMD_OP_2RST_QP = 0x50a, 125 MLX5_CMD_OP_QUERY_QP = 0x50b, 126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 128 MLX5_CMD_OP_CREATE_PSV = 0x600, 129 MLX5_CMD_OP_DESTROY_PSV = 0x601, 130 MLX5_CMD_OP_CREATE_SRQ = 0x700, 131 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 132 MLX5_CMD_OP_QUERY_SRQ = 0x702, 133 MLX5_CMD_OP_ARM_RQ = 0x703, 134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 138 MLX5_CMD_OP_CREATE_DCT = 0x710, 139 MLX5_CMD_OP_DESTROY_DCT = 0x711, 140 MLX5_CMD_OP_DRAIN_DCT = 0x712, 141 MLX5_CMD_OP_QUERY_DCT = 0x713, 142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 143 MLX5_CMD_OP_CREATE_XRQ = 0x717, 144 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 145 MLX5_CMD_OP_QUERY_XRQ = 0x719, 146 MLX5_CMD_OP_ARM_XRQ = 0x71a, 147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 172 MLX5_CMD_OP_ALLOC_PD = 0x800, 173 MLX5_CMD_OP_DEALLOC_PD = 0x801, 174 MLX5_CMD_OP_ALLOC_UAR = 0x802, 175 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 177 MLX5_CMD_OP_ACCESS_REG = 0x805, 178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 181 MLX5_CMD_OP_MAD_IFC = 0x50d, 182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 184 MLX5_CMD_OP_NOP = 0x80d, 185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_CREATE_TIS = 0x912, 225 MLX5_CMD_OP_MODIFY_TIS = 0x913, 226 MLX5_CMD_OP_DESTROY_TIS = 0x914, 227 MLX5_CMD_OP_QUERY_TIS = 0x915, 228 MLX5_CMD_OP_CREATE_RQT = 0x916, 229 MLX5_CMD_OP_MODIFY_RQT = 0x917, 230 MLX5_CMD_OP_DESTROY_RQT = 0x918, 231 MLX5_CMD_OP_QUERY_RQT = 0x919, 232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 246 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 247 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 260 MLX5_CMD_OP_MAX 261 }; 262 263 struct mlx5_ifc_flow_table_fields_supported_bits { 264 u8 outer_dmac[0x1]; 265 u8 outer_smac[0x1]; 266 u8 outer_ether_type[0x1]; 267 u8 outer_ip_version[0x1]; 268 u8 outer_first_prio[0x1]; 269 u8 outer_first_cfi[0x1]; 270 u8 outer_first_vid[0x1]; 271 u8 outer_ipv4_ttl[0x1]; 272 u8 outer_second_prio[0x1]; 273 u8 outer_second_cfi[0x1]; 274 u8 outer_second_vid[0x1]; 275 u8 reserved_at_b[0x1]; 276 u8 outer_sip[0x1]; 277 u8 outer_dip[0x1]; 278 u8 outer_frag[0x1]; 279 u8 outer_ip_protocol[0x1]; 280 u8 outer_ip_ecn[0x1]; 281 u8 outer_ip_dscp[0x1]; 282 u8 outer_udp_sport[0x1]; 283 u8 outer_udp_dport[0x1]; 284 u8 outer_tcp_sport[0x1]; 285 u8 outer_tcp_dport[0x1]; 286 u8 outer_tcp_flags[0x1]; 287 u8 outer_gre_protocol[0x1]; 288 u8 outer_gre_key[0x1]; 289 u8 outer_vxlan_vni[0x1]; 290 u8 reserved_at_1a[0x5]; 291 u8 source_eswitch_port[0x1]; 292 293 u8 inner_dmac[0x1]; 294 u8 inner_smac[0x1]; 295 u8 inner_ether_type[0x1]; 296 u8 inner_ip_version[0x1]; 297 u8 inner_first_prio[0x1]; 298 u8 inner_first_cfi[0x1]; 299 u8 inner_first_vid[0x1]; 300 u8 reserved_at_27[0x1]; 301 u8 inner_second_prio[0x1]; 302 u8 inner_second_cfi[0x1]; 303 u8 inner_second_vid[0x1]; 304 u8 reserved_at_2b[0x1]; 305 u8 inner_sip[0x1]; 306 u8 inner_dip[0x1]; 307 u8 inner_frag[0x1]; 308 u8 inner_ip_protocol[0x1]; 309 u8 inner_ip_ecn[0x1]; 310 u8 inner_ip_dscp[0x1]; 311 u8 inner_udp_sport[0x1]; 312 u8 inner_udp_dport[0x1]; 313 u8 inner_tcp_sport[0x1]; 314 u8 inner_tcp_dport[0x1]; 315 u8 inner_tcp_flags[0x1]; 316 u8 reserved_at_37[0x9]; 317 318 u8 reserved_at_40[0x5]; 319 u8 outer_first_mpls_over_udp[0x4]; 320 u8 outer_first_mpls_over_gre[0x4]; 321 u8 inner_first_mpls[0x4]; 322 u8 outer_first_mpls[0x4]; 323 u8 reserved_at_55[0x2]; 324 u8 outer_esp_spi[0x1]; 325 u8 reserved_at_58[0x2]; 326 u8 bth_dst_qp[0x1]; 327 328 u8 reserved_at_5b[0x25]; 329 }; 330 331 struct mlx5_ifc_flow_table_prop_layout_bits { 332 u8 ft_support[0x1]; 333 u8 reserved_at_1[0x1]; 334 u8 flow_counter[0x1]; 335 u8 flow_modify_en[0x1]; 336 u8 modify_root[0x1]; 337 u8 identified_miss_table_mode[0x1]; 338 u8 flow_table_modify[0x1]; 339 u8 encap[0x1]; 340 u8 decap[0x1]; 341 u8 reserved_at_9[0x1]; 342 u8 pop_vlan[0x1]; 343 u8 push_vlan[0x1]; 344 u8 reserved_at_c[0x1]; 345 u8 pop_vlan_2[0x1]; 346 u8 push_vlan_2[0x1]; 347 u8 reserved_at_f[0x11]; 348 349 u8 reserved_at_20[0x2]; 350 u8 log_max_ft_size[0x6]; 351 u8 log_max_modify_header_context[0x8]; 352 u8 max_modify_header_actions[0x8]; 353 u8 max_ft_level[0x8]; 354 355 u8 reserved_at_40[0x20]; 356 357 u8 reserved_at_60[0x18]; 358 u8 log_max_ft_num[0x8]; 359 360 u8 reserved_at_80[0x10]; 361 u8 log_max_flow_counter[0x8]; 362 u8 log_max_destination[0x8]; 363 364 u8 reserved_at_a0[0x18]; 365 u8 log_max_flow[0x8]; 366 367 u8 reserved_at_c0[0x40]; 368 369 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 370 371 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 372 }; 373 374 struct mlx5_ifc_odp_per_transport_service_cap_bits { 375 u8 send[0x1]; 376 u8 receive[0x1]; 377 u8 write[0x1]; 378 u8 read[0x1]; 379 u8 atomic[0x1]; 380 u8 srq_receive[0x1]; 381 u8 reserved_at_6[0x1a]; 382 }; 383 384 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 385 u8 smac_47_16[0x20]; 386 387 u8 smac_15_0[0x10]; 388 u8 ethertype[0x10]; 389 390 u8 dmac_47_16[0x20]; 391 392 u8 dmac_15_0[0x10]; 393 u8 first_prio[0x3]; 394 u8 first_cfi[0x1]; 395 u8 first_vid[0xc]; 396 397 u8 ip_protocol[0x8]; 398 u8 ip_dscp[0x6]; 399 u8 ip_ecn[0x2]; 400 u8 cvlan_tag[0x1]; 401 u8 svlan_tag[0x1]; 402 u8 frag[0x1]; 403 u8 ip_version[0x4]; 404 u8 tcp_flags[0x9]; 405 406 u8 tcp_sport[0x10]; 407 u8 tcp_dport[0x10]; 408 409 u8 reserved_at_c0[0x18]; 410 u8 ttl_hoplimit[0x8]; 411 412 u8 udp_sport[0x10]; 413 u8 udp_dport[0x10]; 414 415 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 416 417 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 418 }; 419 420 struct mlx5_ifc_fte_match_set_misc_bits { 421 u8 reserved_at_0[0x8]; 422 u8 source_sqn[0x18]; 423 424 u8 source_eswitch_owner_vhca_id[0x10]; 425 u8 source_port[0x10]; 426 427 u8 outer_second_prio[0x3]; 428 u8 outer_second_cfi[0x1]; 429 u8 outer_second_vid[0xc]; 430 u8 inner_second_prio[0x3]; 431 u8 inner_second_cfi[0x1]; 432 u8 inner_second_vid[0xc]; 433 434 u8 outer_second_cvlan_tag[0x1]; 435 u8 inner_second_cvlan_tag[0x1]; 436 u8 outer_second_svlan_tag[0x1]; 437 u8 inner_second_svlan_tag[0x1]; 438 u8 reserved_at_64[0xc]; 439 u8 gre_protocol[0x10]; 440 441 u8 gre_key_h[0x18]; 442 u8 gre_key_l[0x8]; 443 444 u8 vxlan_vni[0x18]; 445 u8 reserved_at_b8[0x8]; 446 447 u8 reserved_at_c0[0x20]; 448 449 u8 reserved_at_e0[0xc]; 450 u8 outer_ipv6_flow_label[0x14]; 451 452 u8 reserved_at_100[0xc]; 453 u8 inner_ipv6_flow_label[0x14]; 454 455 u8 reserved_at_120[0x28]; 456 u8 bth_dst_qp[0x18]; 457 u8 reserved_at_160[0x20]; 458 u8 outer_esp_spi[0x20]; 459 u8 reserved_at_1a0[0x60]; 460 }; 461 462 struct mlx5_ifc_fte_match_mpls_bits { 463 u8 mpls_label[0x14]; 464 u8 mpls_exp[0x3]; 465 u8 mpls_s_bos[0x1]; 466 u8 mpls_ttl[0x8]; 467 }; 468 469 struct mlx5_ifc_fte_match_set_misc2_bits { 470 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 471 472 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 473 474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 475 476 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 477 478 u8 reserved_at_80[0x100]; 479 480 u8 metadata_reg_a[0x20]; 481 482 u8 reserved_at_1a0[0x60]; 483 }; 484 485 struct mlx5_ifc_cmd_pas_bits { 486 u8 pa_h[0x20]; 487 488 u8 pa_l[0x14]; 489 u8 reserved_at_34[0xc]; 490 }; 491 492 struct mlx5_ifc_uint64_bits { 493 u8 hi[0x20]; 494 495 u8 lo[0x20]; 496 }; 497 498 enum { 499 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 500 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 501 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 502 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 503 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 504 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 505 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 506 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 507 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 508 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 509 }; 510 511 struct mlx5_ifc_ads_bits { 512 u8 fl[0x1]; 513 u8 free_ar[0x1]; 514 u8 reserved_at_2[0xe]; 515 u8 pkey_index[0x10]; 516 517 u8 reserved_at_20[0x8]; 518 u8 grh[0x1]; 519 u8 mlid[0x7]; 520 u8 rlid[0x10]; 521 522 u8 ack_timeout[0x5]; 523 u8 reserved_at_45[0x3]; 524 u8 src_addr_index[0x8]; 525 u8 reserved_at_50[0x4]; 526 u8 stat_rate[0x4]; 527 u8 hop_limit[0x8]; 528 529 u8 reserved_at_60[0x4]; 530 u8 tclass[0x8]; 531 u8 flow_label[0x14]; 532 533 u8 rgid_rip[16][0x8]; 534 535 u8 reserved_at_100[0x4]; 536 u8 f_dscp[0x1]; 537 u8 f_ecn[0x1]; 538 u8 reserved_at_106[0x1]; 539 u8 f_eth_prio[0x1]; 540 u8 ecn[0x2]; 541 u8 dscp[0x6]; 542 u8 udp_sport[0x10]; 543 544 u8 dei_cfi[0x1]; 545 u8 eth_prio[0x3]; 546 u8 sl[0x4]; 547 u8 vhca_port_num[0x8]; 548 u8 rmac_47_32[0x10]; 549 550 u8 rmac_31_0[0x20]; 551 }; 552 553 struct mlx5_ifc_flow_table_nic_cap_bits { 554 u8 nic_rx_multi_path_tirs[0x1]; 555 u8 nic_rx_multi_path_tirs_fts[0x1]; 556 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 557 u8 reserved_at_3[0x1fd]; 558 559 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 560 561 u8 reserved_at_400[0x200]; 562 563 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 564 565 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 566 567 u8 reserved_at_a00[0x200]; 568 569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 570 571 u8 reserved_at_e00[0x7200]; 572 }; 573 574 struct mlx5_ifc_flow_table_eswitch_cap_bits { 575 u8 reserved_at_0[0x1c]; 576 u8 fdb_multi_path_to_table[0x1]; 577 u8 reserved_at_1d[0x1e3]; 578 579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 580 581 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 582 583 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 584 585 u8 reserved_at_800[0x7800]; 586 }; 587 588 struct mlx5_ifc_e_switch_cap_bits { 589 u8 vport_svlan_strip[0x1]; 590 u8 vport_cvlan_strip[0x1]; 591 u8 vport_svlan_insert[0x1]; 592 u8 vport_cvlan_insert_if_not_exist[0x1]; 593 u8 vport_cvlan_insert_overwrite[0x1]; 594 u8 reserved_at_5[0x18]; 595 u8 merged_eswitch[0x1]; 596 u8 nic_vport_node_guid_modify[0x1]; 597 u8 nic_vport_port_guid_modify[0x1]; 598 599 u8 vxlan_encap_decap[0x1]; 600 u8 nvgre_encap_decap[0x1]; 601 u8 reserved_at_22[0x9]; 602 u8 log_max_encap_headers[0x5]; 603 u8 reserved_2b[0x6]; 604 u8 max_encap_header_size[0xa]; 605 606 u8 reserved_40[0x7c0]; 607 608 }; 609 610 struct mlx5_ifc_qos_cap_bits { 611 u8 packet_pacing[0x1]; 612 u8 esw_scheduling[0x1]; 613 u8 esw_bw_share[0x1]; 614 u8 esw_rate_limit[0x1]; 615 u8 reserved_at_4[0x1]; 616 u8 packet_pacing_burst_bound[0x1]; 617 u8 packet_pacing_typical_size[0x1]; 618 u8 reserved_at_7[0x19]; 619 620 u8 reserved_at_20[0x20]; 621 622 u8 packet_pacing_max_rate[0x20]; 623 624 u8 packet_pacing_min_rate[0x20]; 625 626 u8 reserved_at_80[0x10]; 627 u8 packet_pacing_rate_table_size[0x10]; 628 629 u8 esw_element_type[0x10]; 630 u8 esw_tsar_type[0x10]; 631 632 u8 reserved_at_c0[0x10]; 633 u8 max_qos_para_vport[0x10]; 634 635 u8 max_tsar_bw_share[0x20]; 636 637 u8 reserved_at_100[0x700]; 638 }; 639 640 struct mlx5_ifc_debug_cap_bits { 641 u8 reserved_at_0[0x20]; 642 643 u8 reserved_at_20[0x2]; 644 u8 stall_detect[0x1]; 645 u8 reserved_at_23[0x1d]; 646 647 u8 reserved_at_40[0x7c0]; 648 }; 649 650 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 651 u8 csum_cap[0x1]; 652 u8 vlan_cap[0x1]; 653 u8 lro_cap[0x1]; 654 u8 lro_psh_flag[0x1]; 655 u8 lro_time_stamp[0x1]; 656 u8 reserved_at_5[0x2]; 657 u8 wqe_vlan_insert[0x1]; 658 u8 self_lb_en_modifiable[0x1]; 659 u8 reserved_at_9[0x2]; 660 u8 max_lso_cap[0x5]; 661 u8 multi_pkt_send_wqe[0x2]; 662 u8 wqe_inline_mode[0x2]; 663 u8 rss_ind_tbl_cap[0x4]; 664 u8 reg_umr_sq[0x1]; 665 u8 scatter_fcs[0x1]; 666 u8 enhanced_multi_pkt_send_wqe[0x1]; 667 u8 tunnel_lso_const_out_ip_id[0x1]; 668 u8 reserved_at_1c[0x2]; 669 u8 tunnel_stateless_gre[0x1]; 670 u8 tunnel_stateless_vxlan[0x1]; 671 672 u8 swp[0x1]; 673 u8 swp_csum[0x1]; 674 u8 swp_lso[0x1]; 675 u8 cqe_checksum_full[0x1]; 676 u8 tunnel_stateless_geneve_tx[0x1]; 677 u8 tunnel_stateless_mpls_over_udp[0x1]; 678 u8 tunnel_stateless_mpls_over_gre[0x1]; 679 u8 tunnel_stateless_vxlan_gpe[0x1]; 680 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 681 u8 tunnel_stateless_ip_over_ip[0x1]; 682 u8 reserved_at_2a[0x6]; 683 u8 max_vxlan_udp_ports[0x8]; 684 u8 reserved_at_38[0x6]; 685 u8 max_geneve_opt_len[0x1]; 686 u8 tunnel_stateless_geneve_rx[0x1]; 687 688 u8 reserved_at_40[0x10]; 689 u8 lro_min_mss_size[0x10]; 690 691 u8 reserved_at_60[0x120]; 692 693 u8 lro_timer_supported_periods[4][0x20]; 694 695 u8 reserved_at_200[0x600]; 696 }; 697 698 struct mlx5_ifc_roce_cap_bits { 699 u8 roce_apm[0x1]; 700 u8 reserved_at_1[0x1f]; 701 702 u8 reserved_at_20[0x60]; 703 704 u8 reserved_at_80[0xc]; 705 u8 l3_type[0x4]; 706 u8 reserved_at_90[0x8]; 707 u8 roce_version[0x8]; 708 709 u8 reserved_at_a0[0x10]; 710 u8 r_roce_dest_udp_port[0x10]; 711 712 u8 r_roce_max_src_udp_port[0x10]; 713 u8 r_roce_min_src_udp_port[0x10]; 714 715 u8 reserved_at_e0[0x10]; 716 u8 roce_address_table_size[0x10]; 717 718 u8 reserved_at_100[0x700]; 719 }; 720 721 struct mlx5_ifc_device_mem_cap_bits { 722 u8 memic[0x1]; 723 u8 reserved_at_1[0x1f]; 724 725 u8 reserved_at_20[0xb]; 726 u8 log_min_memic_alloc_size[0x5]; 727 u8 reserved_at_30[0x8]; 728 u8 log_max_memic_addr_alignment[0x8]; 729 730 u8 memic_bar_start_addr[0x40]; 731 732 u8 memic_bar_size[0x20]; 733 734 u8 max_memic_size[0x20]; 735 736 u8 reserved_at_c0[0x740]; 737 }; 738 739 enum { 740 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 741 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 742 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 743 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 744 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 749 }; 750 751 enum { 752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 754 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 755 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 756 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 757 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 758 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 759 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 760 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 761 }; 762 763 struct mlx5_ifc_atomic_caps_bits { 764 u8 reserved_at_0[0x40]; 765 766 u8 atomic_req_8B_endianness_mode[0x2]; 767 u8 reserved_at_42[0x4]; 768 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 769 770 u8 reserved_at_47[0x19]; 771 772 u8 reserved_at_60[0x20]; 773 774 u8 reserved_at_80[0x10]; 775 u8 atomic_operations[0x10]; 776 777 u8 reserved_at_a0[0x10]; 778 u8 atomic_size_qp[0x10]; 779 780 u8 reserved_at_c0[0x10]; 781 u8 atomic_size_dc[0x10]; 782 783 u8 reserved_at_e0[0x720]; 784 }; 785 786 struct mlx5_ifc_odp_cap_bits { 787 u8 reserved_at_0[0x40]; 788 789 u8 sig[0x1]; 790 u8 reserved_at_41[0x1f]; 791 792 u8 reserved_at_60[0x20]; 793 794 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 795 796 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 797 798 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 799 800 u8 reserved_at_e0[0x720]; 801 }; 802 803 struct mlx5_ifc_calc_op { 804 u8 reserved_at_0[0x10]; 805 u8 reserved_at_10[0x9]; 806 u8 op_swap_endianness[0x1]; 807 u8 op_min[0x1]; 808 u8 op_xor[0x1]; 809 u8 op_or[0x1]; 810 u8 op_and[0x1]; 811 u8 op_max[0x1]; 812 u8 op_add[0x1]; 813 }; 814 815 struct mlx5_ifc_vector_calc_cap_bits { 816 u8 calc_matrix[0x1]; 817 u8 reserved_at_1[0x1f]; 818 u8 reserved_at_20[0x8]; 819 u8 max_vec_count[0x8]; 820 u8 reserved_at_30[0xd]; 821 u8 max_chunk_size[0x3]; 822 struct mlx5_ifc_calc_op calc0; 823 struct mlx5_ifc_calc_op calc1; 824 struct mlx5_ifc_calc_op calc2; 825 struct mlx5_ifc_calc_op calc3; 826 827 u8 reserved_at_e0[0x720]; 828 }; 829 830 enum { 831 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 832 MLX5_WQ_TYPE_CYCLIC = 0x1, 833 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 834 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 835 }; 836 837 enum { 838 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 839 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 840 }; 841 842 enum { 843 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 844 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 845 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 846 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 847 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 848 }; 849 850 enum { 851 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 852 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 853 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 854 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 855 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 856 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 857 }; 858 859 enum { 860 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 861 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 862 }; 863 864 enum { 865 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 866 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 867 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 868 }; 869 870 enum { 871 MLX5_CAP_PORT_TYPE_IB = 0x0, 872 MLX5_CAP_PORT_TYPE_ETH = 0x1, 873 }; 874 875 enum { 876 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 877 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 878 MLX5_CAP_UMR_FENCE_NONE = 0x2, 879 }; 880 881 struct mlx5_ifc_cmd_hca_cap_bits { 882 u8 reserved_at_0[0x30]; 883 u8 vhca_id[0x10]; 884 885 u8 reserved_at_40[0x40]; 886 887 u8 log_max_srq_sz[0x8]; 888 u8 log_max_qp_sz[0x8]; 889 u8 reserved_at_90[0xb]; 890 u8 log_max_qp[0x5]; 891 892 u8 reserved_at_a0[0xb]; 893 u8 log_max_srq[0x5]; 894 u8 reserved_at_b0[0x10]; 895 896 u8 reserved_at_c0[0x8]; 897 u8 log_max_cq_sz[0x8]; 898 u8 reserved_at_d0[0xb]; 899 u8 log_max_cq[0x5]; 900 901 u8 log_max_eq_sz[0x8]; 902 u8 reserved_at_e8[0x2]; 903 u8 log_max_mkey[0x6]; 904 u8 reserved_at_f0[0x8]; 905 u8 dump_fill_mkey[0x1]; 906 u8 reserved_at_f9[0x3]; 907 u8 log_max_eq[0x4]; 908 909 u8 max_indirection[0x8]; 910 u8 fixed_buffer_size[0x1]; 911 u8 log_max_mrw_sz[0x7]; 912 u8 force_teardown[0x1]; 913 u8 reserved_at_111[0x1]; 914 u8 log_max_bsf_list_size[0x6]; 915 u8 umr_extended_translation_offset[0x1]; 916 u8 null_mkey[0x1]; 917 u8 log_max_klm_list_size[0x6]; 918 919 u8 reserved_at_120[0xa]; 920 u8 log_max_ra_req_dc[0x6]; 921 u8 reserved_at_130[0xa]; 922 u8 log_max_ra_res_dc[0x6]; 923 924 u8 reserved_at_140[0xa]; 925 u8 log_max_ra_req_qp[0x6]; 926 u8 reserved_at_150[0xa]; 927 u8 log_max_ra_res_qp[0x6]; 928 929 u8 end_pad[0x1]; 930 u8 cc_query_allowed[0x1]; 931 u8 cc_modify_allowed[0x1]; 932 u8 start_pad[0x1]; 933 u8 cache_line_128byte[0x1]; 934 u8 reserved_at_165[0xa]; 935 u8 qcam_reg[0x1]; 936 u8 gid_table_size[0x10]; 937 938 u8 out_of_seq_cnt[0x1]; 939 u8 vport_counters[0x1]; 940 u8 retransmission_q_counters[0x1]; 941 u8 debug[0x1]; 942 u8 modify_rq_counter_set_id[0x1]; 943 u8 rq_delay_drop[0x1]; 944 u8 max_qp_cnt[0xa]; 945 u8 pkey_table_size[0x10]; 946 947 u8 vport_group_manager[0x1]; 948 u8 vhca_group_manager[0x1]; 949 u8 ib_virt[0x1]; 950 u8 eth_virt[0x1]; 951 u8 vnic_env_queue_counters[0x1]; 952 u8 ets[0x1]; 953 u8 nic_flow_table[0x1]; 954 u8 eswitch_manager[0x1]; 955 u8 device_memory[0x1]; 956 u8 mcam_reg[0x1]; 957 u8 pcam_reg[0x1]; 958 u8 local_ca_ack_delay[0x5]; 959 u8 port_module_event[0x1]; 960 u8 enhanced_error_q_counters[0x1]; 961 u8 ports_check[0x1]; 962 u8 reserved_at_1b3[0x1]; 963 u8 disable_link_up[0x1]; 964 u8 beacon_led[0x1]; 965 u8 port_type[0x2]; 966 u8 num_ports[0x8]; 967 968 u8 reserved_at_1c0[0x1]; 969 u8 pps[0x1]; 970 u8 pps_modify[0x1]; 971 u8 log_max_msg[0x5]; 972 u8 reserved_at_1c8[0x4]; 973 u8 max_tc[0x4]; 974 u8 temp_warn_event[0x1]; 975 u8 dcbx[0x1]; 976 u8 general_notification_event[0x1]; 977 u8 reserved_at_1d3[0x2]; 978 u8 fpga[0x1]; 979 u8 rol_s[0x1]; 980 u8 rol_g[0x1]; 981 u8 reserved_at_1d8[0x1]; 982 u8 wol_s[0x1]; 983 u8 wol_g[0x1]; 984 u8 wol_a[0x1]; 985 u8 wol_b[0x1]; 986 u8 wol_m[0x1]; 987 u8 wol_u[0x1]; 988 u8 wol_p[0x1]; 989 990 u8 stat_rate_support[0x10]; 991 u8 reserved_at_1f0[0xc]; 992 u8 cqe_version[0x4]; 993 994 u8 compact_address_vector[0x1]; 995 u8 striding_rq[0x1]; 996 u8 reserved_at_202[0x1]; 997 u8 ipoib_enhanced_offloads[0x1]; 998 u8 ipoib_basic_offloads[0x1]; 999 u8 reserved_at_205[0x1]; 1000 u8 repeated_block_disabled[0x1]; 1001 u8 umr_modify_entity_size_disabled[0x1]; 1002 u8 umr_modify_atomic_disabled[0x1]; 1003 u8 umr_indirect_mkey_disabled[0x1]; 1004 u8 umr_fence[0x2]; 1005 u8 reserved_at_20c[0x3]; 1006 u8 drain_sigerr[0x1]; 1007 u8 cmdif_checksum[0x2]; 1008 u8 sigerr_cqe[0x1]; 1009 u8 reserved_at_213[0x1]; 1010 u8 wq_signature[0x1]; 1011 u8 sctr_data_cqe[0x1]; 1012 u8 reserved_at_216[0x1]; 1013 u8 sho[0x1]; 1014 u8 tph[0x1]; 1015 u8 rf[0x1]; 1016 u8 dct[0x1]; 1017 u8 qos[0x1]; 1018 u8 eth_net_offloads[0x1]; 1019 u8 roce[0x1]; 1020 u8 atomic[0x1]; 1021 u8 reserved_at_21f[0x1]; 1022 1023 u8 cq_oi[0x1]; 1024 u8 cq_resize[0x1]; 1025 u8 cq_moderation[0x1]; 1026 u8 reserved_at_223[0x3]; 1027 u8 cq_eq_remap[0x1]; 1028 u8 pg[0x1]; 1029 u8 block_lb_mc[0x1]; 1030 u8 reserved_at_229[0x1]; 1031 u8 scqe_break_moderation[0x1]; 1032 u8 cq_period_start_from_cqe[0x1]; 1033 u8 cd[0x1]; 1034 u8 reserved_at_22d[0x1]; 1035 u8 apm[0x1]; 1036 u8 vector_calc[0x1]; 1037 u8 umr_ptr_rlky[0x1]; 1038 u8 imaicl[0x1]; 1039 u8 reserved_at_232[0x4]; 1040 u8 qkv[0x1]; 1041 u8 pkv[0x1]; 1042 u8 set_deth_sqpn[0x1]; 1043 u8 reserved_at_239[0x3]; 1044 u8 xrc[0x1]; 1045 u8 ud[0x1]; 1046 u8 uc[0x1]; 1047 u8 rc[0x1]; 1048 1049 u8 uar_4k[0x1]; 1050 u8 reserved_at_241[0x9]; 1051 u8 uar_sz[0x6]; 1052 u8 reserved_at_250[0x8]; 1053 u8 log_pg_sz[0x8]; 1054 1055 u8 bf[0x1]; 1056 u8 driver_version[0x1]; 1057 u8 pad_tx_eth_packet[0x1]; 1058 u8 reserved_at_263[0x8]; 1059 u8 log_bf_reg_size[0x5]; 1060 1061 u8 reserved_at_270[0xb]; 1062 u8 lag_master[0x1]; 1063 u8 num_lag_ports[0x4]; 1064 1065 u8 reserved_at_280[0x10]; 1066 u8 max_wqe_sz_sq[0x10]; 1067 1068 u8 reserved_at_2a0[0x10]; 1069 u8 max_wqe_sz_rq[0x10]; 1070 1071 u8 max_flow_counter_31_16[0x10]; 1072 u8 max_wqe_sz_sq_dc[0x10]; 1073 1074 u8 reserved_at_2e0[0x7]; 1075 u8 max_qp_mcg[0x19]; 1076 1077 u8 reserved_at_300[0x18]; 1078 u8 log_max_mcg[0x8]; 1079 1080 u8 reserved_at_320[0x3]; 1081 u8 log_max_transport_domain[0x5]; 1082 u8 reserved_at_328[0x3]; 1083 u8 log_max_pd[0x5]; 1084 u8 reserved_at_330[0xb]; 1085 u8 log_max_xrcd[0x5]; 1086 1087 u8 nic_receive_steering_discard[0x1]; 1088 u8 receive_discard_vport_down[0x1]; 1089 u8 transmit_discard_vport_down[0x1]; 1090 u8 reserved_at_343[0x5]; 1091 u8 log_max_flow_counter_bulk[0x8]; 1092 u8 max_flow_counter_15_0[0x10]; 1093 1094 1095 u8 reserved_at_360[0x3]; 1096 u8 log_max_rq[0x5]; 1097 u8 reserved_at_368[0x3]; 1098 u8 log_max_sq[0x5]; 1099 u8 reserved_at_370[0x3]; 1100 u8 log_max_tir[0x5]; 1101 u8 reserved_at_378[0x3]; 1102 u8 log_max_tis[0x5]; 1103 1104 u8 basic_cyclic_rcv_wqe[0x1]; 1105 u8 reserved_at_381[0x2]; 1106 u8 log_max_rmp[0x5]; 1107 u8 reserved_at_388[0x3]; 1108 u8 log_max_rqt[0x5]; 1109 u8 reserved_at_390[0x3]; 1110 u8 log_max_rqt_size[0x5]; 1111 u8 reserved_at_398[0x3]; 1112 u8 log_max_tis_per_sq[0x5]; 1113 1114 u8 ext_stride_num_range[0x1]; 1115 u8 reserved_at_3a1[0x2]; 1116 u8 log_max_stride_sz_rq[0x5]; 1117 u8 reserved_at_3a8[0x3]; 1118 u8 log_min_stride_sz_rq[0x5]; 1119 u8 reserved_at_3b0[0x3]; 1120 u8 log_max_stride_sz_sq[0x5]; 1121 u8 reserved_at_3b8[0x3]; 1122 u8 log_min_stride_sz_sq[0x5]; 1123 1124 u8 hairpin[0x1]; 1125 u8 reserved_at_3c1[0x2]; 1126 u8 log_max_hairpin_queues[0x5]; 1127 u8 reserved_at_3c8[0x3]; 1128 u8 log_max_hairpin_wq_data_sz[0x5]; 1129 u8 reserved_at_3d0[0x3]; 1130 u8 log_max_hairpin_num_packets[0x5]; 1131 u8 reserved_at_3d8[0x3]; 1132 u8 log_max_wq_sz[0x5]; 1133 1134 u8 nic_vport_change_event[0x1]; 1135 u8 disable_local_lb_uc[0x1]; 1136 u8 disable_local_lb_mc[0x1]; 1137 u8 log_min_hairpin_wq_data_sz[0x5]; 1138 u8 reserved_at_3e8[0x3]; 1139 u8 log_max_vlan_list[0x5]; 1140 u8 reserved_at_3f0[0x3]; 1141 u8 log_max_current_mc_list[0x5]; 1142 u8 reserved_at_3f8[0x3]; 1143 u8 log_max_current_uc_list[0x5]; 1144 1145 u8 general_obj_types[0x40]; 1146 1147 u8 reserved_at_440[0x20]; 1148 1149 u8 reserved_at_460[0x10]; 1150 u8 max_num_eqs[0x10]; 1151 1152 u8 reserved_at_480[0x3]; 1153 u8 log_max_l2_table[0x5]; 1154 u8 reserved_at_488[0x8]; 1155 u8 log_uar_page_sz[0x10]; 1156 1157 u8 reserved_at_4a0[0x20]; 1158 u8 device_frequency_mhz[0x20]; 1159 u8 device_frequency_khz[0x20]; 1160 1161 u8 reserved_at_500[0x20]; 1162 u8 num_of_uars_per_page[0x20]; 1163 1164 u8 flex_parser_protocols[0x20]; 1165 u8 reserved_at_560[0x20]; 1166 1167 u8 reserved_at_580[0x3c]; 1168 u8 mini_cqe_resp_stride_index[0x1]; 1169 u8 cqe_128_always[0x1]; 1170 u8 cqe_compression_128[0x1]; 1171 u8 cqe_compression[0x1]; 1172 1173 u8 cqe_compression_timeout[0x10]; 1174 u8 cqe_compression_max_num[0x10]; 1175 1176 u8 reserved_at_5e0[0x10]; 1177 u8 tag_matching[0x1]; 1178 u8 rndv_offload_rc[0x1]; 1179 u8 rndv_offload_dc[0x1]; 1180 u8 log_tag_matching_list_sz[0x5]; 1181 u8 reserved_at_5f8[0x3]; 1182 u8 log_max_xrq[0x5]; 1183 1184 u8 affiliate_nic_vport_criteria[0x8]; 1185 u8 native_port_num[0x8]; 1186 u8 num_vhca_ports[0x8]; 1187 u8 reserved_at_618[0x6]; 1188 u8 sw_owner_id[0x1]; 1189 u8 reserved_at_61f[0x1e1]; 1190 }; 1191 1192 enum mlx5_flow_destination_type { 1193 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1194 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1195 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1196 1197 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1198 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1199 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1200 }; 1201 1202 struct mlx5_ifc_dest_format_struct_bits { 1203 u8 destination_type[0x8]; 1204 u8 destination_id[0x18]; 1205 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1206 u8 reserved_at_21[0xf]; 1207 u8 destination_eswitch_owner_vhca_id[0x10]; 1208 }; 1209 1210 struct mlx5_ifc_flow_counter_list_bits { 1211 u8 flow_counter_id[0x20]; 1212 1213 u8 reserved_at_20[0x20]; 1214 }; 1215 1216 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1217 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1218 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1219 u8 reserved_at_0[0x40]; 1220 }; 1221 1222 struct mlx5_ifc_fte_match_param_bits { 1223 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1224 1225 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1226 1227 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1228 1229 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1230 1231 u8 reserved_at_800[0x800]; 1232 }; 1233 1234 enum { 1235 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1236 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1237 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1238 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1239 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1240 }; 1241 1242 struct mlx5_ifc_rx_hash_field_select_bits { 1243 u8 l3_prot_type[0x1]; 1244 u8 l4_prot_type[0x1]; 1245 u8 selected_fields[0x1e]; 1246 }; 1247 1248 enum { 1249 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1250 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1251 }; 1252 1253 enum { 1254 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1255 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1256 }; 1257 1258 struct mlx5_ifc_wq_bits { 1259 u8 wq_type[0x4]; 1260 u8 wq_signature[0x1]; 1261 u8 end_padding_mode[0x2]; 1262 u8 cd_slave[0x1]; 1263 u8 reserved_at_8[0x18]; 1264 1265 u8 hds_skip_first_sge[0x1]; 1266 u8 log2_hds_buf_size[0x3]; 1267 u8 reserved_at_24[0x7]; 1268 u8 page_offset[0x5]; 1269 u8 lwm[0x10]; 1270 1271 u8 reserved_at_40[0x8]; 1272 u8 pd[0x18]; 1273 1274 u8 reserved_at_60[0x8]; 1275 u8 uar_page[0x18]; 1276 1277 u8 dbr_addr[0x40]; 1278 1279 u8 hw_counter[0x20]; 1280 1281 u8 sw_counter[0x20]; 1282 1283 u8 reserved_at_100[0xc]; 1284 u8 log_wq_stride[0x4]; 1285 u8 reserved_at_110[0x3]; 1286 u8 log_wq_pg_sz[0x5]; 1287 u8 reserved_at_118[0x3]; 1288 u8 log_wq_sz[0x5]; 1289 1290 u8 reserved_at_120[0x3]; 1291 u8 log_hairpin_num_packets[0x5]; 1292 u8 reserved_at_128[0x3]; 1293 u8 log_hairpin_data_sz[0x5]; 1294 1295 u8 reserved_at_130[0x4]; 1296 u8 log_wqe_num_of_strides[0x4]; 1297 u8 two_byte_shift_en[0x1]; 1298 u8 reserved_at_139[0x4]; 1299 u8 log_wqe_stride_size[0x3]; 1300 1301 u8 reserved_at_140[0x4c0]; 1302 1303 struct mlx5_ifc_cmd_pas_bits pas[0]; 1304 }; 1305 1306 struct mlx5_ifc_rq_num_bits { 1307 u8 reserved_at_0[0x8]; 1308 u8 rq_num[0x18]; 1309 }; 1310 1311 struct mlx5_ifc_mac_address_layout_bits { 1312 u8 reserved_at_0[0x10]; 1313 u8 mac_addr_47_32[0x10]; 1314 1315 u8 mac_addr_31_0[0x20]; 1316 }; 1317 1318 struct mlx5_ifc_vlan_layout_bits { 1319 u8 reserved_at_0[0x14]; 1320 u8 vlan[0x0c]; 1321 1322 u8 reserved_at_20[0x20]; 1323 }; 1324 1325 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1326 u8 reserved_at_0[0xa0]; 1327 1328 u8 min_time_between_cnps[0x20]; 1329 1330 u8 reserved_at_c0[0x12]; 1331 u8 cnp_dscp[0x6]; 1332 u8 reserved_at_d8[0x4]; 1333 u8 cnp_prio_mode[0x1]; 1334 u8 cnp_802p_prio[0x3]; 1335 1336 u8 reserved_at_e0[0x720]; 1337 }; 1338 1339 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1340 u8 reserved_at_0[0x60]; 1341 1342 u8 reserved_at_60[0x4]; 1343 u8 clamp_tgt_rate[0x1]; 1344 u8 reserved_at_65[0x3]; 1345 u8 clamp_tgt_rate_after_time_inc[0x1]; 1346 u8 reserved_at_69[0x17]; 1347 1348 u8 reserved_at_80[0x20]; 1349 1350 u8 rpg_time_reset[0x20]; 1351 1352 u8 rpg_byte_reset[0x20]; 1353 1354 u8 rpg_threshold[0x20]; 1355 1356 u8 rpg_max_rate[0x20]; 1357 1358 u8 rpg_ai_rate[0x20]; 1359 1360 u8 rpg_hai_rate[0x20]; 1361 1362 u8 rpg_gd[0x20]; 1363 1364 u8 rpg_min_dec_fac[0x20]; 1365 1366 u8 rpg_min_rate[0x20]; 1367 1368 u8 reserved_at_1c0[0xe0]; 1369 1370 u8 rate_to_set_on_first_cnp[0x20]; 1371 1372 u8 dce_tcp_g[0x20]; 1373 1374 u8 dce_tcp_rtt[0x20]; 1375 1376 u8 rate_reduce_monitor_period[0x20]; 1377 1378 u8 reserved_at_320[0x20]; 1379 1380 u8 initial_alpha_value[0x20]; 1381 1382 u8 reserved_at_360[0x4a0]; 1383 }; 1384 1385 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1386 u8 reserved_at_0[0x80]; 1387 1388 u8 rppp_max_rps[0x20]; 1389 1390 u8 rpg_time_reset[0x20]; 1391 1392 u8 rpg_byte_reset[0x20]; 1393 1394 u8 rpg_threshold[0x20]; 1395 1396 u8 rpg_max_rate[0x20]; 1397 1398 u8 rpg_ai_rate[0x20]; 1399 1400 u8 rpg_hai_rate[0x20]; 1401 1402 u8 rpg_gd[0x20]; 1403 1404 u8 rpg_min_dec_fac[0x20]; 1405 1406 u8 rpg_min_rate[0x20]; 1407 1408 u8 reserved_at_1c0[0x640]; 1409 }; 1410 1411 enum { 1412 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1413 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1414 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1415 }; 1416 1417 struct mlx5_ifc_resize_field_select_bits { 1418 u8 resize_field_select[0x20]; 1419 }; 1420 1421 enum { 1422 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1423 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1424 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1425 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1426 }; 1427 1428 struct mlx5_ifc_modify_field_select_bits { 1429 u8 modify_field_select[0x20]; 1430 }; 1431 1432 struct mlx5_ifc_field_select_r_roce_np_bits { 1433 u8 field_select_r_roce_np[0x20]; 1434 }; 1435 1436 struct mlx5_ifc_field_select_r_roce_rp_bits { 1437 u8 field_select_r_roce_rp[0x20]; 1438 }; 1439 1440 enum { 1441 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1442 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1443 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1444 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1445 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1446 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1447 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1448 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1449 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1450 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1451 }; 1452 1453 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1454 u8 field_select_8021qaurp[0x20]; 1455 }; 1456 1457 struct mlx5_ifc_phys_layer_cntrs_bits { 1458 u8 time_since_last_clear_high[0x20]; 1459 1460 u8 time_since_last_clear_low[0x20]; 1461 1462 u8 symbol_errors_high[0x20]; 1463 1464 u8 symbol_errors_low[0x20]; 1465 1466 u8 sync_headers_errors_high[0x20]; 1467 1468 u8 sync_headers_errors_low[0x20]; 1469 1470 u8 edpl_bip_errors_lane0_high[0x20]; 1471 1472 u8 edpl_bip_errors_lane0_low[0x20]; 1473 1474 u8 edpl_bip_errors_lane1_high[0x20]; 1475 1476 u8 edpl_bip_errors_lane1_low[0x20]; 1477 1478 u8 edpl_bip_errors_lane2_high[0x20]; 1479 1480 u8 edpl_bip_errors_lane2_low[0x20]; 1481 1482 u8 edpl_bip_errors_lane3_high[0x20]; 1483 1484 u8 edpl_bip_errors_lane3_low[0x20]; 1485 1486 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1487 1488 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1489 1490 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1491 1492 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1493 1494 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1495 1496 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1497 1498 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1499 1500 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1501 1502 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1503 1504 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1505 1506 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1507 1508 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1509 1510 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1511 1512 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1513 1514 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1515 1516 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1517 1518 u8 rs_fec_corrected_blocks_high[0x20]; 1519 1520 u8 rs_fec_corrected_blocks_low[0x20]; 1521 1522 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1523 1524 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1525 1526 u8 rs_fec_no_errors_blocks_high[0x20]; 1527 1528 u8 rs_fec_no_errors_blocks_low[0x20]; 1529 1530 u8 rs_fec_single_error_blocks_high[0x20]; 1531 1532 u8 rs_fec_single_error_blocks_low[0x20]; 1533 1534 u8 rs_fec_corrected_symbols_total_high[0x20]; 1535 1536 u8 rs_fec_corrected_symbols_total_low[0x20]; 1537 1538 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1539 1540 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1541 1542 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1543 1544 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1545 1546 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1547 1548 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1549 1550 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1551 1552 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1553 1554 u8 link_down_events[0x20]; 1555 1556 u8 successful_recovery_events[0x20]; 1557 1558 u8 reserved_at_640[0x180]; 1559 }; 1560 1561 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1562 u8 time_since_last_clear_high[0x20]; 1563 1564 u8 time_since_last_clear_low[0x20]; 1565 1566 u8 phy_received_bits_high[0x20]; 1567 1568 u8 phy_received_bits_low[0x20]; 1569 1570 u8 phy_symbol_errors_high[0x20]; 1571 1572 u8 phy_symbol_errors_low[0x20]; 1573 1574 u8 phy_corrected_bits_high[0x20]; 1575 1576 u8 phy_corrected_bits_low[0x20]; 1577 1578 u8 phy_corrected_bits_lane0_high[0x20]; 1579 1580 u8 phy_corrected_bits_lane0_low[0x20]; 1581 1582 u8 phy_corrected_bits_lane1_high[0x20]; 1583 1584 u8 phy_corrected_bits_lane1_low[0x20]; 1585 1586 u8 phy_corrected_bits_lane2_high[0x20]; 1587 1588 u8 phy_corrected_bits_lane2_low[0x20]; 1589 1590 u8 phy_corrected_bits_lane3_high[0x20]; 1591 1592 u8 phy_corrected_bits_lane3_low[0x20]; 1593 1594 u8 reserved_at_200[0x5c0]; 1595 }; 1596 1597 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1598 u8 symbol_error_counter[0x10]; 1599 1600 u8 link_error_recovery_counter[0x8]; 1601 1602 u8 link_downed_counter[0x8]; 1603 1604 u8 port_rcv_errors[0x10]; 1605 1606 u8 port_rcv_remote_physical_errors[0x10]; 1607 1608 u8 port_rcv_switch_relay_errors[0x10]; 1609 1610 u8 port_xmit_discards[0x10]; 1611 1612 u8 port_xmit_constraint_errors[0x8]; 1613 1614 u8 port_rcv_constraint_errors[0x8]; 1615 1616 u8 reserved_at_70[0x8]; 1617 1618 u8 link_overrun_errors[0x8]; 1619 1620 u8 reserved_at_80[0x10]; 1621 1622 u8 vl_15_dropped[0x10]; 1623 1624 u8 reserved_at_a0[0x80]; 1625 1626 u8 port_xmit_wait[0x20]; 1627 }; 1628 1629 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1630 u8 transmit_queue_high[0x20]; 1631 1632 u8 transmit_queue_low[0x20]; 1633 1634 u8 reserved_at_40[0x780]; 1635 }; 1636 1637 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1638 u8 rx_octets_high[0x20]; 1639 1640 u8 rx_octets_low[0x20]; 1641 1642 u8 reserved_at_40[0xc0]; 1643 1644 u8 rx_frames_high[0x20]; 1645 1646 u8 rx_frames_low[0x20]; 1647 1648 u8 tx_octets_high[0x20]; 1649 1650 u8 tx_octets_low[0x20]; 1651 1652 u8 reserved_at_180[0xc0]; 1653 1654 u8 tx_frames_high[0x20]; 1655 1656 u8 tx_frames_low[0x20]; 1657 1658 u8 rx_pause_high[0x20]; 1659 1660 u8 rx_pause_low[0x20]; 1661 1662 u8 rx_pause_duration_high[0x20]; 1663 1664 u8 rx_pause_duration_low[0x20]; 1665 1666 u8 tx_pause_high[0x20]; 1667 1668 u8 tx_pause_low[0x20]; 1669 1670 u8 tx_pause_duration_high[0x20]; 1671 1672 u8 tx_pause_duration_low[0x20]; 1673 1674 u8 rx_pause_transition_high[0x20]; 1675 1676 u8 rx_pause_transition_low[0x20]; 1677 1678 u8 reserved_at_3c0[0x40]; 1679 1680 u8 device_stall_minor_watermark_cnt_high[0x20]; 1681 1682 u8 device_stall_minor_watermark_cnt_low[0x20]; 1683 1684 u8 device_stall_critical_watermark_cnt_high[0x20]; 1685 1686 u8 device_stall_critical_watermark_cnt_low[0x20]; 1687 1688 u8 reserved_at_480[0x340]; 1689 }; 1690 1691 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1692 u8 port_transmit_wait_high[0x20]; 1693 1694 u8 port_transmit_wait_low[0x20]; 1695 1696 u8 reserved_at_40[0x100]; 1697 1698 u8 rx_buffer_almost_full_high[0x20]; 1699 1700 u8 rx_buffer_almost_full_low[0x20]; 1701 1702 u8 rx_buffer_full_high[0x20]; 1703 1704 u8 rx_buffer_full_low[0x20]; 1705 1706 u8 rx_icrc_encapsulated_high[0x20]; 1707 1708 u8 rx_icrc_encapsulated_low[0x20]; 1709 1710 u8 reserved_at_200[0x5c0]; 1711 }; 1712 1713 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1714 u8 dot3stats_alignment_errors_high[0x20]; 1715 1716 u8 dot3stats_alignment_errors_low[0x20]; 1717 1718 u8 dot3stats_fcs_errors_high[0x20]; 1719 1720 u8 dot3stats_fcs_errors_low[0x20]; 1721 1722 u8 dot3stats_single_collision_frames_high[0x20]; 1723 1724 u8 dot3stats_single_collision_frames_low[0x20]; 1725 1726 u8 dot3stats_multiple_collision_frames_high[0x20]; 1727 1728 u8 dot3stats_multiple_collision_frames_low[0x20]; 1729 1730 u8 dot3stats_sqe_test_errors_high[0x20]; 1731 1732 u8 dot3stats_sqe_test_errors_low[0x20]; 1733 1734 u8 dot3stats_deferred_transmissions_high[0x20]; 1735 1736 u8 dot3stats_deferred_transmissions_low[0x20]; 1737 1738 u8 dot3stats_late_collisions_high[0x20]; 1739 1740 u8 dot3stats_late_collisions_low[0x20]; 1741 1742 u8 dot3stats_excessive_collisions_high[0x20]; 1743 1744 u8 dot3stats_excessive_collisions_low[0x20]; 1745 1746 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1747 1748 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1749 1750 u8 dot3stats_carrier_sense_errors_high[0x20]; 1751 1752 u8 dot3stats_carrier_sense_errors_low[0x20]; 1753 1754 u8 dot3stats_frame_too_longs_high[0x20]; 1755 1756 u8 dot3stats_frame_too_longs_low[0x20]; 1757 1758 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1759 1760 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1761 1762 u8 dot3stats_symbol_errors_high[0x20]; 1763 1764 u8 dot3stats_symbol_errors_low[0x20]; 1765 1766 u8 dot3control_in_unknown_opcodes_high[0x20]; 1767 1768 u8 dot3control_in_unknown_opcodes_low[0x20]; 1769 1770 u8 dot3in_pause_frames_high[0x20]; 1771 1772 u8 dot3in_pause_frames_low[0x20]; 1773 1774 u8 dot3out_pause_frames_high[0x20]; 1775 1776 u8 dot3out_pause_frames_low[0x20]; 1777 1778 u8 reserved_at_400[0x3c0]; 1779 }; 1780 1781 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1782 u8 ether_stats_drop_events_high[0x20]; 1783 1784 u8 ether_stats_drop_events_low[0x20]; 1785 1786 u8 ether_stats_octets_high[0x20]; 1787 1788 u8 ether_stats_octets_low[0x20]; 1789 1790 u8 ether_stats_pkts_high[0x20]; 1791 1792 u8 ether_stats_pkts_low[0x20]; 1793 1794 u8 ether_stats_broadcast_pkts_high[0x20]; 1795 1796 u8 ether_stats_broadcast_pkts_low[0x20]; 1797 1798 u8 ether_stats_multicast_pkts_high[0x20]; 1799 1800 u8 ether_stats_multicast_pkts_low[0x20]; 1801 1802 u8 ether_stats_crc_align_errors_high[0x20]; 1803 1804 u8 ether_stats_crc_align_errors_low[0x20]; 1805 1806 u8 ether_stats_undersize_pkts_high[0x20]; 1807 1808 u8 ether_stats_undersize_pkts_low[0x20]; 1809 1810 u8 ether_stats_oversize_pkts_high[0x20]; 1811 1812 u8 ether_stats_oversize_pkts_low[0x20]; 1813 1814 u8 ether_stats_fragments_high[0x20]; 1815 1816 u8 ether_stats_fragments_low[0x20]; 1817 1818 u8 ether_stats_jabbers_high[0x20]; 1819 1820 u8 ether_stats_jabbers_low[0x20]; 1821 1822 u8 ether_stats_collisions_high[0x20]; 1823 1824 u8 ether_stats_collisions_low[0x20]; 1825 1826 u8 ether_stats_pkts64octets_high[0x20]; 1827 1828 u8 ether_stats_pkts64octets_low[0x20]; 1829 1830 u8 ether_stats_pkts65to127octets_high[0x20]; 1831 1832 u8 ether_stats_pkts65to127octets_low[0x20]; 1833 1834 u8 ether_stats_pkts128to255octets_high[0x20]; 1835 1836 u8 ether_stats_pkts128to255octets_low[0x20]; 1837 1838 u8 ether_stats_pkts256to511octets_high[0x20]; 1839 1840 u8 ether_stats_pkts256to511octets_low[0x20]; 1841 1842 u8 ether_stats_pkts512to1023octets_high[0x20]; 1843 1844 u8 ether_stats_pkts512to1023octets_low[0x20]; 1845 1846 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1847 1848 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1849 1850 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1851 1852 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1853 1854 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1855 1856 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1857 1858 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1859 1860 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1861 1862 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1863 1864 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1865 1866 u8 reserved_at_540[0x280]; 1867 }; 1868 1869 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1870 u8 if_in_octets_high[0x20]; 1871 1872 u8 if_in_octets_low[0x20]; 1873 1874 u8 if_in_ucast_pkts_high[0x20]; 1875 1876 u8 if_in_ucast_pkts_low[0x20]; 1877 1878 u8 if_in_discards_high[0x20]; 1879 1880 u8 if_in_discards_low[0x20]; 1881 1882 u8 if_in_errors_high[0x20]; 1883 1884 u8 if_in_errors_low[0x20]; 1885 1886 u8 if_in_unknown_protos_high[0x20]; 1887 1888 u8 if_in_unknown_protos_low[0x20]; 1889 1890 u8 if_out_octets_high[0x20]; 1891 1892 u8 if_out_octets_low[0x20]; 1893 1894 u8 if_out_ucast_pkts_high[0x20]; 1895 1896 u8 if_out_ucast_pkts_low[0x20]; 1897 1898 u8 if_out_discards_high[0x20]; 1899 1900 u8 if_out_discards_low[0x20]; 1901 1902 u8 if_out_errors_high[0x20]; 1903 1904 u8 if_out_errors_low[0x20]; 1905 1906 u8 if_in_multicast_pkts_high[0x20]; 1907 1908 u8 if_in_multicast_pkts_low[0x20]; 1909 1910 u8 if_in_broadcast_pkts_high[0x20]; 1911 1912 u8 if_in_broadcast_pkts_low[0x20]; 1913 1914 u8 if_out_multicast_pkts_high[0x20]; 1915 1916 u8 if_out_multicast_pkts_low[0x20]; 1917 1918 u8 if_out_broadcast_pkts_high[0x20]; 1919 1920 u8 if_out_broadcast_pkts_low[0x20]; 1921 1922 u8 reserved_at_340[0x480]; 1923 }; 1924 1925 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1926 u8 a_frames_transmitted_ok_high[0x20]; 1927 1928 u8 a_frames_transmitted_ok_low[0x20]; 1929 1930 u8 a_frames_received_ok_high[0x20]; 1931 1932 u8 a_frames_received_ok_low[0x20]; 1933 1934 u8 a_frame_check_sequence_errors_high[0x20]; 1935 1936 u8 a_frame_check_sequence_errors_low[0x20]; 1937 1938 u8 a_alignment_errors_high[0x20]; 1939 1940 u8 a_alignment_errors_low[0x20]; 1941 1942 u8 a_octets_transmitted_ok_high[0x20]; 1943 1944 u8 a_octets_transmitted_ok_low[0x20]; 1945 1946 u8 a_octets_received_ok_high[0x20]; 1947 1948 u8 a_octets_received_ok_low[0x20]; 1949 1950 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1951 1952 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1953 1954 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1955 1956 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1957 1958 u8 a_multicast_frames_received_ok_high[0x20]; 1959 1960 u8 a_multicast_frames_received_ok_low[0x20]; 1961 1962 u8 a_broadcast_frames_received_ok_high[0x20]; 1963 1964 u8 a_broadcast_frames_received_ok_low[0x20]; 1965 1966 u8 a_in_range_length_errors_high[0x20]; 1967 1968 u8 a_in_range_length_errors_low[0x20]; 1969 1970 u8 a_out_of_range_length_field_high[0x20]; 1971 1972 u8 a_out_of_range_length_field_low[0x20]; 1973 1974 u8 a_frame_too_long_errors_high[0x20]; 1975 1976 u8 a_frame_too_long_errors_low[0x20]; 1977 1978 u8 a_symbol_error_during_carrier_high[0x20]; 1979 1980 u8 a_symbol_error_during_carrier_low[0x20]; 1981 1982 u8 a_mac_control_frames_transmitted_high[0x20]; 1983 1984 u8 a_mac_control_frames_transmitted_low[0x20]; 1985 1986 u8 a_mac_control_frames_received_high[0x20]; 1987 1988 u8 a_mac_control_frames_received_low[0x20]; 1989 1990 u8 a_unsupported_opcodes_received_high[0x20]; 1991 1992 u8 a_unsupported_opcodes_received_low[0x20]; 1993 1994 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1995 1996 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1997 1998 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1999 2000 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2001 2002 u8 reserved_at_4c0[0x300]; 2003 }; 2004 2005 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2006 u8 life_time_counter_high[0x20]; 2007 2008 u8 life_time_counter_low[0x20]; 2009 2010 u8 rx_errors[0x20]; 2011 2012 u8 tx_errors[0x20]; 2013 2014 u8 l0_to_recovery_eieos[0x20]; 2015 2016 u8 l0_to_recovery_ts[0x20]; 2017 2018 u8 l0_to_recovery_framing[0x20]; 2019 2020 u8 l0_to_recovery_retrain[0x20]; 2021 2022 u8 crc_error_dllp[0x20]; 2023 2024 u8 crc_error_tlp[0x20]; 2025 2026 u8 tx_overflow_buffer_pkt_high[0x20]; 2027 2028 u8 tx_overflow_buffer_pkt_low[0x20]; 2029 2030 u8 outbound_stalled_reads[0x20]; 2031 2032 u8 outbound_stalled_writes[0x20]; 2033 2034 u8 outbound_stalled_reads_events[0x20]; 2035 2036 u8 outbound_stalled_writes_events[0x20]; 2037 2038 u8 reserved_at_200[0x5c0]; 2039 }; 2040 2041 struct mlx5_ifc_cmd_inter_comp_event_bits { 2042 u8 command_completion_vector[0x20]; 2043 2044 u8 reserved_at_20[0xc0]; 2045 }; 2046 2047 struct mlx5_ifc_stall_vl_event_bits { 2048 u8 reserved_at_0[0x18]; 2049 u8 port_num[0x1]; 2050 u8 reserved_at_19[0x3]; 2051 u8 vl[0x4]; 2052 2053 u8 reserved_at_20[0xa0]; 2054 }; 2055 2056 struct mlx5_ifc_db_bf_congestion_event_bits { 2057 u8 event_subtype[0x8]; 2058 u8 reserved_at_8[0x8]; 2059 u8 congestion_level[0x8]; 2060 u8 reserved_at_18[0x8]; 2061 2062 u8 reserved_at_20[0xa0]; 2063 }; 2064 2065 struct mlx5_ifc_gpio_event_bits { 2066 u8 reserved_at_0[0x60]; 2067 2068 u8 gpio_event_hi[0x20]; 2069 2070 u8 gpio_event_lo[0x20]; 2071 2072 u8 reserved_at_a0[0x40]; 2073 }; 2074 2075 struct mlx5_ifc_port_state_change_event_bits { 2076 u8 reserved_at_0[0x40]; 2077 2078 u8 port_num[0x4]; 2079 u8 reserved_at_44[0x1c]; 2080 2081 u8 reserved_at_60[0x80]; 2082 }; 2083 2084 struct mlx5_ifc_dropped_packet_logged_bits { 2085 u8 reserved_at_0[0xe0]; 2086 }; 2087 2088 enum { 2089 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2090 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2091 }; 2092 2093 struct mlx5_ifc_cq_error_bits { 2094 u8 reserved_at_0[0x8]; 2095 u8 cqn[0x18]; 2096 2097 u8 reserved_at_20[0x20]; 2098 2099 u8 reserved_at_40[0x18]; 2100 u8 syndrome[0x8]; 2101 2102 u8 reserved_at_60[0x80]; 2103 }; 2104 2105 struct mlx5_ifc_rdma_page_fault_event_bits { 2106 u8 bytes_committed[0x20]; 2107 2108 u8 r_key[0x20]; 2109 2110 u8 reserved_at_40[0x10]; 2111 u8 packet_len[0x10]; 2112 2113 u8 rdma_op_len[0x20]; 2114 2115 u8 rdma_va[0x40]; 2116 2117 u8 reserved_at_c0[0x5]; 2118 u8 rdma[0x1]; 2119 u8 write[0x1]; 2120 u8 requestor[0x1]; 2121 u8 qp_number[0x18]; 2122 }; 2123 2124 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2125 u8 bytes_committed[0x20]; 2126 2127 u8 reserved_at_20[0x10]; 2128 u8 wqe_index[0x10]; 2129 2130 u8 reserved_at_40[0x10]; 2131 u8 len[0x10]; 2132 2133 u8 reserved_at_60[0x60]; 2134 2135 u8 reserved_at_c0[0x5]; 2136 u8 rdma[0x1]; 2137 u8 write_read[0x1]; 2138 u8 requestor[0x1]; 2139 u8 qpn[0x18]; 2140 }; 2141 2142 struct mlx5_ifc_qp_events_bits { 2143 u8 reserved_at_0[0xa0]; 2144 2145 u8 type[0x8]; 2146 u8 reserved_at_a8[0x18]; 2147 2148 u8 reserved_at_c0[0x8]; 2149 u8 qpn_rqn_sqn[0x18]; 2150 }; 2151 2152 struct mlx5_ifc_dct_events_bits { 2153 u8 reserved_at_0[0xc0]; 2154 2155 u8 reserved_at_c0[0x8]; 2156 u8 dct_number[0x18]; 2157 }; 2158 2159 struct mlx5_ifc_comp_event_bits { 2160 u8 reserved_at_0[0xc0]; 2161 2162 u8 reserved_at_c0[0x8]; 2163 u8 cq_number[0x18]; 2164 }; 2165 2166 enum { 2167 MLX5_QPC_STATE_RST = 0x0, 2168 MLX5_QPC_STATE_INIT = 0x1, 2169 MLX5_QPC_STATE_RTR = 0x2, 2170 MLX5_QPC_STATE_RTS = 0x3, 2171 MLX5_QPC_STATE_SQER = 0x4, 2172 MLX5_QPC_STATE_ERR = 0x6, 2173 MLX5_QPC_STATE_SQD = 0x7, 2174 MLX5_QPC_STATE_SUSPENDED = 0x9, 2175 }; 2176 2177 enum { 2178 MLX5_QPC_ST_RC = 0x0, 2179 MLX5_QPC_ST_UC = 0x1, 2180 MLX5_QPC_ST_UD = 0x2, 2181 MLX5_QPC_ST_XRC = 0x3, 2182 MLX5_QPC_ST_DCI = 0x5, 2183 MLX5_QPC_ST_QP0 = 0x7, 2184 MLX5_QPC_ST_QP1 = 0x8, 2185 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2186 MLX5_QPC_ST_REG_UMR = 0xc, 2187 }; 2188 2189 enum { 2190 MLX5_QPC_PM_STATE_ARMED = 0x0, 2191 MLX5_QPC_PM_STATE_REARM = 0x1, 2192 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2193 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2194 }; 2195 2196 enum { 2197 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2198 }; 2199 2200 enum { 2201 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2202 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2203 }; 2204 2205 enum { 2206 MLX5_QPC_MTU_256_BYTES = 0x1, 2207 MLX5_QPC_MTU_512_BYTES = 0x2, 2208 MLX5_QPC_MTU_1K_BYTES = 0x3, 2209 MLX5_QPC_MTU_2K_BYTES = 0x4, 2210 MLX5_QPC_MTU_4K_BYTES = 0x5, 2211 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2212 }; 2213 2214 enum { 2215 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2216 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2217 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2218 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2219 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2220 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2221 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2222 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2223 }; 2224 2225 enum { 2226 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2227 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2228 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2229 }; 2230 2231 enum { 2232 MLX5_QPC_CS_RES_DISABLE = 0x0, 2233 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2234 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2235 }; 2236 2237 struct mlx5_ifc_qpc_bits { 2238 u8 state[0x4]; 2239 u8 lag_tx_port_affinity[0x4]; 2240 u8 st[0x8]; 2241 u8 reserved_at_10[0x3]; 2242 u8 pm_state[0x2]; 2243 u8 reserved_at_15[0x3]; 2244 u8 offload_type[0x4]; 2245 u8 end_padding_mode[0x2]; 2246 u8 reserved_at_1e[0x2]; 2247 2248 u8 wq_signature[0x1]; 2249 u8 block_lb_mc[0x1]; 2250 u8 atomic_like_write_en[0x1]; 2251 u8 latency_sensitive[0x1]; 2252 u8 reserved_at_24[0x1]; 2253 u8 drain_sigerr[0x1]; 2254 u8 reserved_at_26[0x2]; 2255 u8 pd[0x18]; 2256 2257 u8 mtu[0x3]; 2258 u8 log_msg_max[0x5]; 2259 u8 reserved_at_48[0x1]; 2260 u8 log_rq_size[0x4]; 2261 u8 log_rq_stride[0x3]; 2262 u8 no_sq[0x1]; 2263 u8 log_sq_size[0x4]; 2264 u8 reserved_at_55[0x6]; 2265 u8 rlky[0x1]; 2266 u8 ulp_stateless_offload_mode[0x4]; 2267 2268 u8 counter_set_id[0x8]; 2269 u8 uar_page[0x18]; 2270 2271 u8 reserved_at_80[0x8]; 2272 u8 user_index[0x18]; 2273 2274 u8 reserved_at_a0[0x3]; 2275 u8 log_page_size[0x5]; 2276 u8 remote_qpn[0x18]; 2277 2278 struct mlx5_ifc_ads_bits primary_address_path; 2279 2280 struct mlx5_ifc_ads_bits secondary_address_path; 2281 2282 u8 log_ack_req_freq[0x4]; 2283 u8 reserved_at_384[0x4]; 2284 u8 log_sra_max[0x3]; 2285 u8 reserved_at_38b[0x2]; 2286 u8 retry_count[0x3]; 2287 u8 rnr_retry[0x3]; 2288 u8 reserved_at_393[0x1]; 2289 u8 fre[0x1]; 2290 u8 cur_rnr_retry[0x3]; 2291 u8 cur_retry_count[0x3]; 2292 u8 reserved_at_39b[0x5]; 2293 2294 u8 reserved_at_3a0[0x20]; 2295 2296 u8 reserved_at_3c0[0x8]; 2297 u8 next_send_psn[0x18]; 2298 2299 u8 reserved_at_3e0[0x8]; 2300 u8 cqn_snd[0x18]; 2301 2302 u8 reserved_at_400[0x8]; 2303 u8 deth_sqpn[0x18]; 2304 2305 u8 reserved_at_420[0x20]; 2306 2307 u8 reserved_at_440[0x8]; 2308 u8 last_acked_psn[0x18]; 2309 2310 u8 reserved_at_460[0x8]; 2311 u8 ssn[0x18]; 2312 2313 u8 reserved_at_480[0x8]; 2314 u8 log_rra_max[0x3]; 2315 u8 reserved_at_48b[0x1]; 2316 u8 atomic_mode[0x4]; 2317 u8 rre[0x1]; 2318 u8 rwe[0x1]; 2319 u8 rae[0x1]; 2320 u8 reserved_at_493[0x1]; 2321 u8 page_offset[0x6]; 2322 u8 reserved_at_49a[0x3]; 2323 u8 cd_slave_receive[0x1]; 2324 u8 cd_slave_send[0x1]; 2325 u8 cd_master[0x1]; 2326 2327 u8 reserved_at_4a0[0x3]; 2328 u8 min_rnr_nak[0x5]; 2329 u8 next_rcv_psn[0x18]; 2330 2331 u8 reserved_at_4c0[0x8]; 2332 u8 xrcd[0x18]; 2333 2334 u8 reserved_at_4e0[0x8]; 2335 u8 cqn_rcv[0x18]; 2336 2337 u8 dbr_addr[0x40]; 2338 2339 u8 q_key[0x20]; 2340 2341 u8 reserved_at_560[0x5]; 2342 u8 rq_type[0x3]; 2343 u8 srqn_rmpn_xrqn[0x18]; 2344 2345 u8 reserved_at_580[0x8]; 2346 u8 rmsn[0x18]; 2347 2348 u8 hw_sq_wqebb_counter[0x10]; 2349 u8 sw_sq_wqebb_counter[0x10]; 2350 2351 u8 hw_rq_counter[0x20]; 2352 2353 u8 sw_rq_counter[0x20]; 2354 2355 u8 reserved_at_600[0x20]; 2356 2357 u8 reserved_at_620[0xf]; 2358 u8 cgs[0x1]; 2359 u8 cs_req[0x8]; 2360 u8 cs_res[0x8]; 2361 2362 u8 dc_access_key[0x40]; 2363 2364 u8 reserved_at_680[0xc0]; 2365 }; 2366 2367 struct mlx5_ifc_roce_addr_layout_bits { 2368 u8 source_l3_address[16][0x8]; 2369 2370 u8 reserved_at_80[0x3]; 2371 u8 vlan_valid[0x1]; 2372 u8 vlan_id[0xc]; 2373 u8 source_mac_47_32[0x10]; 2374 2375 u8 source_mac_31_0[0x20]; 2376 2377 u8 reserved_at_c0[0x14]; 2378 u8 roce_l3_type[0x4]; 2379 u8 roce_version[0x8]; 2380 2381 u8 reserved_at_e0[0x20]; 2382 }; 2383 2384 union mlx5_ifc_hca_cap_union_bits { 2385 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2386 struct mlx5_ifc_odp_cap_bits odp_cap; 2387 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2388 struct mlx5_ifc_roce_cap_bits roce_cap; 2389 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2390 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2391 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2392 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2393 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2394 struct mlx5_ifc_qos_cap_bits qos_cap; 2395 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2396 u8 reserved_at_0[0x8000]; 2397 }; 2398 2399 enum { 2400 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2401 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2402 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2403 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2404 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2405 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2406 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2407 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2408 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2409 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2410 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2411 }; 2412 2413 struct mlx5_ifc_vlan_bits { 2414 u8 ethtype[0x10]; 2415 u8 prio[0x3]; 2416 u8 cfi[0x1]; 2417 u8 vid[0xc]; 2418 }; 2419 2420 struct mlx5_ifc_flow_context_bits { 2421 struct mlx5_ifc_vlan_bits push_vlan; 2422 2423 u8 group_id[0x20]; 2424 2425 u8 reserved_at_40[0x8]; 2426 u8 flow_tag[0x18]; 2427 2428 u8 reserved_at_60[0x10]; 2429 u8 action[0x10]; 2430 2431 u8 reserved_at_80[0x8]; 2432 u8 destination_list_size[0x18]; 2433 2434 u8 reserved_at_a0[0x8]; 2435 u8 flow_counter_list_size[0x18]; 2436 2437 u8 encap_id[0x20]; 2438 2439 u8 modify_header_id[0x20]; 2440 2441 struct mlx5_ifc_vlan_bits push_vlan_2; 2442 2443 u8 reserved_at_120[0xe0]; 2444 2445 struct mlx5_ifc_fte_match_param_bits match_value; 2446 2447 u8 reserved_at_1200[0x600]; 2448 2449 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2450 }; 2451 2452 enum { 2453 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2454 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2455 }; 2456 2457 struct mlx5_ifc_xrc_srqc_bits { 2458 u8 state[0x4]; 2459 u8 log_xrc_srq_size[0x4]; 2460 u8 reserved_at_8[0x18]; 2461 2462 u8 wq_signature[0x1]; 2463 u8 cont_srq[0x1]; 2464 u8 reserved_at_22[0x1]; 2465 u8 rlky[0x1]; 2466 u8 basic_cyclic_rcv_wqe[0x1]; 2467 u8 log_rq_stride[0x3]; 2468 u8 xrcd[0x18]; 2469 2470 u8 page_offset[0x6]; 2471 u8 reserved_at_46[0x2]; 2472 u8 cqn[0x18]; 2473 2474 u8 reserved_at_60[0x20]; 2475 2476 u8 user_index_equal_xrc_srqn[0x1]; 2477 u8 reserved_at_81[0x1]; 2478 u8 log_page_size[0x6]; 2479 u8 user_index[0x18]; 2480 2481 u8 reserved_at_a0[0x20]; 2482 2483 u8 reserved_at_c0[0x8]; 2484 u8 pd[0x18]; 2485 2486 u8 lwm[0x10]; 2487 u8 wqe_cnt[0x10]; 2488 2489 u8 reserved_at_100[0x40]; 2490 2491 u8 db_record_addr_h[0x20]; 2492 2493 u8 db_record_addr_l[0x1e]; 2494 u8 reserved_at_17e[0x2]; 2495 2496 u8 reserved_at_180[0x80]; 2497 }; 2498 2499 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2500 u8 counter_error_queues[0x20]; 2501 2502 u8 total_error_queues[0x20]; 2503 2504 u8 send_queue_priority_update_flow[0x20]; 2505 2506 u8 reserved_at_60[0x20]; 2507 2508 u8 nic_receive_steering_discard[0x40]; 2509 2510 u8 receive_discard_vport_down[0x40]; 2511 2512 u8 transmit_discard_vport_down[0x40]; 2513 2514 u8 reserved_at_140[0xec0]; 2515 }; 2516 2517 struct mlx5_ifc_traffic_counter_bits { 2518 u8 packets[0x40]; 2519 2520 u8 octets[0x40]; 2521 }; 2522 2523 struct mlx5_ifc_tisc_bits { 2524 u8 strict_lag_tx_port_affinity[0x1]; 2525 u8 reserved_at_1[0x3]; 2526 u8 lag_tx_port_affinity[0x04]; 2527 2528 u8 reserved_at_8[0x4]; 2529 u8 prio[0x4]; 2530 u8 reserved_at_10[0x10]; 2531 2532 u8 reserved_at_20[0x100]; 2533 2534 u8 reserved_at_120[0x8]; 2535 u8 transport_domain[0x18]; 2536 2537 u8 reserved_at_140[0x8]; 2538 u8 underlay_qpn[0x18]; 2539 u8 reserved_at_160[0x3a0]; 2540 }; 2541 2542 enum { 2543 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2544 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2545 }; 2546 2547 enum { 2548 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2549 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2550 }; 2551 2552 enum { 2553 MLX5_RX_HASH_FN_NONE = 0x0, 2554 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2555 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2556 }; 2557 2558 enum { 2559 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2560 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2561 }; 2562 2563 struct mlx5_ifc_tirc_bits { 2564 u8 reserved_at_0[0x20]; 2565 2566 u8 disp_type[0x4]; 2567 u8 reserved_at_24[0x1c]; 2568 2569 u8 reserved_at_40[0x40]; 2570 2571 u8 reserved_at_80[0x4]; 2572 u8 lro_timeout_period_usecs[0x10]; 2573 u8 lro_enable_mask[0x4]; 2574 u8 lro_max_ip_payload_size[0x8]; 2575 2576 u8 reserved_at_a0[0x40]; 2577 2578 u8 reserved_at_e0[0x8]; 2579 u8 inline_rqn[0x18]; 2580 2581 u8 rx_hash_symmetric[0x1]; 2582 u8 reserved_at_101[0x1]; 2583 u8 tunneled_offload_en[0x1]; 2584 u8 reserved_at_103[0x5]; 2585 u8 indirect_table[0x18]; 2586 2587 u8 rx_hash_fn[0x4]; 2588 u8 reserved_at_124[0x2]; 2589 u8 self_lb_block[0x2]; 2590 u8 transport_domain[0x18]; 2591 2592 u8 rx_hash_toeplitz_key[10][0x20]; 2593 2594 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2595 2596 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2597 2598 u8 reserved_at_2c0[0x4c0]; 2599 }; 2600 2601 enum { 2602 MLX5_SRQC_STATE_GOOD = 0x0, 2603 MLX5_SRQC_STATE_ERROR = 0x1, 2604 }; 2605 2606 struct mlx5_ifc_srqc_bits { 2607 u8 state[0x4]; 2608 u8 log_srq_size[0x4]; 2609 u8 reserved_at_8[0x18]; 2610 2611 u8 wq_signature[0x1]; 2612 u8 cont_srq[0x1]; 2613 u8 reserved_at_22[0x1]; 2614 u8 rlky[0x1]; 2615 u8 reserved_at_24[0x1]; 2616 u8 log_rq_stride[0x3]; 2617 u8 xrcd[0x18]; 2618 2619 u8 page_offset[0x6]; 2620 u8 reserved_at_46[0x2]; 2621 u8 cqn[0x18]; 2622 2623 u8 reserved_at_60[0x20]; 2624 2625 u8 reserved_at_80[0x2]; 2626 u8 log_page_size[0x6]; 2627 u8 reserved_at_88[0x18]; 2628 2629 u8 reserved_at_a0[0x20]; 2630 2631 u8 reserved_at_c0[0x8]; 2632 u8 pd[0x18]; 2633 2634 u8 lwm[0x10]; 2635 u8 wqe_cnt[0x10]; 2636 2637 u8 reserved_at_100[0x40]; 2638 2639 u8 dbr_addr[0x40]; 2640 2641 u8 reserved_at_180[0x80]; 2642 }; 2643 2644 enum { 2645 MLX5_SQC_STATE_RST = 0x0, 2646 MLX5_SQC_STATE_RDY = 0x1, 2647 MLX5_SQC_STATE_ERR = 0x3, 2648 }; 2649 2650 struct mlx5_ifc_sqc_bits { 2651 u8 rlky[0x1]; 2652 u8 cd_master[0x1]; 2653 u8 fre[0x1]; 2654 u8 flush_in_error_en[0x1]; 2655 u8 allow_multi_pkt_send_wqe[0x1]; 2656 u8 min_wqe_inline_mode[0x3]; 2657 u8 state[0x4]; 2658 u8 reg_umr[0x1]; 2659 u8 allow_swp[0x1]; 2660 u8 hairpin[0x1]; 2661 u8 reserved_at_f[0x11]; 2662 2663 u8 reserved_at_20[0x8]; 2664 u8 user_index[0x18]; 2665 2666 u8 reserved_at_40[0x8]; 2667 u8 cqn[0x18]; 2668 2669 u8 reserved_at_60[0x8]; 2670 u8 hairpin_peer_rq[0x18]; 2671 2672 u8 reserved_at_80[0x10]; 2673 u8 hairpin_peer_vhca[0x10]; 2674 2675 u8 reserved_at_a0[0x50]; 2676 2677 u8 packet_pacing_rate_limit_index[0x10]; 2678 u8 tis_lst_sz[0x10]; 2679 u8 reserved_at_110[0x10]; 2680 2681 u8 reserved_at_120[0x40]; 2682 2683 u8 reserved_at_160[0x8]; 2684 u8 tis_num_0[0x18]; 2685 2686 struct mlx5_ifc_wq_bits wq; 2687 }; 2688 2689 enum { 2690 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2691 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2692 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2693 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2694 }; 2695 2696 struct mlx5_ifc_scheduling_context_bits { 2697 u8 element_type[0x8]; 2698 u8 reserved_at_8[0x18]; 2699 2700 u8 element_attributes[0x20]; 2701 2702 u8 parent_element_id[0x20]; 2703 2704 u8 reserved_at_60[0x40]; 2705 2706 u8 bw_share[0x20]; 2707 2708 u8 max_average_bw[0x20]; 2709 2710 u8 reserved_at_e0[0x120]; 2711 }; 2712 2713 struct mlx5_ifc_rqtc_bits { 2714 u8 reserved_at_0[0xa0]; 2715 2716 u8 reserved_at_a0[0x10]; 2717 u8 rqt_max_size[0x10]; 2718 2719 u8 reserved_at_c0[0x10]; 2720 u8 rqt_actual_size[0x10]; 2721 2722 u8 reserved_at_e0[0x6a0]; 2723 2724 struct mlx5_ifc_rq_num_bits rq_num[0]; 2725 }; 2726 2727 enum { 2728 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2729 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2730 }; 2731 2732 enum { 2733 MLX5_RQC_STATE_RST = 0x0, 2734 MLX5_RQC_STATE_RDY = 0x1, 2735 MLX5_RQC_STATE_ERR = 0x3, 2736 }; 2737 2738 struct mlx5_ifc_rqc_bits { 2739 u8 rlky[0x1]; 2740 u8 delay_drop_en[0x1]; 2741 u8 scatter_fcs[0x1]; 2742 u8 vsd[0x1]; 2743 u8 mem_rq_type[0x4]; 2744 u8 state[0x4]; 2745 u8 reserved_at_c[0x1]; 2746 u8 flush_in_error_en[0x1]; 2747 u8 hairpin[0x1]; 2748 u8 reserved_at_f[0x11]; 2749 2750 u8 reserved_at_20[0x8]; 2751 u8 user_index[0x18]; 2752 2753 u8 reserved_at_40[0x8]; 2754 u8 cqn[0x18]; 2755 2756 u8 counter_set_id[0x8]; 2757 u8 reserved_at_68[0x18]; 2758 2759 u8 reserved_at_80[0x8]; 2760 u8 rmpn[0x18]; 2761 2762 u8 reserved_at_a0[0x8]; 2763 u8 hairpin_peer_sq[0x18]; 2764 2765 u8 reserved_at_c0[0x10]; 2766 u8 hairpin_peer_vhca[0x10]; 2767 2768 u8 reserved_at_e0[0xa0]; 2769 2770 struct mlx5_ifc_wq_bits wq; 2771 }; 2772 2773 enum { 2774 MLX5_RMPC_STATE_RDY = 0x1, 2775 MLX5_RMPC_STATE_ERR = 0x3, 2776 }; 2777 2778 struct mlx5_ifc_rmpc_bits { 2779 u8 reserved_at_0[0x8]; 2780 u8 state[0x4]; 2781 u8 reserved_at_c[0x14]; 2782 2783 u8 basic_cyclic_rcv_wqe[0x1]; 2784 u8 reserved_at_21[0x1f]; 2785 2786 u8 reserved_at_40[0x140]; 2787 2788 struct mlx5_ifc_wq_bits wq; 2789 }; 2790 2791 struct mlx5_ifc_nic_vport_context_bits { 2792 u8 reserved_at_0[0x5]; 2793 u8 min_wqe_inline_mode[0x3]; 2794 u8 reserved_at_8[0x15]; 2795 u8 disable_mc_local_lb[0x1]; 2796 u8 disable_uc_local_lb[0x1]; 2797 u8 roce_en[0x1]; 2798 2799 u8 arm_change_event[0x1]; 2800 u8 reserved_at_21[0x1a]; 2801 u8 event_on_mtu[0x1]; 2802 u8 event_on_promisc_change[0x1]; 2803 u8 event_on_vlan_change[0x1]; 2804 u8 event_on_mc_address_change[0x1]; 2805 u8 event_on_uc_address_change[0x1]; 2806 2807 u8 reserved_at_40[0xc]; 2808 2809 u8 affiliation_criteria[0x4]; 2810 u8 affiliated_vhca_id[0x10]; 2811 2812 u8 reserved_at_60[0xd0]; 2813 2814 u8 mtu[0x10]; 2815 2816 u8 system_image_guid[0x40]; 2817 u8 port_guid[0x40]; 2818 u8 node_guid[0x40]; 2819 2820 u8 reserved_at_200[0x140]; 2821 u8 qkey_violation_counter[0x10]; 2822 u8 reserved_at_350[0x430]; 2823 2824 u8 promisc_uc[0x1]; 2825 u8 promisc_mc[0x1]; 2826 u8 promisc_all[0x1]; 2827 u8 reserved_at_783[0x2]; 2828 u8 allowed_list_type[0x3]; 2829 u8 reserved_at_788[0xc]; 2830 u8 allowed_list_size[0xc]; 2831 2832 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2833 2834 u8 reserved_at_7e0[0x20]; 2835 2836 u8 current_uc_mac_address[0][0x40]; 2837 }; 2838 2839 enum { 2840 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2841 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2842 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2843 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2844 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2845 }; 2846 2847 struct mlx5_ifc_mkc_bits { 2848 u8 reserved_at_0[0x1]; 2849 u8 free[0x1]; 2850 u8 reserved_at_2[0x1]; 2851 u8 access_mode_4_2[0x3]; 2852 u8 reserved_at_6[0x7]; 2853 u8 relaxed_ordering_write[0x1]; 2854 u8 reserved_at_e[0x1]; 2855 u8 small_fence_on_rdma_read_response[0x1]; 2856 u8 umr_en[0x1]; 2857 u8 a[0x1]; 2858 u8 rw[0x1]; 2859 u8 rr[0x1]; 2860 u8 lw[0x1]; 2861 u8 lr[0x1]; 2862 u8 access_mode_1_0[0x2]; 2863 u8 reserved_at_18[0x8]; 2864 2865 u8 qpn[0x18]; 2866 u8 mkey_7_0[0x8]; 2867 2868 u8 reserved_at_40[0x20]; 2869 2870 u8 length64[0x1]; 2871 u8 bsf_en[0x1]; 2872 u8 sync_umr[0x1]; 2873 u8 reserved_at_63[0x2]; 2874 u8 expected_sigerr_count[0x1]; 2875 u8 reserved_at_66[0x1]; 2876 u8 en_rinval[0x1]; 2877 u8 pd[0x18]; 2878 2879 u8 start_addr[0x40]; 2880 2881 u8 len[0x40]; 2882 2883 u8 bsf_octword_size[0x20]; 2884 2885 u8 reserved_at_120[0x80]; 2886 2887 u8 translations_octword_size[0x20]; 2888 2889 u8 reserved_at_1c0[0x1b]; 2890 u8 log_page_size[0x5]; 2891 2892 u8 reserved_at_1e0[0x20]; 2893 }; 2894 2895 struct mlx5_ifc_pkey_bits { 2896 u8 reserved_at_0[0x10]; 2897 u8 pkey[0x10]; 2898 }; 2899 2900 struct mlx5_ifc_array128_auto_bits { 2901 u8 array128_auto[16][0x8]; 2902 }; 2903 2904 struct mlx5_ifc_hca_vport_context_bits { 2905 u8 field_select[0x20]; 2906 2907 u8 reserved_at_20[0xe0]; 2908 2909 u8 sm_virt_aware[0x1]; 2910 u8 has_smi[0x1]; 2911 u8 has_raw[0x1]; 2912 u8 grh_required[0x1]; 2913 u8 reserved_at_104[0xc]; 2914 u8 port_physical_state[0x4]; 2915 u8 vport_state_policy[0x4]; 2916 u8 port_state[0x4]; 2917 u8 vport_state[0x4]; 2918 2919 u8 reserved_at_120[0x20]; 2920 2921 u8 system_image_guid[0x40]; 2922 2923 u8 port_guid[0x40]; 2924 2925 u8 node_guid[0x40]; 2926 2927 u8 cap_mask1[0x20]; 2928 2929 u8 cap_mask1_field_select[0x20]; 2930 2931 u8 cap_mask2[0x20]; 2932 2933 u8 cap_mask2_field_select[0x20]; 2934 2935 u8 reserved_at_280[0x80]; 2936 2937 u8 lid[0x10]; 2938 u8 reserved_at_310[0x4]; 2939 u8 init_type_reply[0x4]; 2940 u8 lmc[0x3]; 2941 u8 subnet_timeout[0x5]; 2942 2943 u8 sm_lid[0x10]; 2944 u8 sm_sl[0x4]; 2945 u8 reserved_at_334[0xc]; 2946 2947 u8 qkey_violation_counter[0x10]; 2948 u8 pkey_violation_counter[0x10]; 2949 2950 u8 reserved_at_360[0xca0]; 2951 }; 2952 2953 struct mlx5_ifc_esw_vport_context_bits { 2954 u8 reserved_at_0[0x3]; 2955 u8 vport_svlan_strip[0x1]; 2956 u8 vport_cvlan_strip[0x1]; 2957 u8 vport_svlan_insert[0x1]; 2958 u8 vport_cvlan_insert[0x2]; 2959 u8 reserved_at_8[0x18]; 2960 2961 u8 reserved_at_20[0x20]; 2962 2963 u8 svlan_cfi[0x1]; 2964 u8 svlan_pcp[0x3]; 2965 u8 svlan_id[0xc]; 2966 u8 cvlan_cfi[0x1]; 2967 u8 cvlan_pcp[0x3]; 2968 u8 cvlan_id[0xc]; 2969 2970 u8 reserved_at_60[0x7a0]; 2971 }; 2972 2973 enum { 2974 MLX5_EQC_STATUS_OK = 0x0, 2975 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2976 }; 2977 2978 enum { 2979 MLX5_EQC_ST_ARMED = 0x9, 2980 MLX5_EQC_ST_FIRED = 0xa, 2981 }; 2982 2983 struct mlx5_ifc_eqc_bits { 2984 u8 status[0x4]; 2985 u8 reserved_at_4[0x9]; 2986 u8 ec[0x1]; 2987 u8 oi[0x1]; 2988 u8 reserved_at_f[0x5]; 2989 u8 st[0x4]; 2990 u8 reserved_at_18[0x8]; 2991 2992 u8 reserved_at_20[0x20]; 2993 2994 u8 reserved_at_40[0x14]; 2995 u8 page_offset[0x6]; 2996 u8 reserved_at_5a[0x6]; 2997 2998 u8 reserved_at_60[0x3]; 2999 u8 log_eq_size[0x5]; 3000 u8 uar_page[0x18]; 3001 3002 u8 reserved_at_80[0x20]; 3003 3004 u8 reserved_at_a0[0x18]; 3005 u8 intr[0x8]; 3006 3007 u8 reserved_at_c0[0x3]; 3008 u8 log_page_size[0x5]; 3009 u8 reserved_at_c8[0x18]; 3010 3011 u8 reserved_at_e0[0x60]; 3012 3013 u8 reserved_at_140[0x8]; 3014 u8 consumer_counter[0x18]; 3015 3016 u8 reserved_at_160[0x8]; 3017 u8 producer_counter[0x18]; 3018 3019 u8 reserved_at_180[0x80]; 3020 }; 3021 3022 enum { 3023 MLX5_DCTC_STATE_ACTIVE = 0x0, 3024 MLX5_DCTC_STATE_DRAINING = 0x1, 3025 MLX5_DCTC_STATE_DRAINED = 0x2, 3026 }; 3027 3028 enum { 3029 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3030 MLX5_DCTC_CS_RES_NA = 0x1, 3031 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3032 }; 3033 3034 enum { 3035 MLX5_DCTC_MTU_256_BYTES = 0x1, 3036 MLX5_DCTC_MTU_512_BYTES = 0x2, 3037 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3038 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3039 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3040 }; 3041 3042 struct mlx5_ifc_dctc_bits { 3043 u8 reserved_at_0[0x4]; 3044 u8 state[0x4]; 3045 u8 reserved_at_8[0x18]; 3046 3047 u8 reserved_at_20[0x8]; 3048 u8 user_index[0x18]; 3049 3050 u8 reserved_at_40[0x8]; 3051 u8 cqn[0x18]; 3052 3053 u8 counter_set_id[0x8]; 3054 u8 atomic_mode[0x4]; 3055 u8 rre[0x1]; 3056 u8 rwe[0x1]; 3057 u8 rae[0x1]; 3058 u8 atomic_like_write_en[0x1]; 3059 u8 latency_sensitive[0x1]; 3060 u8 rlky[0x1]; 3061 u8 free_ar[0x1]; 3062 u8 reserved_at_73[0xd]; 3063 3064 u8 reserved_at_80[0x8]; 3065 u8 cs_res[0x8]; 3066 u8 reserved_at_90[0x3]; 3067 u8 min_rnr_nak[0x5]; 3068 u8 reserved_at_98[0x8]; 3069 3070 u8 reserved_at_a0[0x8]; 3071 u8 srqn_xrqn[0x18]; 3072 3073 u8 reserved_at_c0[0x8]; 3074 u8 pd[0x18]; 3075 3076 u8 tclass[0x8]; 3077 u8 reserved_at_e8[0x4]; 3078 u8 flow_label[0x14]; 3079 3080 u8 dc_access_key[0x40]; 3081 3082 u8 reserved_at_140[0x5]; 3083 u8 mtu[0x3]; 3084 u8 port[0x8]; 3085 u8 pkey_index[0x10]; 3086 3087 u8 reserved_at_160[0x8]; 3088 u8 my_addr_index[0x8]; 3089 u8 reserved_at_170[0x8]; 3090 u8 hop_limit[0x8]; 3091 3092 u8 dc_access_key_violation_count[0x20]; 3093 3094 u8 reserved_at_1a0[0x14]; 3095 u8 dei_cfi[0x1]; 3096 u8 eth_prio[0x3]; 3097 u8 ecn[0x2]; 3098 u8 dscp[0x6]; 3099 3100 u8 reserved_at_1c0[0x40]; 3101 }; 3102 3103 enum { 3104 MLX5_CQC_STATUS_OK = 0x0, 3105 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3106 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3107 }; 3108 3109 enum { 3110 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3111 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3112 }; 3113 3114 enum { 3115 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3116 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3117 MLX5_CQC_ST_FIRED = 0xa, 3118 }; 3119 3120 enum { 3121 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3122 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3123 MLX5_CQ_PERIOD_NUM_MODES 3124 }; 3125 3126 struct mlx5_ifc_cqc_bits { 3127 u8 status[0x4]; 3128 u8 reserved_at_4[0x4]; 3129 u8 cqe_sz[0x3]; 3130 u8 cc[0x1]; 3131 u8 reserved_at_c[0x1]; 3132 u8 scqe_break_moderation_en[0x1]; 3133 u8 oi[0x1]; 3134 u8 cq_period_mode[0x2]; 3135 u8 cqe_comp_en[0x1]; 3136 u8 mini_cqe_res_format[0x2]; 3137 u8 st[0x4]; 3138 u8 reserved_at_18[0x8]; 3139 3140 u8 reserved_at_20[0x20]; 3141 3142 u8 reserved_at_40[0x14]; 3143 u8 page_offset[0x6]; 3144 u8 reserved_at_5a[0x6]; 3145 3146 u8 reserved_at_60[0x3]; 3147 u8 log_cq_size[0x5]; 3148 u8 uar_page[0x18]; 3149 3150 u8 reserved_at_80[0x4]; 3151 u8 cq_period[0xc]; 3152 u8 cq_max_count[0x10]; 3153 3154 u8 reserved_at_a0[0x18]; 3155 u8 c_eqn[0x8]; 3156 3157 u8 reserved_at_c0[0x3]; 3158 u8 log_page_size[0x5]; 3159 u8 reserved_at_c8[0x18]; 3160 3161 u8 reserved_at_e0[0x20]; 3162 3163 u8 reserved_at_100[0x8]; 3164 u8 last_notified_index[0x18]; 3165 3166 u8 reserved_at_120[0x8]; 3167 u8 last_solicit_index[0x18]; 3168 3169 u8 reserved_at_140[0x8]; 3170 u8 consumer_counter[0x18]; 3171 3172 u8 reserved_at_160[0x8]; 3173 u8 producer_counter[0x18]; 3174 3175 u8 reserved_at_180[0x40]; 3176 3177 u8 dbr_addr[0x40]; 3178 }; 3179 3180 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3181 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3182 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3183 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3184 u8 reserved_at_0[0x800]; 3185 }; 3186 3187 struct mlx5_ifc_query_adapter_param_block_bits { 3188 u8 reserved_at_0[0xc0]; 3189 3190 u8 reserved_at_c0[0x8]; 3191 u8 ieee_vendor_id[0x18]; 3192 3193 u8 reserved_at_e0[0x10]; 3194 u8 vsd_vendor_id[0x10]; 3195 3196 u8 vsd[208][0x8]; 3197 3198 u8 vsd_contd_psid[16][0x8]; 3199 }; 3200 3201 enum { 3202 MLX5_XRQC_STATE_GOOD = 0x0, 3203 MLX5_XRQC_STATE_ERROR = 0x1, 3204 }; 3205 3206 enum { 3207 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3208 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3209 }; 3210 3211 enum { 3212 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3213 }; 3214 3215 struct mlx5_ifc_tag_matching_topology_context_bits { 3216 u8 log_matching_list_sz[0x4]; 3217 u8 reserved_at_4[0xc]; 3218 u8 append_next_index[0x10]; 3219 3220 u8 sw_phase_cnt[0x10]; 3221 u8 hw_phase_cnt[0x10]; 3222 3223 u8 reserved_at_40[0x40]; 3224 }; 3225 3226 struct mlx5_ifc_xrqc_bits { 3227 u8 state[0x4]; 3228 u8 rlkey[0x1]; 3229 u8 reserved_at_5[0xf]; 3230 u8 topology[0x4]; 3231 u8 reserved_at_18[0x4]; 3232 u8 offload[0x4]; 3233 3234 u8 reserved_at_20[0x8]; 3235 u8 user_index[0x18]; 3236 3237 u8 reserved_at_40[0x8]; 3238 u8 cqn[0x18]; 3239 3240 u8 reserved_at_60[0xa0]; 3241 3242 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3243 3244 u8 reserved_at_180[0x280]; 3245 3246 struct mlx5_ifc_wq_bits wq; 3247 }; 3248 3249 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3250 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3251 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3252 u8 reserved_at_0[0x20]; 3253 }; 3254 3255 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3256 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3257 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3258 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3259 u8 reserved_at_0[0x20]; 3260 }; 3261 3262 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3263 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3264 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3265 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3266 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3267 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3268 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3269 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3270 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3271 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3272 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3273 u8 reserved_at_0[0x7c0]; 3274 }; 3275 3276 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3277 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3278 u8 reserved_at_0[0x7c0]; 3279 }; 3280 3281 union mlx5_ifc_event_auto_bits { 3282 struct mlx5_ifc_comp_event_bits comp_event; 3283 struct mlx5_ifc_dct_events_bits dct_events; 3284 struct mlx5_ifc_qp_events_bits qp_events; 3285 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3286 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3287 struct mlx5_ifc_cq_error_bits cq_error; 3288 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3289 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3290 struct mlx5_ifc_gpio_event_bits gpio_event; 3291 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3292 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3293 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3294 u8 reserved_at_0[0xe0]; 3295 }; 3296 3297 struct mlx5_ifc_health_buffer_bits { 3298 u8 reserved_at_0[0x100]; 3299 3300 u8 assert_existptr[0x20]; 3301 3302 u8 assert_callra[0x20]; 3303 3304 u8 reserved_at_140[0x40]; 3305 3306 u8 fw_version[0x20]; 3307 3308 u8 hw_id[0x20]; 3309 3310 u8 reserved_at_1c0[0x20]; 3311 3312 u8 irisc_index[0x8]; 3313 u8 synd[0x8]; 3314 u8 ext_synd[0x10]; 3315 }; 3316 3317 struct mlx5_ifc_register_loopback_control_bits { 3318 u8 no_lb[0x1]; 3319 u8 reserved_at_1[0x7]; 3320 u8 port[0x8]; 3321 u8 reserved_at_10[0x10]; 3322 3323 u8 reserved_at_20[0x60]; 3324 }; 3325 3326 struct mlx5_ifc_vport_tc_element_bits { 3327 u8 traffic_class[0x4]; 3328 u8 reserved_at_4[0xc]; 3329 u8 vport_number[0x10]; 3330 }; 3331 3332 struct mlx5_ifc_vport_element_bits { 3333 u8 reserved_at_0[0x10]; 3334 u8 vport_number[0x10]; 3335 }; 3336 3337 enum { 3338 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3339 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3340 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3341 }; 3342 3343 struct mlx5_ifc_tsar_element_bits { 3344 u8 reserved_at_0[0x8]; 3345 u8 tsar_type[0x8]; 3346 u8 reserved_at_10[0x10]; 3347 }; 3348 3349 enum { 3350 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3351 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3352 }; 3353 3354 struct mlx5_ifc_teardown_hca_out_bits { 3355 u8 status[0x8]; 3356 u8 reserved_at_8[0x18]; 3357 3358 u8 syndrome[0x20]; 3359 3360 u8 reserved_at_40[0x3f]; 3361 3362 u8 force_state[0x1]; 3363 }; 3364 3365 enum { 3366 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3367 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3368 }; 3369 3370 struct mlx5_ifc_teardown_hca_in_bits { 3371 u8 opcode[0x10]; 3372 u8 reserved_at_10[0x10]; 3373 3374 u8 reserved_at_20[0x10]; 3375 u8 op_mod[0x10]; 3376 3377 u8 reserved_at_40[0x10]; 3378 u8 profile[0x10]; 3379 3380 u8 reserved_at_60[0x20]; 3381 }; 3382 3383 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3384 u8 status[0x8]; 3385 u8 reserved_at_8[0x18]; 3386 3387 u8 syndrome[0x20]; 3388 3389 u8 reserved_at_40[0x40]; 3390 }; 3391 3392 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3393 u8 opcode[0x10]; 3394 u8 reserved_at_10[0x10]; 3395 3396 u8 reserved_at_20[0x10]; 3397 u8 op_mod[0x10]; 3398 3399 u8 reserved_at_40[0x8]; 3400 u8 qpn[0x18]; 3401 3402 u8 reserved_at_60[0x20]; 3403 3404 u8 opt_param_mask[0x20]; 3405 3406 u8 reserved_at_a0[0x20]; 3407 3408 struct mlx5_ifc_qpc_bits qpc; 3409 3410 u8 reserved_at_800[0x80]; 3411 }; 3412 3413 struct mlx5_ifc_sqd2rts_qp_out_bits { 3414 u8 status[0x8]; 3415 u8 reserved_at_8[0x18]; 3416 3417 u8 syndrome[0x20]; 3418 3419 u8 reserved_at_40[0x40]; 3420 }; 3421 3422 struct mlx5_ifc_sqd2rts_qp_in_bits { 3423 u8 opcode[0x10]; 3424 u8 reserved_at_10[0x10]; 3425 3426 u8 reserved_at_20[0x10]; 3427 u8 op_mod[0x10]; 3428 3429 u8 reserved_at_40[0x8]; 3430 u8 qpn[0x18]; 3431 3432 u8 reserved_at_60[0x20]; 3433 3434 u8 opt_param_mask[0x20]; 3435 3436 u8 reserved_at_a0[0x20]; 3437 3438 struct mlx5_ifc_qpc_bits qpc; 3439 3440 u8 reserved_at_800[0x80]; 3441 }; 3442 3443 struct mlx5_ifc_set_roce_address_out_bits { 3444 u8 status[0x8]; 3445 u8 reserved_at_8[0x18]; 3446 3447 u8 syndrome[0x20]; 3448 3449 u8 reserved_at_40[0x40]; 3450 }; 3451 3452 struct mlx5_ifc_set_roce_address_in_bits { 3453 u8 opcode[0x10]; 3454 u8 reserved_at_10[0x10]; 3455 3456 u8 reserved_at_20[0x10]; 3457 u8 op_mod[0x10]; 3458 3459 u8 roce_address_index[0x10]; 3460 u8 reserved_at_50[0xc]; 3461 u8 vhca_port_num[0x4]; 3462 3463 u8 reserved_at_60[0x20]; 3464 3465 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3466 }; 3467 3468 struct mlx5_ifc_set_mad_demux_out_bits { 3469 u8 status[0x8]; 3470 u8 reserved_at_8[0x18]; 3471 3472 u8 syndrome[0x20]; 3473 3474 u8 reserved_at_40[0x40]; 3475 }; 3476 3477 enum { 3478 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3479 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3480 }; 3481 3482 struct mlx5_ifc_set_mad_demux_in_bits { 3483 u8 opcode[0x10]; 3484 u8 reserved_at_10[0x10]; 3485 3486 u8 reserved_at_20[0x10]; 3487 u8 op_mod[0x10]; 3488 3489 u8 reserved_at_40[0x20]; 3490 3491 u8 reserved_at_60[0x6]; 3492 u8 demux_mode[0x2]; 3493 u8 reserved_at_68[0x18]; 3494 }; 3495 3496 struct mlx5_ifc_set_l2_table_entry_out_bits { 3497 u8 status[0x8]; 3498 u8 reserved_at_8[0x18]; 3499 3500 u8 syndrome[0x20]; 3501 3502 u8 reserved_at_40[0x40]; 3503 }; 3504 3505 struct mlx5_ifc_set_l2_table_entry_in_bits { 3506 u8 opcode[0x10]; 3507 u8 reserved_at_10[0x10]; 3508 3509 u8 reserved_at_20[0x10]; 3510 u8 op_mod[0x10]; 3511 3512 u8 reserved_at_40[0x60]; 3513 3514 u8 reserved_at_a0[0x8]; 3515 u8 table_index[0x18]; 3516 3517 u8 reserved_at_c0[0x20]; 3518 3519 u8 reserved_at_e0[0x13]; 3520 u8 vlan_valid[0x1]; 3521 u8 vlan[0xc]; 3522 3523 struct mlx5_ifc_mac_address_layout_bits mac_address; 3524 3525 u8 reserved_at_140[0xc0]; 3526 }; 3527 3528 struct mlx5_ifc_set_issi_out_bits { 3529 u8 status[0x8]; 3530 u8 reserved_at_8[0x18]; 3531 3532 u8 syndrome[0x20]; 3533 3534 u8 reserved_at_40[0x40]; 3535 }; 3536 3537 struct mlx5_ifc_set_issi_in_bits { 3538 u8 opcode[0x10]; 3539 u8 reserved_at_10[0x10]; 3540 3541 u8 reserved_at_20[0x10]; 3542 u8 op_mod[0x10]; 3543 3544 u8 reserved_at_40[0x10]; 3545 u8 current_issi[0x10]; 3546 3547 u8 reserved_at_60[0x20]; 3548 }; 3549 3550 struct mlx5_ifc_set_hca_cap_out_bits { 3551 u8 status[0x8]; 3552 u8 reserved_at_8[0x18]; 3553 3554 u8 syndrome[0x20]; 3555 3556 u8 reserved_at_40[0x40]; 3557 }; 3558 3559 struct mlx5_ifc_set_hca_cap_in_bits { 3560 u8 opcode[0x10]; 3561 u8 reserved_at_10[0x10]; 3562 3563 u8 reserved_at_20[0x10]; 3564 u8 op_mod[0x10]; 3565 3566 u8 reserved_at_40[0x40]; 3567 3568 union mlx5_ifc_hca_cap_union_bits capability; 3569 }; 3570 3571 enum { 3572 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3573 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3574 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3575 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3576 }; 3577 3578 struct mlx5_ifc_set_fte_out_bits { 3579 u8 status[0x8]; 3580 u8 reserved_at_8[0x18]; 3581 3582 u8 syndrome[0x20]; 3583 3584 u8 reserved_at_40[0x40]; 3585 }; 3586 3587 struct mlx5_ifc_set_fte_in_bits { 3588 u8 opcode[0x10]; 3589 u8 reserved_at_10[0x10]; 3590 3591 u8 reserved_at_20[0x10]; 3592 u8 op_mod[0x10]; 3593 3594 u8 other_vport[0x1]; 3595 u8 reserved_at_41[0xf]; 3596 u8 vport_number[0x10]; 3597 3598 u8 reserved_at_60[0x20]; 3599 3600 u8 table_type[0x8]; 3601 u8 reserved_at_88[0x18]; 3602 3603 u8 reserved_at_a0[0x8]; 3604 u8 table_id[0x18]; 3605 3606 u8 reserved_at_c0[0x18]; 3607 u8 modify_enable_mask[0x8]; 3608 3609 u8 reserved_at_e0[0x20]; 3610 3611 u8 flow_index[0x20]; 3612 3613 u8 reserved_at_120[0xe0]; 3614 3615 struct mlx5_ifc_flow_context_bits flow_context; 3616 }; 3617 3618 struct mlx5_ifc_rts2rts_qp_out_bits { 3619 u8 status[0x8]; 3620 u8 reserved_at_8[0x18]; 3621 3622 u8 syndrome[0x20]; 3623 3624 u8 reserved_at_40[0x40]; 3625 }; 3626 3627 struct mlx5_ifc_rts2rts_qp_in_bits { 3628 u8 opcode[0x10]; 3629 u8 reserved_at_10[0x10]; 3630 3631 u8 reserved_at_20[0x10]; 3632 u8 op_mod[0x10]; 3633 3634 u8 reserved_at_40[0x8]; 3635 u8 qpn[0x18]; 3636 3637 u8 reserved_at_60[0x20]; 3638 3639 u8 opt_param_mask[0x20]; 3640 3641 u8 reserved_at_a0[0x20]; 3642 3643 struct mlx5_ifc_qpc_bits qpc; 3644 3645 u8 reserved_at_800[0x80]; 3646 }; 3647 3648 struct mlx5_ifc_rtr2rts_qp_out_bits { 3649 u8 status[0x8]; 3650 u8 reserved_at_8[0x18]; 3651 3652 u8 syndrome[0x20]; 3653 3654 u8 reserved_at_40[0x40]; 3655 }; 3656 3657 struct mlx5_ifc_rtr2rts_qp_in_bits { 3658 u8 opcode[0x10]; 3659 u8 reserved_at_10[0x10]; 3660 3661 u8 reserved_at_20[0x10]; 3662 u8 op_mod[0x10]; 3663 3664 u8 reserved_at_40[0x8]; 3665 u8 qpn[0x18]; 3666 3667 u8 reserved_at_60[0x20]; 3668 3669 u8 opt_param_mask[0x20]; 3670 3671 u8 reserved_at_a0[0x20]; 3672 3673 struct mlx5_ifc_qpc_bits qpc; 3674 3675 u8 reserved_at_800[0x80]; 3676 }; 3677 3678 struct mlx5_ifc_rst2init_qp_out_bits { 3679 u8 status[0x8]; 3680 u8 reserved_at_8[0x18]; 3681 3682 u8 syndrome[0x20]; 3683 3684 u8 reserved_at_40[0x40]; 3685 }; 3686 3687 struct mlx5_ifc_rst2init_qp_in_bits { 3688 u8 opcode[0x10]; 3689 u8 reserved_at_10[0x10]; 3690 3691 u8 reserved_at_20[0x10]; 3692 u8 op_mod[0x10]; 3693 3694 u8 reserved_at_40[0x8]; 3695 u8 qpn[0x18]; 3696 3697 u8 reserved_at_60[0x20]; 3698 3699 u8 opt_param_mask[0x20]; 3700 3701 u8 reserved_at_a0[0x20]; 3702 3703 struct mlx5_ifc_qpc_bits qpc; 3704 3705 u8 reserved_at_800[0x80]; 3706 }; 3707 3708 struct mlx5_ifc_query_xrq_out_bits { 3709 u8 status[0x8]; 3710 u8 reserved_at_8[0x18]; 3711 3712 u8 syndrome[0x20]; 3713 3714 u8 reserved_at_40[0x40]; 3715 3716 struct mlx5_ifc_xrqc_bits xrq_context; 3717 }; 3718 3719 struct mlx5_ifc_query_xrq_in_bits { 3720 u8 opcode[0x10]; 3721 u8 reserved_at_10[0x10]; 3722 3723 u8 reserved_at_20[0x10]; 3724 u8 op_mod[0x10]; 3725 3726 u8 reserved_at_40[0x8]; 3727 u8 xrqn[0x18]; 3728 3729 u8 reserved_at_60[0x20]; 3730 }; 3731 3732 struct mlx5_ifc_query_xrc_srq_out_bits { 3733 u8 status[0x8]; 3734 u8 reserved_at_8[0x18]; 3735 3736 u8 syndrome[0x20]; 3737 3738 u8 reserved_at_40[0x40]; 3739 3740 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3741 3742 u8 reserved_at_280[0x600]; 3743 3744 u8 pas[0][0x40]; 3745 }; 3746 3747 struct mlx5_ifc_query_xrc_srq_in_bits { 3748 u8 opcode[0x10]; 3749 u8 reserved_at_10[0x10]; 3750 3751 u8 reserved_at_20[0x10]; 3752 u8 op_mod[0x10]; 3753 3754 u8 reserved_at_40[0x8]; 3755 u8 xrc_srqn[0x18]; 3756 3757 u8 reserved_at_60[0x20]; 3758 }; 3759 3760 enum { 3761 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3762 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3763 }; 3764 3765 struct mlx5_ifc_query_vport_state_out_bits { 3766 u8 status[0x8]; 3767 u8 reserved_at_8[0x18]; 3768 3769 u8 syndrome[0x20]; 3770 3771 u8 reserved_at_40[0x20]; 3772 3773 u8 reserved_at_60[0x18]; 3774 u8 admin_state[0x4]; 3775 u8 state[0x4]; 3776 }; 3777 3778 enum { 3779 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3780 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3781 }; 3782 3783 struct mlx5_ifc_query_vport_state_in_bits { 3784 u8 opcode[0x10]; 3785 u8 reserved_at_10[0x10]; 3786 3787 u8 reserved_at_20[0x10]; 3788 u8 op_mod[0x10]; 3789 3790 u8 other_vport[0x1]; 3791 u8 reserved_at_41[0xf]; 3792 u8 vport_number[0x10]; 3793 3794 u8 reserved_at_60[0x20]; 3795 }; 3796 3797 struct mlx5_ifc_query_vnic_env_out_bits { 3798 u8 status[0x8]; 3799 u8 reserved_at_8[0x18]; 3800 3801 u8 syndrome[0x20]; 3802 3803 u8 reserved_at_40[0x40]; 3804 3805 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3806 }; 3807 3808 enum { 3809 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3810 }; 3811 3812 struct mlx5_ifc_query_vnic_env_in_bits { 3813 u8 opcode[0x10]; 3814 u8 reserved_at_10[0x10]; 3815 3816 u8 reserved_at_20[0x10]; 3817 u8 op_mod[0x10]; 3818 3819 u8 other_vport[0x1]; 3820 u8 reserved_at_41[0xf]; 3821 u8 vport_number[0x10]; 3822 3823 u8 reserved_at_60[0x20]; 3824 }; 3825 3826 struct mlx5_ifc_query_vport_counter_out_bits { 3827 u8 status[0x8]; 3828 u8 reserved_at_8[0x18]; 3829 3830 u8 syndrome[0x20]; 3831 3832 u8 reserved_at_40[0x40]; 3833 3834 struct mlx5_ifc_traffic_counter_bits received_errors; 3835 3836 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3837 3838 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3839 3840 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3841 3842 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3843 3844 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3845 3846 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3847 3848 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3849 3850 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3851 3852 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3853 3854 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3855 3856 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3857 3858 u8 reserved_at_680[0xa00]; 3859 }; 3860 3861 enum { 3862 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3863 }; 3864 3865 struct mlx5_ifc_query_vport_counter_in_bits { 3866 u8 opcode[0x10]; 3867 u8 reserved_at_10[0x10]; 3868 3869 u8 reserved_at_20[0x10]; 3870 u8 op_mod[0x10]; 3871 3872 u8 other_vport[0x1]; 3873 u8 reserved_at_41[0xb]; 3874 u8 port_num[0x4]; 3875 u8 vport_number[0x10]; 3876 3877 u8 reserved_at_60[0x60]; 3878 3879 u8 clear[0x1]; 3880 u8 reserved_at_c1[0x1f]; 3881 3882 u8 reserved_at_e0[0x20]; 3883 }; 3884 3885 struct mlx5_ifc_query_tis_out_bits { 3886 u8 status[0x8]; 3887 u8 reserved_at_8[0x18]; 3888 3889 u8 syndrome[0x20]; 3890 3891 u8 reserved_at_40[0x40]; 3892 3893 struct mlx5_ifc_tisc_bits tis_context; 3894 }; 3895 3896 struct mlx5_ifc_query_tis_in_bits { 3897 u8 opcode[0x10]; 3898 u8 reserved_at_10[0x10]; 3899 3900 u8 reserved_at_20[0x10]; 3901 u8 op_mod[0x10]; 3902 3903 u8 reserved_at_40[0x8]; 3904 u8 tisn[0x18]; 3905 3906 u8 reserved_at_60[0x20]; 3907 }; 3908 3909 struct mlx5_ifc_query_tir_out_bits { 3910 u8 status[0x8]; 3911 u8 reserved_at_8[0x18]; 3912 3913 u8 syndrome[0x20]; 3914 3915 u8 reserved_at_40[0xc0]; 3916 3917 struct mlx5_ifc_tirc_bits tir_context; 3918 }; 3919 3920 struct mlx5_ifc_query_tir_in_bits { 3921 u8 opcode[0x10]; 3922 u8 reserved_at_10[0x10]; 3923 3924 u8 reserved_at_20[0x10]; 3925 u8 op_mod[0x10]; 3926 3927 u8 reserved_at_40[0x8]; 3928 u8 tirn[0x18]; 3929 3930 u8 reserved_at_60[0x20]; 3931 }; 3932 3933 struct mlx5_ifc_query_srq_out_bits { 3934 u8 status[0x8]; 3935 u8 reserved_at_8[0x18]; 3936 3937 u8 syndrome[0x20]; 3938 3939 u8 reserved_at_40[0x40]; 3940 3941 struct mlx5_ifc_srqc_bits srq_context_entry; 3942 3943 u8 reserved_at_280[0x600]; 3944 3945 u8 pas[0][0x40]; 3946 }; 3947 3948 struct mlx5_ifc_query_srq_in_bits { 3949 u8 opcode[0x10]; 3950 u8 reserved_at_10[0x10]; 3951 3952 u8 reserved_at_20[0x10]; 3953 u8 op_mod[0x10]; 3954 3955 u8 reserved_at_40[0x8]; 3956 u8 srqn[0x18]; 3957 3958 u8 reserved_at_60[0x20]; 3959 }; 3960 3961 struct mlx5_ifc_query_sq_out_bits { 3962 u8 status[0x8]; 3963 u8 reserved_at_8[0x18]; 3964 3965 u8 syndrome[0x20]; 3966 3967 u8 reserved_at_40[0xc0]; 3968 3969 struct mlx5_ifc_sqc_bits sq_context; 3970 }; 3971 3972 struct mlx5_ifc_query_sq_in_bits { 3973 u8 opcode[0x10]; 3974 u8 reserved_at_10[0x10]; 3975 3976 u8 reserved_at_20[0x10]; 3977 u8 op_mod[0x10]; 3978 3979 u8 reserved_at_40[0x8]; 3980 u8 sqn[0x18]; 3981 3982 u8 reserved_at_60[0x20]; 3983 }; 3984 3985 struct mlx5_ifc_query_special_contexts_out_bits { 3986 u8 status[0x8]; 3987 u8 reserved_at_8[0x18]; 3988 3989 u8 syndrome[0x20]; 3990 3991 u8 dump_fill_mkey[0x20]; 3992 3993 u8 resd_lkey[0x20]; 3994 3995 u8 null_mkey[0x20]; 3996 3997 u8 reserved_at_a0[0x60]; 3998 }; 3999 4000 struct mlx5_ifc_query_special_contexts_in_bits { 4001 u8 opcode[0x10]; 4002 u8 reserved_at_10[0x10]; 4003 4004 u8 reserved_at_20[0x10]; 4005 u8 op_mod[0x10]; 4006 4007 u8 reserved_at_40[0x40]; 4008 }; 4009 4010 struct mlx5_ifc_query_scheduling_element_out_bits { 4011 u8 opcode[0x10]; 4012 u8 reserved_at_10[0x10]; 4013 4014 u8 reserved_at_20[0x10]; 4015 u8 op_mod[0x10]; 4016 4017 u8 reserved_at_40[0xc0]; 4018 4019 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4020 4021 u8 reserved_at_300[0x100]; 4022 }; 4023 4024 enum { 4025 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4026 }; 4027 4028 struct mlx5_ifc_query_scheduling_element_in_bits { 4029 u8 opcode[0x10]; 4030 u8 reserved_at_10[0x10]; 4031 4032 u8 reserved_at_20[0x10]; 4033 u8 op_mod[0x10]; 4034 4035 u8 scheduling_hierarchy[0x8]; 4036 u8 reserved_at_48[0x18]; 4037 4038 u8 scheduling_element_id[0x20]; 4039 4040 u8 reserved_at_80[0x180]; 4041 }; 4042 4043 struct mlx5_ifc_query_rqt_out_bits { 4044 u8 status[0x8]; 4045 u8 reserved_at_8[0x18]; 4046 4047 u8 syndrome[0x20]; 4048 4049 u8 reserved_at_40[0xc0]; 4050 4051 struct mlx5_ifc_rqtc_bits rqt_context; 4052 }; 4053 4054 struct mlx5_ifc_query_rqt_in_bits { 4055 u8 opcode[0x10]; 4056 u8 reserved_at_10[0x10]; 4057 4058 u8 reserved_at_20[0x10]; 4059 u8 op_mod[0x10]; 4060 4061 u8 reserved_at_40[0x8]; 4062 u8 rqtn[0x18]; 4063 4064 u8 reserved_at_60[0x20]; 4065 }; 4066 4067 struct mlx5_ifc_query_rq_out_bits { 4068 u8 status[0x8]; 4069 u8 reserved_at_8[0x18]; 4070 4071 u8 syndrome[0x20]; 4072 4073 u8 reserved_at_40[0xc0]; 4074 4075 struct mlx5_ifc_rqc_bits rq_context; 4076 }; 4077 4078 struct mlx5_ifc_query_rq_in_bits { 4079 u8 opcode[0x10]; 4080 u8 reserved_at_10[0x10]; 4081 4082 u8 reserved_at_20[0x10]; 4083 u8 op_mod[0x10]; 4084 4085 u8 reserved_at_40[0x8]; 4086 u8 rqn[0x18]; 4087 4088 u8 reserved_at_60[0x20]; 4089 }; 4090 4091 struct mlx5_ifc_query_roce_address_out_bits { 4092 u8 status[0x8]; 4093 u8 reserved_at_8[0x18]; 4094 4095 u8 syndrome[0x20]; 4096 4097 u8 reserved_at_40[0x40]; 4098 4099 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4100 }; 4101 4102 struct mlx5_ifc_query_roce_address_in_bits { 4103 u8 opcode[0x10]; 4104 u8 reserved_at_10[0x10]; 4105 4106 u8 reserved_at_20[0x10]; 4107 u8 op_mod[0x10]; 4108 4109 u8 roce_address_index[0x10]; 4110 u8 reserved_at_50[0xc]; 4111 u8 vhca_port_num[0x4]; 4112 4113 u8 reserved_at_60[0x20]; 4114 }; 4115 4116 struct mlx5_ifc_query_rmp_out_bits { 4117 u8 status[0x8]; 4118 u8 reserved_at_8[0x18]; 4119 4120 u8 syndrome[0x20]; 4121 4122 u8 reserved_at_40[0xc0]; 4123 4124 struct mlx5_ifc_rmpc_bits rmp_context; 4125 }; 4126 4127 struct mlx5_ifc_query_rmp_in_bits { 4128 u8 opcode[0x10]; 4129 u8 reserved_at_10[0x10]; 4130 4131 u8 reserved_at_20[0x10]; 4132 u8 op_mod[0x10]; 4133 4134 u8 reserved_at_40[0x8]; 4135 u8 rmpn[0x18]; 4136 4137 u8 reserved_at_60[0x20]; 4138 }; 4139 4140 struct mlx5_ifc_query_qp_out_bits { 4141 u8 status[0x8]; 4142 u8 reserved_at_8[0x18]; 4143 4144 u8 syndrome[0x20]; 4145 4146 u8 reserved_at_40[0x40]; 4147 4148 u8 opt_param_mask[0x20]; 4149 4150 u8 reserved_at_a0[0x20]; 4151 4152 struct mlx5_ifc_qpc_bits qpc; 4153 4154 u8 reserved_at_800[0x80]; 4155 4156 u8 pas[0][0x40]; 4157 }; 4158 4159 struct mlx5_ifc_query_qp_in_bits { 4160 u8 opcode[0x10]; 4161 u8 reserved_at_10[0x10]; 4162 4163 u8 reserved_at_20[0x10]; 4164 u8 op_mod[0x10]; 4165 4166 u8 reserved_at_40[0x8]; 4167 u8 qpn[0x18]; 4168 4169 u8 reserved_at_60[0x20]; 4170 }; 4171 4172 struct mlx5_ifc_query_q_counter_out_bits { 4173 u8 status[0x8]; 4174 u8 reserved_at_8[0x18]; 4175 4176 u8 syndrome[0x20]; 4177 4178 u8 reserved_at_40[0x40]; 4179 4180 u8 rx_write_requests[0x20]; 4181 4182 u8 reserved_at_a0[0x20]; 4183 4184 u8 rx_read_requests[0x20]; 4185 4186 u8 reserved_at_e0[0x20]; 4187 4188 u8 rx_atomic_requests[0x20]; 4189 4190 u8 reserved_at_120[0x20]; 4191 4192 u8 rx_dct_connect[0x20]; 4193 4194 u8 reserved_at_160[0x20]; 4195 4196 u8 out_of_buffer[0x20]; 4197 4198 u8 reserved_at_1a0[0x20]; 4199 4200 u8 out_of_sequence[0x20]; 4201 4202 u8 reserved_at_1e0[0x20]; 4203 4204 u8 duplicate_request[0x20]; 4205 4206 u8 reserved_at_220[0x20]; 4207 4208 u8 rnr_nak_retry_err[0x20]; 4209 4210 u8 reserved_at_260[0x20]; 4211 4212 u8 packet_seq_err[0x20]; 4213 4214 u8 reserved_at_2a0[0x20]; 4215 4216 u8 implied_nak_seq_err[0x20]; 4217 4218 u8 reserved_at_2e0[0x20]; 4219 4220 u8 local_ack_timeout_err[0x20]; 4221 4222 u8 reserved_at_320[0xa0]; 4223 4224 u8 resp_local_length_error[0x20]; 4225 4226 u8 req_local_length_error[0x20]; 4227 4228 u8 resp_local_qp_error[0x20]; 4229 4230 u8 local_operation_error[0x20]; 4231 4232 u8 resp_local_protection[0x20]; 4233 4234 u8 req_local_protection[0x20]; 4235 4236 u8 resp_cqe_error[0x20]; 4237 4238 u8 req_cqe_error[0x20]; 4239 4240 u8 req_mw_binding[0x20]; 4241 4242 u8 req_bad_response[0x20]; 4243 4244 u8 req_remote_invalid_request[0x20]; 4245 4246 u8 resp_remote_invalid_request[0x20]; 4247 4248 u8 req_remote_access_errors[0x20]; 4249 4250 u8 resp_remote_access_errors[0x20]; 4251 4252 u8 req_remote_operation_errors[0x20]; 4253 4254 u8 req_transport_retries_exceeded[0x20]; 4255 4256 u8 cq_overflow[0x20]; 4257 4258 u8 resp_cqe_flush_error[0x20]; 4259 4260 u8 req_cqe_flush_error[0x20]; 4261 4262 u8 reserved_at_620[0x1e0]; 4263 }; 4264 4265 struct mlx5_ifc_query_q_counter_in_bits { 4266 u8 opcode[0x10]; 4267 u8 reserved_at_10[0x10]; 4268 4269 u8 reserved_at_20[0x10]; 4270 u8 op_mod[0x10]; 4271 4272 u8 reserved_at_40[0x80]; 4273 4274 u8 clear[0x1]; 4275 u8 reserved_at_c1[0x1f]; 4276 4277 u8 reserved_at_e0[0x18]; 4278 u8 counter_set_id[0x8]; 4279 }; 4280 4281 struct mlx5_ifc_query_pages_out_bits { 4282 u8 status[0x8]; 4283 u8 reserved_at_8[0x18]; 4284 4285 u8 syndrome[0x20]; 4286 4287 u8 reserved_at_40[0x10]; 4288 u8 function_id[0x10]; 4289 4290 u8 num_pages[0x20]; 4291 }; 4292 4293 enum { 4294 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4295 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4296 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4297 }; 4298 4299 struct mlx5_ifc_query_pages_in_bits { 4300 u8 opcode[0x10]; 4301 u8 reserved_at_10[0x10]; 4302 4303 u8 reserved_at_20[0x10]; 4304 u8 op_mod[0x10]; 4305 4306 u8 reserved_at_40[0x10]; 4307 u8 function_id[0x10]; 4308 4309 u8 reserved_at_60[0x20]; 4310 }; 4311 4312 struct mlx5_ifc_query_nic_vport_context_out_bits { 4313 u8 status[0x8]; 4314 u8 reserved_at_8[0x18]; 4315 4316 u8 syndrome[0x20]; 4317 4318 u8 reserved_at_40[0x40]; 4319 4320 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4321 }; 4322 4323 struct mlx5_ifc_query_nic_vport_context_in_bits { 4324 u8 opcode[0x10]; 4325 u8 reserved_at_10[0x10]; 4326 4327 u8 reserved_at_20[0x10]; 4328 u8 op_mod[0x10]; 4329 4330 u8 other_vport[0x1]; 4331 u8 reserved_at_41[0xf]; 4332 u8 vport_number[0x10]; 4333 4334 u8 reserved_at_60[0x5]; 4335 u8 allowed_list_type[0x3]; 4336 u8 reserved_at_68[0x18]; 4337 }; 4338 4339 struct mlx5_ifc_query_mkey_out_bits { 4340 u8 status[0x8]; 4341 u8 reserved_at_8[0x18]; 4342 4343 u8 syndrome[0x20]; 4344 4345 u8 reserved_at_40[0x40]; 4346 4347 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4348 4349 u8 reserved_at_280[0x600]; 4350 4351 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4352 4353 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4354 }; 4355 4356 struct mlx5_ifc_query_mkey_in_bits { 4357 u8 opcode[0x10]; 4358 u8 reserved_at_10[0x10]; 4359 4360 u8 reserved_at_20[0x10]; 4361 u8 op_mod[0x10]; 4362 4363 u8 reserved_at_40[0x8]; 4364 u8 mkey_index[0x18]; 4365 4366 u8 pg_access[0x1]; 4367 u8 reserved_at_61[0x1f]; 4368 }; 4369 4370 struct mlx5_ifc_query_mad_demux_out_bits { 4371 u8 status[0x8]; 4372 u8 reserved_at_8[0x18]; 4373 4374 u8 syndrome[0x20]; 4375 4376 u8 reserved_at_40[0x40]; 4377 4378 u8 mad_dumux_parameters_block[0x20]; 4379 }; 4380 4381 struct mlx5_ifc_query_mad_demux_in_bits { 4382 u8 opcode[0x10]; 4383 u8 reserved_at_10[0x10]; 4384 4385 u8 reserved_at_20[0x10]; 4386 u8 op_mod[0x10]; 4387 4388 u8 reserved_at_40[0x40]; 4389 }; 4390 4391 struct mlx5_ifc_query_l2_table_entry_out_bits { 4392 u8 status[0x8]; 4393 u8 reserved_at_8[0x18]; 4394 4395 u8 syndrome[0x20]; 4396 4397 u8 reserved_at_40[0xa0]; 4398 4399 u8 reserved_at_e0[0x13]; 4400 u8 vlan_valid[0x1]; 4401 u8 vlan[0xc]; 4402 4403 struct mlx5_ifc_mac_address_layout_bits mac_address; 4404 4405 u8 reserved_at_140[0xc0]; 4406 }; 4407 4408 struct mlx5_ifc_query_l2_table_entry_in_bits { 4409 u8 opcode[0x10]; 4410 u8 reserved_at_10[0x10]; 4411 4412 u8 reserved_at_20[0x10]; 4413 u8 op_mod[0x10]; 4414 4415 u8 reserved_at_40[0x60]; 4416 4417 u8 reserved_at_a0[0x8]; 4418 u8 table_index[0x18]; 4419 4420 u8 reserved_at_c0[0x140]; 4421 }; 4422 4423 struct mlx5_ifc_query_issi_out_bits { 4424 u8 status[0x8]; 4425 u8 reserved_at_8[0x18]; 4426 4427 u8 syndrome[0x20]; 4428 4429 u8 reserved_at_40[0x10]; 4430 u8 current_issi[0x10]; 4431 4432 u8 reserved_at_60[0xa0]; 4433 4434 u8 reserved_at_100[76][0x8]; 4435 u8 supported_issi_dw0[0x20]; 4436 }; 4437 4438 struct mlx5_ifc_query_issi_in_bits { 4439 u8 opcode[0x10]; 4440 u8 reserved_at_10[0x10]; 4441 4442 u8 reserved_at_20[0x10]; 4443 u8 op_mod[0x10]; 4444 4445 u8 reserved_at_40[0x40]; 4446 }; 4447 4448 struct mlx5_ifc_set_driver_version_out_bits { 4449 u8 status[0x8]; 4450 u8 reserved_0[0x18]; 4451 4452 u8 syndrome[0x20]; 4453 u8 reserved_1[0x40]; 4454 }; 4455 4456 struct mlx5_ifc_set_driver_version_in_bits { 4457 u8 opcode[0x10]; 4458 u8 reserved_0[0x10]; 4459 4460 u8 reserved_1[0x10]; 4461 u8 op_mod[0x10]; 4462 4463 u8 reserved_2[0x40]; 4464 u8 driver_version[64][0x8]; 4465 }; 4466 4467 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4468 u8 status[0x8]; 4469 u8 reserved_at_8[0x18]; 4470 4471 u8 syndrome[0x20]; 4472 4473 u8 reserved_at_40[0x40]; 4474 4475 struct mlx5_ifc_pkey_bits pkey[0]; 4476 }; 4477 4478 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4479 u8 opcode[0x10]; 4480 u8 reserved_at_10[0x10]; 4481 4482 u8 reserved_at_20[0x10]; 4483 u8 op_mod[0x10]; 4484 4485 u8 other_vport[0x1]; 4486 u8 reserved_at_41[0xb]; 4487 u8 port_num[0x4]; 4488 u8 vport_number[0x10]; 4489 4490 u8 reserved_at_60[0x10]; 4491 u8 pkey_index[0x10]; 4492 }; 4493 4494 enum { 4495 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4496 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4497 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4498 }; 4499 4500 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4501 u8 status[0x8]; 4502 u8 reserved_at_8[0x18]; 4503 4504 u8 syndrome[0x20]; 4505 4506 u8 reserved_at_40[0x20]; 4507 4508 u8 gids_num[0x10]; 4509 u8 reserved_at_70[0x10]; 4510 4511 struct mlx5_ifc_array128_auto_bits gid[0]; 4512 }; 4513 4514 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4515 u8 opcode[0x10]; 4516 u8 reserved_at_10[0x10]; 4517 4518 u8 reserved_at_20[0x10]; 4519 u8 op_mod[0x10]; 4520 4521 u8 other_vport[0x1]; 4522 u8 reserved_at_41[0xb]; 4523 u8 port_num[0x4]; 4524 u8 vport_number[0x10]; 4525 4526 u8 reserved_at_60[0x10]; 4527 u8 gid_index[0x10]; 4528 }; 4529 4530 struct mlx5_ifc_query_hca_vport_context_out_bits { 4531 u8 status[0x8]; 4532 u8 reserved_at_8[0x18]; 4533 4534 u8 syndrome[0x20]; 4535 4536 u8 reserved_at_40[0x40]; 4537 4538 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4539 }; 4540 4541 struct mlx5_ifc_query_hca_vport_context_in_bits { 4542 u8 opcode[0x10]; 4543 u8 reserved_at_10[0x10]; 4544 4545 u8 reserved_at_20[0x10]; 4546 u8 op_mod[0x10]; 4547 4548 u8 other_vport[0x1]; 4549 u8 reserved_at_41[0xb]; 4550 u8 port_num[0x4]; 4551 u8 vport_number[0x10]; 4552 4553 u8 reserved_at_60[0x20]; 4554 }; 4555 4556 struct mlx5_ifc_query_hca_cap_out_bits { 4557 u8 status[0x8]; 4558 u8 reserved_at_8[0x18]; 4559 4560 u8 syndrome[0x20]; 4561 4562 u8 reserved_at_40[0x40]; 4563 4564 union mlx5_ifc_hca_cap_union_bits capability; 4565 }; 4566 4567 struct mlx5_ifc_query_hca_cap_in_bits { 4568 u8 opcode[0x10]; 4569 u8 reserved_at_10[0x10]; 4570 4571 u8 reserved_at_20[0x10]; 4572 u8 op_mod[0x10]; 4573 4574 u8 reserved_at_40[0x40]; 4575 }; 4576 4577 struct mlx5_ifc_query_flow_table_out_bits { 4578 u8 status[0x8]; 4579 u8 reserved_at_8[0x18]; 4580 4581 u8 syndrome[0x20]; 4582 4583 u8 reserved_at_40[0x80]; 4584 4585 u8 reserved_at_c0[0x8]; 4586 u8 level[0x8]; 4587 u8 reserved_at_d0[0x8]; 4588 u8 log_size[0x8]; 4589 4590 u8 reserved_at_e0[0x120]; 4591 }; 4592 4593 struct mlx5_ifc_query_flow_table_in_bits { 4594 u8 opcode[0x10]; 4595 u8 reserved_at_10[0x10]; 4596 4597 u8 reserved_at_20[0x10]; 4598 u8 op_mod[0x10]; 4599 4600 u8 reserved_at_40[0x40]; 4601 4602 u8 table_type[0x8]; 4603 u8 reserved_at_88[0x18]; 4604 4605 u8 reserved_at_a0[0x8]; 4606 u8 table_id[0x18]; 4607 4608 u8 reserved_at_c0[0x140]; 4609 }; 4610 4611 struct mlx5_ifc_query_fte_out_bits { 4612 u8 status[0x8]; 4613 u8 reserved_at_8[0x18]; 4614 4615 u8 syndrome[0x20]; 4616 4617 u8 reserved_at_40[0x1c0]; 4618 4619 struct mlx5_ifc_flow_context_bits flow_context; 4620 }; 4621 4622 struct mlx5_ifc_query_fte_in_bits { 4623 u8 opcode[0x10]; 4624 u8 reserved_at_10[0x10]; 4625 4626 u8 reserved_at_20[0x10]; 4627 u8 op_mod[0x10]; 4628 4629 u8 reserved_at_40[0x40]; 4630 4631 u8 table_type[0x8]; 4632 u8 reserved_at_88[0x18]; 4633 4634 u8 reserved_at_a0[0x8]; 4635 u8 table_id[0x18]; 4636 4637 u8 reserved_at_c0[0x40]; 4638 4639 u8 flow_index[0x20]; 4640 4641 u8 reserved_at_120[0xe0]; 4642 }; 4643 4644 enum { 4645 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4646 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4647 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4648 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3, 4649 }; 4650 4651 struct mlx5_ifc_query_flow_group_out_bits { 4652 u8 status[0x8]; 4653 u8 reserved_at_8[0x18]; 4654 4655 u8 syndrome[0x20]; 4656 4657 u8 reserved_at_40[0xa0]; 4658 4659 u8 start_flow_index[0x20]; 4660 4661 u8 reserved_at_100[0x20]; 4662 4663 u8 end_flow_index[0x20]; 4664 4665 u8 reserved_at_140[0xa0]; 4666 4667 u8 reserved_at_1e0[0x18]; 4668 u8 match_criteria_enable[0x8]; 4669 4670 struct mlx5_ifc_fte_match_param_bits match_criteria; 4671 4672 u8 reserved_at_1200[0xe00]; 4673 }; 4674 4675 struct mlx5_ifc_query_flow_group_in_bits { 4676 u8 opcode[0x10]; 4677 u8 reserved_at_10[0x10]; 4678 4679 u8 reserved_at_20[0x10]; 4680 u8 op_mod[0x10]; 4681 4682 u8 reserved_at_40[0x40]; 4683 4684 u8 table_type[0x8]; 4685 u8 reserved_at_88[0x18]; 4686 4687 u8 reserved_at_a0[0x8]; 4688 u8 table_id[0x18]; 4689 4690 u8 group_id[0x20]; 4691 4692 u8 reserved_at_e0[0x120]; 4693 }; 4694 4695 struct mlx5_ifc_query_flow_counter_out_bits { 4696 u8 status[0x8]; 4697 u8 reserved_at_8[0x18]; 4698 4699 u8 syndrome[0x20]; 4700 4701 u8 reserved_at_40[0x40]; 4702 4703 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4704 }; 4705 4706 struct mlx5_ifc_query_flow_counter_in_bits { 4707 u8 opcode[0x10]; 4708 u8 reserved_at_10[0x10]; 4709 4710 u8 reserved_at_20[0x10]; 4711 u8 op_mod[0x10]; 4712 4713 u8 reserved_at_40[0x80]; 4714 4715 u8 clear[0x1]; 4716 u8 reserved_at_c1[0xf]; 4717 u8 num_of_counters[0x10]; 4718 4719 u8 flow_counter_id[0x20]; 4720 }; 4721 4722 struct mlx5_ifc_query_esw_vport_context_out_bits { 4723 u8 status[0x8]; 4724 u8 reserved_at_8[0x18]; 4725 4726 u8 syndrome[0x20]; 4727 4728 u8 reserved_at_40[0x40]; 4729 4730 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4731 }; 4732 4733 struct mlx5_ifc_query_esw_vport_context_in_bits { 4734 u8 opcode[0x10]; 4735 u8 reserved_at_10[0x10]; 4736 4737 u8 reserved_at_20[0x10]; 4738 u8 op_mod[0x10]; 4739 4740 u8 other_vport[0x1]; 4741 u8 reserved_at_41[0xf]; 4742 u8 vport_number[0x10]; 4743 4744 u8 reserved_at_60[0x20]; 4745 }; 4746 4747 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4748 u8 status[0x8]; 4749 u8 reserved_at_8[0x18]; 4750 4751 u8 syndrome[0x20]; 4752 4753 u8 reserved_at_40[0x40]; 4754 }; 4755 4756 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4757 u8 reserved_at_0[0x1c]; 4758 u8 vport_cvlan_insert[0x1]; 4759 u8 vport_svlan_insert[0x1]; 4760 u8 vport_cvlan_strip[0x1]; 4761 u8 vport_svlan_strip[0x1]; 4762 }; 4763 4764 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4765 u8 opcode[0x10]; 4766 u8 reserved_at_10[0x10]; 4767 4768 u8 reserved_at_20[0x10]; 4769 u8 op_mod[0x10]; 4770 4771 u8 other_vport[0x1]; 4772 u8 reserved_at_41[0xf]; 4773 u8 vport_number[0x10]; 4774 4775 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4776 4777 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4778 }; 4779 4780 struct mlx5_ifc_query_eq_out_bits { 4781 u8 status[0x8]; 4782 u8 reserved_at_8[0x18]; 4783 4784 u8 syndrome[0x20]; 4785 4786 u8 reserved_at_40[0x40]; 4787 4788 struct mlx5_ifc_eqc_bits eq_context_entry; 4789 4790 u8 reserved_at_280[0x40]; 4791 4792 u8 event_bitmask[0x40]; 4793 4794 u8 reserved_at_300[0x580]; 4795 4796 u8 pas[0][0x40]; 4797 }; 4798 4799 struct mlx5_ifc_query_eq_in_bits { 4800 u8 opcode[0x10]; 4801 u8 reserved_at_10[0x10]; 4802 4803 u8 reserved_at_20[0x10]; 4804 u8 op_mod[0x10]; 4805 4806 u8 reserved_at_40[0x18]; 4807 u8 eq_number[0x8]; 4808 4809 u8 reserved_at_60[0x20]; 4810 }; 4811 4812 struct mlx5_ifc_encap_header_in_bits { 4813 u8 reserved_at_0[0x5]; 4814 u8 header_type[0x3]; 4815 u8 reserved_at_8[0xe]; 4816 u8 encap_header_size[0xa]; 4817 4818 u8 reserved_at_20[0x10]; 4819 u8 encap_header[2][0x8]; 4820 4821 u8 more_encap_header[0][0x8]; 4822 }; 4823 4824 struct mlx5_ifc_query_encap_header_out_bits { 4825 u8 status[0x8]; 4826 u8 reserved_at_8[0x18]; 4827 4828 u8 syndrome[0x20]; 4829 4830 u8 reserved_at_40[0xa0]; 4831 4832 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4833 }; 4834 4835 struct mlx5_ifc_query_encap_header_in_bits { 4836 u8 opcode[0x10]; 4837 u8 reserved_at_10[0x10]; 4838 4839 u8 reserved_at_20[0x10]; 4840 u8 op_mod[0x10]; 4841 4842 u8 encap_id[0x20]; 4843 4844 u8 reserved_at_60[0xa0]; 4845 }; 4846 4847 struct mlx5_ifc_alloc_encap_header_out_bits { 4848 u8 status[0x8]; 4849 u8 reserved_at_8[0x18]; 4850 4851 u8 syndrome[0x20]; 4852 4853 u8 encap_id[0x20]; 4854 4855 u8 reserved_at_60[0x20]; 4856 }; 4857 4858 struct mlx5_ifc_alloc_encap_header_in_bits { 4859 u8 opcode[0x10]; 4860 u8 reserved_at_10[0x10]; 4861 4862 u8 reserved_at_20[0x10]; 4863 u8 op_mod[0x10]; 4864 4865 u8 reserved_at_40[0xa0]; 4866 4867 struct mlx5_ifc_encap_header_in_bits encap_header; 4868 }; 4869 4870 struct mlx5_ifc_dealloc_encap_header_out_bits { 4871 u8 status[0x8]; 4872 u8 reserved_at_8[0x18]; 4873 4874 u8 syndrome[0x20]; 4875 4876 u8 reserved_at_40[0x40]; 4877 }; 4878 4879 struct mlx5_ifc_dealloc_encap_header_in_bits { 4880 u8 opcode[0x10]; 4881 u8 reserved_at_10[0x10]; 4882 4883 u8 reserved_20[0x10]; 4884 u8 op_mod[0x10]; 4885 4886 u8 encap_id[0x20]; 4887 4888 u8 reserved_60[0x20]; 4889 }; 4890 4891 struct mlx5_ifc_set_action_in_bits { 4892 u8 action_type[0x4]; 4893 u8 field[0xc]; 4894 u8 reserved_at_10[0x3]; 4895 u8 offset[0x5]; 4896 u8 reserved_at_18[0x3]; 4897 u8 length[0x5]; 4898 4899 u8 data[0x20]; 4900 }; 4901 4902 struct mlx5_ifc_add_action_in_bits { 4903 u8 action_type[0x4]; 4904 u8 field[0xc]; 4905 u8 reserved_at_10[0x10]; 4906 4907 u8 data[0x20]; 4908 }; 4909 4910 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4911 struct mlx5_ifc_set_action_in_bits set_action_in; 4912 struct mlx5_ifc_add_action_in_bits add_action_in; 4913 u8 reserved_at_0[0x40]; 4914 }; 4915 4916 enum { 4917 MLX5_ACTION_TYPE_SET = 0x1, 4918 MLX5_ACTION_TYPE_ADD = 0x2, 4919 }; 4920 4921 enum { 4922 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4923 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4924 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4925 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4926 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4927 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4928 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4929 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4930 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4931 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4932 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4933 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4934 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4935 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4936 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4937 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4938 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4939 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4940 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4941 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4942 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4943 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4944 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4945 }; 4946 4947 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4948 u8 status[0x8]; 4949 u8 reserved_at_8[0x18]; 4950 4951 u8 syndrome[0x20]; 4952 4953 u8 modify_header_id[0x20]; 4954 4955 u8 reserved_at_60[0x20]; 4956 }; 4957 4958 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4959 u8 opcode[0x10]; 4960 u8 reserved_at_10[0x10]; 4961 4962 u8 reserved_at_20[0x10]; 4963 u8 op_mod[0x10]; 4964 4965 u8 reserved_at_40[0x20]; 4966 4967 u8 table_type[0x8]; 4968 u8 reserved_at_68[0x10]; 4969 u8 num_of_actions[0x8]; 4970 4971 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4972 }; 4973 4974 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4975 u8 status[0x8]; 4976 u8 reserved_at_8[0x18]; 4977 4978 u8 syndrome[0x20]; 4979 4980 u8 reserved_at_40[0x40]; 4981 }; 4982 4983 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4984 u8 opcode[0x10]; 4985 u8 reserved_at_10[0x10]; 4986 4987 u8 reserved_at_20[0x10]; 4988 u8 op_mod[0x10]; 4989 4990 u8 modify_header_id[0x20]; 4991 4992 u8 reserved_at_60[0x20]; 4993 }; 4994 4995 struct mlx5_ifc_query_dct_out_bits { 4996 u8 status[0x8]; 4997 u8 reserved_at_8[0x18]; 4998 4999 u8 syndrome[0x20]; 5000 5001 u8 reserved_at_40[0x40]; 5002 5003 struct mlx5_ifc_dctc_bits dct_context_entry; 5004 5005 u8 reserved_at_280[0x180]; 5006 }; 5007 5008 struct mlx5_ifc_query_dct_in_bits { 5009 u8 opcode[0x10]; 5010 u8 reserved_at_10[0x10]; 5011 5012 u8 reserved_at_20[0x10]; 5013 u8 op_mod[0x10]; 5014 5015 u8 reserved_at_40[0x8]; 5016 u8 dctn[0x18]; 5017 5018 u8 reserved_at_60[0x20]; 5019 }; 5020 5021 struct mlx5_ifc_query_cq_out_bits { 5022 u8 status[0x8]; 5023 u8 reserved_at_8[0x18]; 5024 5025 u8 syndrome[0x20]; 5026 5027 u8 reserved_at_40[0x40]; 5028 5029 struct mlx5_ifc_cqc_bits cq_context; 5030 5031 u8 reserved_at_280[0x600]; 5032 5033 u8 pas[0][0x40]; 5034 }; 5035 5036 struct mlx5_ifc_query_cq_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_at_10[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 reserved_at_40[0x8]; 5044 u8 cqn[0x18]; 5045 5046 u8 reserved_at_60[0x20]; 5047 }; 5048 5049 struct mlx5_ifc_query_cong_status_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_at_8[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 reserved_at_40[0x20]; 5056 5057 u8 enable[0x1]; 5058 u8 tag_enable[0x1]; 5059 u8 reserved_at_62[0x1e]; 5060 }; 5061 5062 struct mlx5_ifc_query_cong_status_in_bits { 5063 u8 opcode[0x10]; 5064 u8 reserved_at_10[0x10]; 5065 5066 u8 reserved_at_20[0x10]; 5067 u8 op_mod[0x10]; 5068 5069 u8 reserved_at_40[0x18]; 5070 u8 priority[0x4]; 5071 u8 cong_protocol[0x4]; 5072 5073 u8 reserved_at_60[0x20]; 5074 }; 5075 5076 struct mlx5_ifc_query_cong_statistics_out_bits { 5077 u8 status[0x8]; 5078 u8 reserved_at_8[0x18]; 5079 5080 u8 syndrome[0x20]; 5081 5082 u8 reserved_at_40[0x40]; 5083 5084 u8 rp_cur_flows[0x20]; 5085 5086 u8 sum_flows[0x20]; 5087 5088 u8 rp_cnp_ignored_high[0x20]; 5089 5090 u8 rp_cnp_ignored_low[0x20]; 5091 5092 u8 rp_cnp_handled_high[0x20]; 5093 5094 u8 rp_cnp_handled_low[0x20]; 5095 5096 u8 reserved_at_140[0x100]; 5097 5098 u8 time_stamp_high[0x20]; 5099 5100 u8 time_stamp_low[0x20]; 5101 5102 u8 accumulators_period[0x20]; 5103 5104 u8 np_ecn_marked_roce_packets_high[0x20]; 5105 5106 u8 np_ecn_marked_roce_packets_low[0x20]; 5107 5108 u8 np_cnp_sent_high[0x20]; 5109 5110 u8 np_cnp_sent_low[0x20]; 5111 5112 u8 reserved_at_320[0x560]; 5113 }; 5114 5115 struct mlx5_ifc_query_cong_statistics_in_bits { 5116 u8 opcode[0x10]; 5117 u8 reserved_at_10[0x10]; 5118 5119 u8 reserved_at_20[0x10]; 5120 u8 op_mod[0x10]; 5121 5122 u8 clear[0x1]; 5123 u8 reserved_at_41[0x1f]; 5124 5125 u8 reserved_at_60[0x20]; 5126 }; 5127 5128 struct mlx5_ifc_query_cong_params_out_bits { 5129 u8 status[0x8]; 5130 u8 reserved_at_8[0x18]; 5131 5132 u8 syndrome[0x20]; 5133 5134 u8 reserved_at_40[0x40]; 5135 5136 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5137 }; 5138 5139 struct mlx5_ifc_query_cong_params_in_bits { 5140 u8 opcode[0x10]; 5141 u8 reserved_at_10[0x10]; 5142 5143 u8 reserved_at_20[0x10]; 5144 u8 op_mod[0x10]; 5145 5146 u8 reserved_at_40[0x1c]; 5147 u8 cong_protocol[0x4]; 5148 5149 u8 reserved_at_60[0x20]; 5150 }; 5151 5152 struct mlx5_ifc_query_adapter_out_bits { 5153 u8 status[0x8]; 5154 u8 reserved_at_8[0x18]; 5155 5156 u8 syndrome[0x20]; 5157 5158 u8 reserved_at_40[0x40]; 5159 5160 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5161 }; 5162 5163 struct mlx5_ifc_query_adapter_in_bits { 5164 u8 opcode[0x10]; 5165 u8 reserved_at_10[0x10]; 5166 5167 u8 reserved_at_20[0x10]; 5168 u8 op_mod[0x10]; 5169 5170 u8 reserved_at_40[0x40]; 5171 }; 5172 5173 struct mlx5_ifc_qp_2rst_out_bits { 5174 u8 status[0x8]; 5175 u8 reserved_at_8[0x18]; 5176 5177 u8 syndrome[0x20]; 5178 5179 u8 reserved_at_40[0x40]; 5180 }; 5181 5182 struct mlx5_ifc_qp_2rst_in_bits { 5183 u8 opcode[0x10]; 5184 u8 reserved_at_10[0x10]; 5185 5186 u8 reserved_at_20[0x10]; 5187 u8 op_mod[0x10]; 5188 5189 u8 reserved_at_40[0x8]; 5190 u8 qpn[0x18]; 5191 5192 u8 reserved_at_60[0x20]; 5193 }; 5194 5195 struct mlx5_ifc_qp_2err_out_bits { 5196 u8 status[0x8]; 5197 u8 reserved_at_8[0x18]; 5198 5199 u8 syndrome[0x20]; 5200 5201 u8 reserved_at_40[0x40]; 5202 }; 5203 5204 struct mlx5_ifc_qp_2err_in_bits { 5205 u8 opcode[0x10]; 5206 u8 reserved_at_10[0x10]; 5207 5208 u8 reserved_at_20[0x10]; 5209 u8 op_mod[0x10]; 5210 5211 u8 reserved_at_40[0x8]; 5212 u8 qpn[0x18]; 5213 5214 u8 reserved_at_60[0x20]; 5215 }; 5216 5217 struct mlx5_ifc_page_fault_resume_out_bits { 5218 u8 status[0x8]; 5219 u8 reserved_at_8[0x18]; 5220 5221 u8 syndrome[0x20]; 5222 5223 u8 reserved_at_40[0x40]; 5224 }; 5225 5226 struct mlx5_ifc_page_fault_resume_in_bits { 5227 u8 opcode[0x10]; 5228 u8 reserved_at_10[0x10]; 5229 5230 u8 reserved_at_20[0x10]; 5231 u8 op_mod[0x10]; 5232 5233 u8 error[0x1]; 5234 u8 reserved_at_41[0x4]; 5235 u8 page_fault_type[0x3]; 5236 u8 wq_number[0x18]; 5237 5238 u8 reserved_at_60[0x8]; 5239 u8 token[0x18]; 5240 }; 5241 5242 struct mlx5_ifc_nop_out_bits { 5243 u8 status[0x8]; 5244 u8 reserved_at_8[0x18]; 5245 5246 u8 syndrome[0x20]; 5247 5248 u8 reserved_at_40[0x40]; 5249 }; 5250 5251 struct mlx5_ifc_nop_in_bits { 5252 u8 opcode[0x10]; 5253 u8 reserved_at_10[0x10]; 5254 5255 u8 reserved_at_20[0x10]; 5256 u8 op_mod[0x10]; 5257 5258 u8 reserved_at_40[0x40]; 5259 }; 5260 5261 struct mlx5_ifc_modify_vport_state_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 }; 5269 5270 struct mlx5_ifc_modify_vport_state_in_bits { 5271 u8 opcode[0x10]; 5272 u8 reserved_at_10[0x10]; 5273 5274 u8 reserved_at_20[0x10]; 5275 u8 op_mod[0x10]; 5276 5277 u8 other_vport[0x1]; 5278 u8 reserved_at_41[0xf]; 5279 u8 vport_number[0x10]; 5280 5281 u8 reserved_at_60[0x18]; 5282 u8 admin_state[0x4]; 5283 u8 reserved_at_7c[0x4]; 5284 }; 5285 5286 struct mlx5_ifc_modify_tis_out_bits { 5287 u8 status[0x8]; 5288 u8 reserved_at_8[0x18]; 5289 5290 u8 syndrome[0x20]; 5291 5292 u8 reserved_at_40[0x40]; 5293 }; 5294 5295 struct mlx5_ifc_modify_tis_bitmask_bits { 5296 u8 reserved_at_0[0x20]; 5297 5298 u8 reserved_at_20[0x1d]; 5299 u8 lag_tx_port_affinity[0x1]; 5300 u8 strict_lag_tx_port_affinity[0x1]; 5301 u8 prio[0x1]; 5302 }; 5303 5304 struct mlx5_ifc_modify_tis_in_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 reserved_at_20[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_at_40[0x8]; 5312 u8 tisn[0x18]; 5313 5314 u8 reserved_at_60[0x20]; 5315 5316 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5317 5318 u8 reserved_at_c0[0x40]; 5319 5320 struct mlx5_ifc_tisc_bits ctx; 5321 }; 5322 5323 struct mlx5_ifc_modify_tir_bitmask_bits { 5324 u8 reserved_at_0[0x20]; 5325 5326 u8 reserved_at_20[0x1b]; 5327 u8 self_lb_en[0x1]; 5328 u8 reserved_at_3c[0x1]; 5329 u8 hash[0x1]; 5330 u8 reserved_at_3e[0x1]; 5331 u8 lro[0x1]; 5332 }; 5333 5334 struct mlx5_ifc_modify_tir_out_bits { 5335 u8 status[0x8]; 5336 u8 reserved_at_8[0x18]; 5337 5338 u8 syndrome[0x20]; 5339 5340 u8 reserved_at_40[0x40]; 5341 }; 5342 5343 struct mlx5_ifc_modify_tir_in_bits { 5344 u8 opcode[0x10]; 5345 u8 reserved_at_10[0x10]; 5346 5347 u8 reserved_at_20[0x10]; 5348 u8 op_mod[0x10]; 5349 5350 u8 reserved_at_40[0x8]; 5351 u8 tirn[0x18]; 5352 5353 u8 reserved_at_60[0x20]; 5354 5355 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5356 5357 u8 reserved_at_c0[0x40]; 5358 5359 struct mlx5_ifc_tirc_bits ctx; 5360 }; 5361 5362 struct mlx5_ifc_modify_sq_out_bits { 5363 u8 status[0x8]; 5364 u8 reserved_at_8[0x18]; 5365 5366 u8 syndrome[0x20]; 5367 5368 u8 reserved_at_40[0x40]; 5369 }; 5370 5371 struct mlx5_ifc_modify_sq_in_bits { 5372 u8 opcode[0x10]; 5373 u8 reserved_at_10[0x10]; 5374 5375 u8 reserved_at_20[0x10]; 5376 u8 op_mod[0x10]; 5377 5378 u8 sq_state[0x4]; 5379 u8 reserved_at_44[0x4]; 5380 u8 sqn[0x18]; 5381 5382 u8 reserved_at_60[0x20]; 5383 5384 u8 modify_bitmask[0x40]; 5385 5386 u8 reserved_at_c0[0x40]; 5387 5388 struct mlx5_ifc_sqc_bits ctx; 5389 }; 5390 5391 struct mlx5_ifc_modify_scheduling_element_out_bits { 5392 u8 status[0x8]; 5393 u8 reserved_at_8[0x18]; 5394 5395 u8 syndrome[0x20]; 5396 5397 u8 reserved_at_40[0x1c0]; 5398 }; 5399 5400 enum { 5401 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5402 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5403 }; 5404 5405 struct mlx5_ifc_modify_scheduling_element_in_bits { 5406 u8 opcode[0x10]; 5407 u8 reserved_at_10[0x10]; 5408 5409 u8 reserved_at_20[0x10]; 5410 u8 op_mod[0x10]; 5411 5412 u8 scheduling_hierarchy[0x8]; 5413 u8 reserved_at_48[0x18]; 5414 5415 u8 scheduling_element_id[0x20]; 5416 5417 u8 reserved_at_80[0x20]; 5418 5419 u8 modify_bitmask[0x20]; 5420 5421 u8 reserved_at_c0[0x40]; 5422 5423 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5424 5425 u8 reserved_at_300[0x100]; 5426 }; 5427 5428 struct mlx5_ifc_modify_rqt_out_bits { 5429 u8 status[0x8]; 5430 u8 reserved_at_8[0x18]; 5431 5432 u8 syndrome[0x20]; 5433 5434 u8 reserved_at_40[0x40]; 5435 }; 5436 5437 struct mlx5_ifc_rqt_bitmask_bits { 5438 u8 reserved_at_0[0x20]; 5439 5440 u8 reserved_at_20[0x1f]; 5441 u8 rqn_list[0x1]; 5442 }; 5443 5444 struct mlx5_ifc_modify_rqt_in_bits { 5445 u8 opcode[0x10]; 5446 u8 reserved_at_10[0x10]; 5447 5448 u8 reserved_at_20[0x10]; 5449 u8 op_mod[0x10]; 5450 5451 u8 reserved_at_40[0x8]; 5452 u8 rqtn[0x18]; 5453 5454 u8 reserved_at_60[0x20]; 5455 5456 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5457 5458 u8 reserved_at_c0[0x40]; 5459 5460 struct mlx5_ifc_rqtc_bits ctx; 5461 }; 5462 5463 struct mlx5_ifc_modify_rq_out_bits { 5464 u8 status[0x8]; 5465 u8 reserved_at_8[0x18]; 5466 5467 u8 syndrome[0x20]; 5468 5469 u8 reserved_at_40[0x40]; 5470 }; 5471 5472 enum { 5473 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5474 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5475 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5476 }; 5477 5478 struct mlx5_ifc_modify_rq_in_bits { 5479 u8 opcode[0x10]; 5480 u8 reserved_at_10[0x10]; 5481 5482 u8 reserved_at_20[0x10]; 5483 u8 op_mod[0x10]; 5484 5485 u8 rq_state[0x4]; 5486 u8 reserved_at_44[0x4]; 5487 u8 rqn[0x18]; 5488 5489 u8 reserved_at_60[0x20]; 5490 5491 u8 modify_bitmask[0x40]; 5492 5493 u8 reserved_at_c0[0x40]; 5494 5495 struct mlx5_ifc_rqc_bits ctx; 5496 }; 5497 5498 struct mlx5_ifc_modify_rmp_out_bits { 5499 u8 status[0x8]; 5500 u8 reserved_at_8[0x18]; 5501 5502 u8 syndrome[0x20]; 5503 5504 u8 reserved_at_40[0x40]; 5505 }; 5506 5507 struct mlx5_ifc_rmp_bitmask_bits { 5508 u8 reserved_at_0[0x20]; 5509 5510 u8 reserved_at_20[0x1f]; 5511 u8 lwm[0x1]; 5512 }; 5513 5514 struct mlx5_ifc_modify_rmp_in_bits { 5515 u8 opcode[0x10]; 5516 u8 reserved_at_10[0x10]; 5517 5518 u8 reserved_at_20[0x10]; 5519 u8 op_mod[0x10]; 5520 5521 u8 rmp_state[0x4]; 5522 u8 reserved_at_44[0x4]; 5523 u8 rmpn[0x18]; 5524 5525 u8 reserved_at_60[0x20]; 5526 5527 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5528 5529 u8 reserved_at_c0[0x40]; 5530 5531 struct mlx5_ifc_rmpc_bits ctx; 5532 }; 5533 5534 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5535 u8 status[0x8]; 5536 u8 reserved_at_8[0x18]; 5537 5538 u8 syndrome[0x20]; 5539 5540 u8 reserved_at_40[0x40]; 5541 }; 5542 5543 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5544 u8 reserved_at_0[0x12]; 5545 u8 affiliation[0x1]; 5546 u8 reserved_at_e[0x1]; 5547 u8 disable_uc_local_lb[0x1]; 5548 u8 disable_mc_local_lb[0x1]; 5549 u8 node_guid[0x1]; 5550 u8 port_guid[0x1]; 5551 u8 min_inline[0x1]; 5552 u8 mtu[0x1]; 5553 u8 change_event[0x1]; 5554 u8 promisc[0x1]; 5555 u8 permanent_address[0x1]; 5556 u8 addresses_list[0x1]; 5557 u8 roce_en[0x1]; 5558 u8 reserved_at_1f[0x1]; 5559 }; 5560 5561 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5562 u8 opcode[0x10]; 5563 u8 reserved_at_10[0x10]; 5564 5565 u8 reserved_at_20[0x10]; 5566 u8 op_mod[0x10]; 5567 5568 u8 other_vport[0x1]; 5569 u8 reserved_at_41[0xf]; 5570 u8 vport_number[0x10]; 5571 5572 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5573 5574 u8 reserved_at_80[0x780]; 5575 5576 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5577 }; 5578 5579 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5580 u8 status[0x8]; 5581 u8 reserved_at_8[0x18]; 5582 5583 u8 syndrome[0x20]; 5584 5585 u8 reserved_at_40[0x40]; 5586 }; 5587 5588 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5589 u8 opcode[0x10]; 5590 u8 reserved_at_10[0x10]; 5591 5592 u8 reserved_at_20[0x10]; 5593 u8 op_mod[0x10]; 5594 5595 u8 other_vport[0x1]; 5596 u8 reserved_at_41[0xb]; 5597 u8 port_num[0x4]; 5598 u8 vport_number[0x10]; 5599 5600 u8 reserved_at_60[0x20]; 5601 5602 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5603 }; 5604 5605 struct mlx5_ifc_modify_cq_out_bits { 5606 u8 status[0x8]; 5607 u8 reserved_at_8[0x18]; 5608 5609 u8 syndrome[0x20]; 5610 5611 u8 reserved_at_40[0x40]; 5612 }; 5613 5614 enum { 5615 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5616 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5617 }; 5618 5619 struct mlx5_ifc_modify_cq_in_bits { 5620 u8 opcode[0x10]; 5621 u8 reserved_at_10[0x10]; 5622 5623 u8 reserved_at_20[0x10]; 5624 u8 op_mod[0x10]; 5625 5626 u8 reserved_at_40[0x8]; 5627 u8 cqn[0x18]; 5628 5629 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5630 5631 struct mlx5_ifc_cqc_bits cq_context; 5632 5633 u8 reserved_at_280[0x60]; 5634 5635 u8 cq_umem_valid[0x1]; 5636 u8 reserved_at_2e1[0x1f]; 5637 5638 u8 reserved_at_300[0x580]; 5639 5640 u8 pas[0][0x40]; 5641 }; 5642 5643 struct mlx5_ifc_modify_cong_status_out_bits { 5644 u8 status[0x8]; 5645 u8 reserved_at_8[0x18]; 5646 5647 u8 syndrome[0x20]; 5648 5649 u8 reserved_at_40[0x40]; 5650 }; 5651 5652 struct mlx5_ifc_modify_cong_status_in_bits { 5653 u8 opcode[0x10]; 5654 u8 reserved_at_10[0x10]; 5655 5656 u8 reserved_at_20[0x10]; 5657 u8 op_mod[0x10]; 5658 5659 u8 reserved_at_40[0x18]; 5660 u8 priority[0x4]; 5661 u8 cong_protocol[0x4]; 5662 5663 u8 enable[0x1]; 5664 u8 tag_enable[0x1]; 5665 u8 reserved_at_62[0x1e]; 5666 }; 5667 5668 struct mlx5_ifc_modify_cong_params_out_bits { 5669 u8 status[0x8]; 5670 u8 reserved_at_8[0x18]; 5671 5672 u8 syndrome[0x20]; 5673 5674 u8 reserved_at_40[0x40]; 5675 }; 5676 5677 struct mlx5_ifc_modify_cong_params_in_bits { 5678 u8 opcode[0x10]; 5679 u8 reserved_at_10[0x10]; 5680 5681 u8 reserved_at_20[0x10]; 5682 u8 op_mod[0x10]; 5683 5684 u8 reserved_at_40[0x1c]; 5685 u8 cong_protocol[0x4]; 5686 5687 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5688 5689 u8 reserved_at_80[0x80]; 5690 5691 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5692 }; 5693 5694 struct mlx5_ifc_manage_pages_out_bits { 5695 u8 status[0x8]; 5696 u8 reserved_at_8[0x18]; 5697 5698 u8 syndrome[0x20]; 5699 5700 u8 output_num_entries[0x20]; 5701 5702 u8 reserved_at_60[0x20]; 5703 5704 u8 pas[0][0x40]; 5705 }; 5706 5707 enum { 5708 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5709 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5710 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5711 }; 5712 5713 struct mlx5_ifc_manage_pages_in_bits { 5714 u8 opcode[0x10]; 5715 u8 reserved_at_10[0x10]; 5716 5717 u8 reserved_at_20[0x10]; 5718 u8 op_mod[0x10]; 5719 5720 u8 reserved_at_40[0x10]; 5721 u8 function_id[0x10]; 5722 5723 u8 input_num_entries[0x20]; 5724 5725 u8 pas[0][0x40]; 5726 }; 5727 5728 struct mlx5_ifc_mad_ifc_out_bits { 5729 u8 status[0x8]; 5730 u8 reserved_at_8[0x18]; 5731 5732 u8 syndrome[0x20]; 5733 5734 u8 reserved_at_40[0x40]; 5735 5736 u8 response_mad_packet[256][0x8]; 5737 }; 5738 5739 struct mlx5_ifc_mad_ifc_in_bits { 5740 u8 opcode[0x10]; 5741 u8 reserved_at_10[0x10]; 5742 5743 u8 reserved_at_20[0x10]; 5744 u8 op_mod[0x10]; 5745 5746 u8 remote_lid[0x10]; 5747 u8 reserved_at_50[0x8]; 5748 u8 port[0x8]; 5749 5750 u8 reserved_at_60[0x20]; 5751 5752 u8 mad[256][0x8]; 5753 }; 5754 5755 struct mlx5_ifc_init_hca_out_bits { 5756 u8 status[0x8]; 5757 u8 reserved_at_8[0x18]; 5758 5759 u8 syndrome[0x20]; 5760 5761 u8 reserved_at_40[0x40]; 5762 }; 5763 5764 struct mlx5_ifc_init_hca_in_bits { 5765 u8 opcode[0x10]; 5766 u8 reserved_at_10[0x10]; 5767 5768 u8 reserved_at_20[0x10]; 5769 u8 op_mod[0x10]; 5770 5771 u8 reserved_at_40[0x40]; 5772 u8 sw_owner_id[4][0x20]; 5773 }; 5774 5775 struct mlx5_ifc_init2rtr_qp_out_bits { 5776 u8 status[0x8]; 5777 u8 reserved_at_8[0x18]; 5778 5779 u8 syndrome[0x20]; 5780 5781 u8 reserved_at_40[0x40]; 5782 }; 5783 5784 struct mlx5_ifc_init2rtr_qp_in_bits { 5785 u8 opcode[0x10]; 5786 u8 reserved_at_10[0x10]; 5787 5788 u8 reserved_at_20[0x10]; 5789 u8 op_mod[0x10]; 5790 5791 u8 reserved_at_40[0x8]; 5792 u8 qpn[0x18]; 5793 5794 u8 reserved_at_60[0x20]; 5795 5796 u8 opt_param_mask[0x20]; 5797 5798 u8 reserved_at_a0[0x20]; 5799 5800 struct mlx5_ifc_qpc_bits qpc; 5801 5802 u8 reserved_at_800[0x80]; 5803 }; 5804 5805 struct mlx5_ifc_init2init_qp_out_bits { 5806 u8 status[0x8]; 5807 u8 reserved_at_8[0x18]; 5808 5809 u8 syndrome[0x20]; 5810 5811 u8 reserved_at_40[0x40]; 5812 }; 5813 5814 struct mlx5_ifc_init2init_qp_in_bits { 5815 u8 opcode[0x10]; 5816 u8 reserved_at_10[0x10]; 5817 5818 u8 reserved_at_20[0x10]; 5819 u8 op_mod[0x10]; 5820 5821 u8 reserved_at_40[0x8]; 5822 u8 qpn[0x18]; 5823 5824 u8 reserved_at_60[0x20]; 5825 5826 u8 opt_param_mask[0x20]; 5827 5828 u8 reserved_at_a0[0x20]; 5829 5830 struct mlx5_ifc_qpc_bits qpc; 5831 5832 u8 reserved_at_800[0x80]; 5833 }; 5834 5835 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5836 u8 status[0x8]; 5837 u8 reserved_at_8[0x18]; 5838 5839 u8 syndrome[0x20]; 5840 5841 u8 reserved_at_40[0x40]; 5842 5843 u8 packet_headers_log[128][0x8]; 5844 5845 u8 packet_syndrome[64][0x8]; 5846 }; 5847 5848 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5849 u8 opcode[0x10]; 5850 u8 reserved_at_10[0x10]; 5851 5852 u8 reserved_at_20[0x10]; 5853 u8 op_mod[0x10]; 5854 5855 u8 reserved_at_40[0x40]; 5856 }; 5857 5858 struct mlx5_ifc_gen_eqe_in_bits { 5859 u8 opcode[0x10]; 5860 u8 reserved_at_10[0x10]; 5861 5862 u8 reserved_at_20[0x10]; 5863 u8 op_mod[0x10]; 5864 5865 u8 reserved_at_40[0x18]; 5866 u8 eq_number[0x8]; 5867 5868 u8 reserved_at_60[0x20]; 5869 5870 u8 eqe[64][0x8]; 5871 }; 5872 5873 struct mlx5_ifc_gen_eq_out_bits { 5874 u8 status[0x8]; 5875 u8 reserved_at_8[0x18]; 5876 5877 u8 syndrome[0x20]; 5878 5879 u8 reserved_at_40[0x40]; 5880 }; 5881 5882 struct mlx5_ifc_enable_hca_out_bits { 5883 u8 status[0x8]; 5884 u8 reserved_at_8[0x18]; 5885 5886 u8 syndrome[0x20]; 5887 5888 u8 reserved_at_40[0x20]; 5889 }; 5890 5891 struct mlx5_ifc_enable_hca_in_bits { 5892 u8 opcode[0x10]; 5893 u8 reserved_at_10[0x10]; 5894 5895 u8 reserved_at_20[0x10]; 5896 u8 op_mod[0x10]; 5897 5898 u8 reserved_at_40[0x10]; 5899 u8 function_id[0x10]; 5900 5901 u8 reserved_at_60[0x20]; 5902 }; 5903 5904 struct mlx5_ifc_drain_dct_out_bits { 5905 u8 status[0x8]; 5906 u8 reserved_at_8[0x18]; 5907 5908 u8 syndrome[0x20]; 5909 5910 u8 reserved_at_40[0x40]; 5911 }; 5912 5913 struct mlx5_ifc_drain_dct_in_bits { 5914 u8 opcode[0x10]; 5915 u8 reserved_at_10[0x10]; 5916 5917 u8 reserved_at_20[0x10]; 5918 u8 op_mod[0x10]; 5919 5920 u8 reserved_at_40[0x8]; 5921 u8 dctn[0x18]; 5922 5923 u8 reserved_at_60[0x20]; 5924 }; 5925 5926 struct mlx5_ifc_disable_hca_out_bits { 5927 u8 status[0x8]; 5928 u8 reserved_at_8[0x18]; 5929 5930 u8 syndrome[0x20]; 5931 5932 u8 reserved_at_40[0x20]; 5933 }; 5934 5935 struct mlx5_ifc_disable_hca_in_bits { 5936 u8 opcode[0x10]; 5937 u8 reserved_at_10[0x10]; 5938 5939 u8 reserved_at_20[0x10]; 5940 u8 op_mod[0x10]; 5941 5942 u8 reserved_at_40[0x10]; 5943 u8 function_id[0x10]; 5944 5945 u8 reserved_at_60[0x20]; 5946 }; 5947 5948 struct mlx5_ifc_detach_from_mcg_out_bits { 5949 u8 status[0x8]; 5950 u8 reserved_at_8[0x18]; 5951 5952 u8 syndrome[0x20]; 5953 5954 u8 reserved_at_40[0x40]; 5955 }; 5956 5957 struct mlx5_ifc_detach_from_mcg_in_bits { 5958 u8 opcode[0x10]; 5959 u8 reserved_at_10[0x10]; 5960 5961 u8 reserved_at_20[0x10]; 5962 u8 op_mod[0x10]; 5963 5964 u8 reserved_at_40[0x8]; 5965 u8 qpn[0x18]; 5966 5967 u8 reserved_at_60[0x20]; 5968 5969 u8 multicast_gid[16][0x8]; 5970 }; 5971 5972 struct mlx5_ifc_destroy_xrq_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_at_8[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 reserved_at_40[0x40]; 5979 }; 5980 5981 struct mlx5_ifc_destroy_xrq_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_at_10[0x10]; 5984 5985 u8 reserved_at_20[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_at_40[0x8]; 5989 u8 xrqn[0x18]; 5990 5991 u8 reserved_at_60[0x20]; 5992 }; 5993 5994 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_at_8[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_at_40[0x40]; 6001 }; 6002 6003 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x8]; 6011 u8 xrc_srqn[0x18]; 6012 6013 u8 reserved_at_60[0x20]; 6014 }; 6015 6016 struct mlx5_ifc_destroy_tis_out_bits { 6017 u8 status[0x8]; 6018 u8 reserved_at_8[0x18]; 6019 6020 u8 syndrome[0x20]; 6021 6022 u8 reserved_at_40[0x40]; 6023 }; 6024 6025 struct mlx5_ifc_destroy_tis_in_bits { 6026 u8 opcode[0x10]; 6027 u8 reserved_at_10[0x10]; 6028 6029 u8 reserved_at_20[0x10]; 6030 u8 op_mod[0x10]; 6031 6032 u8 reserved_at_40[0x8]; 6033 u8 tisn[0x18]; 6034 6035 u8 reserved_at_60[0x20]; 6036 }; 6037 6038 struct mlx5_ifc_destroy_tir_out_bits { 6039 u8 status[0x8]; 6040 u8 reserved_at_8[0x18]; 6041 6042 u8 syndrome[0x20]; 6043 6044 u8 reserved_at_40[0x40]; 6045 }; 6046 6047 struct mlx5_ifc_destroy_tir_in_bits { 6048 u8 opcode[0x10]; 6049 u8 reserved_at_10[0x10]; 6050 6051 u8 reserved_at_20[0x10]; 6052 u8 op_mod[0x10]; 6053 6054 u8 reserved_at_40[0x8]; 6055 u8 tirn[0x18]; 6056 6057 u8 reserved_at_60[0x20]; 6058 }; 6059 6060 struct mlx5_ifc_destroy_srq_out_bits { 6061 u8 status[0x8]; 6062 u8 reserved_at_8[0x18]; 6063 6064 u8 syndrome[0x20]; 6065 6066 u8 reserved_at_40[0x40]; 6067 }; 6068 6069 struct mlx5_ifc_destroy_srq_in_bits { 6070 u8 opcode[0x10]; 6071 u8 reserved_at_10[0x10]; 6072 6073 u8 reserved_at_20[0x10]; 6074 u8 op_mod[0x10]; 6075 6076 u8 reserved_at_40[0x8]; 6077 u8 srqn[0x18]; 6078 6079 u8 reserved_at_60[0x20]; 6080 }; 6081 6082 struct mlx5_ifc_destroy_sq_out_bits { 6083 u8 status[0x8]; 6084 u8 reserved_at_8[0x18]; 6085 6086 u8 syndrome[0x20]; 6087 6088 u8 reserved_at_40[0x40]; 6089 }; 6090 6091 struct mlx5_ifc_destroy_sq_in_bits { 6092 u8 opcode[0x10]; 6093 u8 reserved_at_10[0x10]; 6094 6095 u8 reserved_at_20[0x10]; 6096 u8 op_mod[0x10]; 6097 6098 u8 reserved_at_40[0x8]; 6099 u8 sqn[0x18]; 6100 6101 u8 reserved_at_60[0x20]; 6102 }; 6103 6104 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6105 u8 status[0x8]; 6106 u8 reserved_at_8[0x18]; 6107 6108 u8 syndrome[0x20]; 6109 6110 u8 reserved_at_40[0x1c0]; 6111 }; 6112 6113 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6114 u8 opcode[0x10]; 6115 u8 reserved_at_10[0x10]; 6116 6117 u8 reserved_at_20[0x10]; 6118 u8 op_mod[0x10]; 6119 6120 u8 scheduling_hierarchy[0x8]; 6121 u8 reserved_at_48[0x18]; 6122 6123 u8 scheduling_element_id[0x20]; 6124 6125 u8 reserved_at_80[0x180]; 6126 }; 6127 6128 struct mlx5_ifc_destroy_rqt_out_bits { 6129 u8 status[0x8]; 6130 u8 reserved_at_8[0x18]; 6131 6132 u8 syndrome[0x20]; 6133 6134 u8 reserved_at_40[0x40]; 6135 }; 6136 6137 struct mlx5_ifc_destroy_rqt_in_bits { 6138 u8 opcode[0x10]; 6139 u8 reserved_at_10[0x10]; 6140 6141 u8 reserved_at_20[0x10]; 6142 u8 op_mod[0x10]; 6143 6144 u8 reserved_at_40[0x8]; 6145 u8 rqtn[0x18]; 6146 6147 u8 reserved_at_60[0x20]; 6148 }; 6149 6150 struct mlx5_ifc_destroy_rq_out_bits { 6151 u8 status[0x8]; 6152 u8 reserved_at_8[0x18]; 6153 6154 u8 syndrome[0x20]; 6155 6156 u8 reserved_at_40[0x40]; 6157 }; 6158 6159 struct mlx5_ifc_destroy_rq_in_bits { 6160 u8 opcode[0x10]; 6161 u8 reserved_at_10[0x10]; 6162 6163 u8 reserved_at_20[0x10]; 6164 u8 op_mod[0x10]; 6165 6166 u8 reserved_at_40[0x8]; 6167 u8 rqn[0x18]; 6168 6169 u8 reserved_at_60[0x20]; 6170 }; 6171 6172 struct mlx5_ifc_set_delay_drop_params_in_bits { 6173 u8 opcode[0x10]; 6174 u8 reserved_at_10[0x10]; 6175 6176 u8 reserved_at_20[0x10]; 6177 u8 op_mod[0x10]; 6178 6179 u8 reserved_at_40[0x20]; 6180 6181 u8 reserved_at_60[0x10]; 6182 u8 delay_drop_timeout[0x10]; 6183 }; 6184 6185 struct mlx5_ifc_set_delay_drop_params_out_bits { 6186 u8 status[0x8]; 6187 u8 reserved_at_8[0x18]; 6188 6189 u8 syndrome[0x20]; 6190 6191 u8 reserved_at_40[0x40]; 6192 }; 6193 6194 struct mlx5_ifc_destroy_rmp_out_bits { 6195 u8 status[0x8]; 6196 u8 reserved_at_8[0x18]; 6197 6198 u8 syndrome[0x20]; 6199 6200 u8 reserved_at_40[0x40]; 6201 }; 6202 6203 struct mlx5_ifc_destroy_rmp_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_at_10[0x10]; 6206 6207 u8 reserved_at_20[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 reserved_at_40[0x8]; 6211 u8 rmpn[0x18]; 6212 6213 u8 reserved_at_60[0x20]; 6214 }; 6215 6216 struct mlx5_ifc_destroy_qp_out_bits { 6217 u8 status[0x8]; 6218 u8 reserved_at_8[0x18]; 6219 6220 u8 syndrome[0x20]; 6221 6222 u8 reserved_at_40[0x40]; 6223 }; 6224 6225 struct mlx5_ifc_destroy_qp_in_bits { 6226 u8 opcode[0x10]; 6227 u8 reserved_at_10[0x10]; 6228 6229 u8 reserved_at_20[0x10]; 6230 u8 op_mod[0x10]; 6231 6232 u8 reserved_at_40[0x8]; 6233 u8 qpn[0x18]; 6234 6235 u8 reserved_at_60[0x20]; 6236 }; 6237 6238 struct mlx5_ifc_destroy_psv_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 }; 6246 6247 struct mlx5_ifc_destroy_psv_in_bits { 6248 u8 opcode[0x10]; 6249 u8 reserved_at_10[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 reserved_at_40[0x8]; 6255 u8 psvn[0x18]; 6256 6257 u8 reserved_at_60[0x20]; 6258 }; 6259 6260 struct mlx5_ifc_destroy_mkey_out_bits { 6261 u8 status[0x8]; 6262 u8 reserved_at_8[0x18]; 6263 6264 u8 syndrome[0x20]; 6265 6266 u8 reserved_at_40[0x40]; 6267 }; 6268 6269 struct mlx5_ifc_destroy_mkey_in_bits { 6270 u8 opcode[0x10]; 6271 u8 reserved_at_10[0x10]; 6272 6273 u8 reserved_at_20[0x10]; 6274 u8 op_mod[0x10]; 6275 6276 u8 reserved_at_40[0x8]; 6277 u8 mkey_index[0x18]; 6278 6279 u8 reserved_at_60[0x20]; 6280 }; 6281 6282 struct mlx5_ifc_destroy_flow_table_out_bits { 6283 u8 status[0x8]; 6284 u8 reserved_at_8[0x18]; 6285 6286 u8 syndrome[0x20]; 6287 6288 u8 reserved_at_40[0x40]; 6289 }; 6290 6291 struct mlx5_ifc_destroy_flow_table_in_bits { 6292 u8 opcode[0x10]; 6293 u8 reserved_at_10[0x10]; 6294 6295 u8 reserved_at_20[0x10]; 6296 u8 op_mod[0x10]; 6297 6298 u8 other_vport[0x1]; 6299 u8 reserved_at_41[0xf]; 6300 u8 vport_number[0x10]; 6301 6302 u8 reserved_at_60[0x20]; 6303 6304 u8 table_type[0x8]; 6305 u8 reserved_at_88[0x18]; 6306 6307 u8 reserved_at_a0[0x8]; 6308 u8 table_id[0x18]; 6309 6310 u8 reserved_at_c0[0x140]; 6311 }; 6312 6313 struct mlx5_ifc_destroy_flow_group_out_bits { 6314 u8 status[0x8]; 6315 u8 reserved_at_8[0x18]; 6316 6317 u8 syndrome[0x20]; 6318 6319 u8 reserved_at_40[0x40]; 6320 }; 6321 6322 struct mlx5_ifc_destroy_flow_group_in_bits { 6323 u8 opcode[0x10]; 6324 u8 reserved_at_10[0x10]; 6325 6326 u8 reserved_at_20[0x10]; 6327 u8 op_mod[0x10]; 6328 6329 u8 other_vport[0x1]; 6330 u8 reserved_at_41[0xf]; 6331 u8 vport_number[0x10]; 6332 6333 u8 reserved_at_60[0x20]; 6334 6335 u8 table_type[0x8]; 6336 u8 reserved_at_88[0x18]; 6337 6338 u8 reserved_at_a0[0x8]; 6339 u8 table_id[0x18]; 6340 6341 u8 group_id[0x20]; 6342 6343 u8 reserved_at_e0[0x120]; 6344 }; 6345 6346 struct mlx5_ifc_destroy_eq_out_bits { 6347 u8 status[0x8]; 6348 u8 reserved_at_8[0x18]; 6349 6350 u8 syndrome[0x20]; 6351 6352 u8 reserved_at_40[0x40]; 6353 }; 6354 6355 struct mlx5_ifc_destroy_eq_in_bits { 6356 u8 opcode[0x10]; 6357 u8 reserved_at_10[0x10]; 6358 6359 u8 reserved_at_20[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 reserved_at_40[0x18]; 6363 u8 eq_number[0x8]; 6364 6365 u8 reserved_at_60[0x20]; 6366 }; 6367 6368 struct mlx5_ifc_destroy_dct_out_bits { 6369 u8 status[0x8]; 6370 u8 reserved_at_8[0x18]; 6371 6372 u8 syndrome[0x20]; 6373 6374 u8 reserved_at_40[0x40]; 6375 }; 6376 6377 struct mlx5_ifc_destroy_dct_in_bits { 6378 u8 opcode[0x10]; 6379 u8 reserved_at_10[0x10]; 6380 6381 u8 reserved_at_20[0x10]; 6382 u8 op_mod[0x10]; 6383 6384 u8 reserved_at_40[0x8]; 6385 u8 dctn[0x18]; 6386 6387 u8 reserved_at_60[0x20]; 6388 }; 6389 6390 struct mlx5_ifc_destroy_cq_out_bits { 6391 u8 status[0x8]; 6392 u8 reserved_at_8[0x18]; 6393 6394 u8 syndrome[0x20]; 6395 6396 u8 reserved_at_40[0x40]; 6397 }; 6398 6399 struct mlx5_ifc_destroy_cq_in_bits { 6400 u8 opcode[0x10]; 6401 u8 reserved_at_10[0x10]; 6402 6403 u8 reserved_at_20[0x10]; 6404 u8 op_mod[0x10]; 6405 6406 u8 reserved_at_40[0x8]; 6407 u8 cqn[0x18]; 6408 6409 u8 reserved_at_60[0x20]; 6410 }; 6411 6412 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6413 u8 status[0x8]; 6414 u8 reserved_at_8[0x18]; 6415 6416 u8 syndrome[0x20]; 6417 6418 u8 reserved_at_40[0x40]; 6419 }; 6420 6421 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6422 u8 opcode[0x10]; 6423 u8 reserved_at_10[0x10]; 6424 6425 u8 reserved_at_20[0x10]; 6426 u8 op_mod[0x10]; 6427 6428 u8 reserved_at_40[0x20]; 6429 6430 u8 reserved_at_60[0x10]; 6431 u8 vxlan_udp_port[0x10]; 6432 }; 6433 6434 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6435 u8 status[0x8]; 6436 u8 reserved_at_8[0x18]; 6437 6438 u8 syndrome[0x20]; 6439 6440 u8 reserved_at_40[0x40]; 6441 }; 6442 6443 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6444 u8 opcode[0x10]; 6445 u8 reserved_at_10[0x10]; 6446 6447 u8 reserved_at_20[0x10]; 6448 u8 op_mod[0x10]; 6449 6450 u8 reserved_at_40[0x60]; 6451 6452 u8 reserved_at_a0[0x8]; 6453 u8 table_index[0x18]; 6454 6455 u8 reserved_at_c0[0x140]; 6456 }; 6457 6458 struct mlx5_ifc_delete_fte_out_bits { 6459 u8 status[0x8]; 6460 u8 reserved_at_8[0x18]; 6461 6462 u8 syndrome[0x20]; 6463 6464 u8 reserved_at_40[0x40]; 6465 }; 6466 6467 struct mlx5_ifc_delete_fte_in_bits { 6468 u8 opcode[0x10]; 6469 u8 reserved_at_10[0x10]; 6470 6471 u8 reserved_at_20[0x10]; 6472 u8 op_mod[0x10]; 6473 6474 u8 other_vport[0x1]; 6475 u8 reserved_at_41[0xf]; 6476 u8 vport_number[0x10]; 6477 6478 u8 reserved_at_60[0x20]; 6479 6480 u8 table_type[0x8]; 6481 u8 reserved_at_88[0x18]; 6482 6483 u8 reserved_at_a0[0x8]; 6484 u8 table_id[0x18]; 6485 6486 u8 reserved_at_c0[0x40]; 6487 6488 u8 flow_index[0x20]; 6489 6490 u8 reserved_at_120[0xe0]; 6491 }; 6492 6493 struct mlx5_ifc_dealloc_xrcd_out_bits { 6494 u8 status[0x8]; 6495 u8 reserved_at_8[0x18]; 6496 6497 u8 syndrome[0x20]; 6498 6499 u8 reserved_at_40[0x40]; 6500 }; 6501 6502 struct mlx5_ifc_dealloc_xrcd_in_bits { 6503 u8 opcode[0x10]; 6504 u8 reserved_at_10[0x10]; 6505 6506 u8 reserved_at_20[0x10]; 6507 u8 op_mod[0x10]; 6508 6509 u8 reserved_at_40[0x8]; 6510 u8 xrcd[0x18]; 6511 6512 u8 reserved_at_60[0x20]; 6513 }; 6514 6515 struct mlx5_ifc_dealloc_uar_out_bits { 6516 u8 status[0x8]; 6517 u8 reserved_at_8[0x18]; 6518 6519 u8 syndrome[0x20]; 6520 6521 u8 reserved_at_40[0x40]; 6522 }; 6523 6524 struct mlx5_ifc_dealloc_uar_in_bits { 6525 u8 opcode[0x10]; 6526 u8 reserved_at_10[0x10]; 6527 6528 u8 reserved_at_20[0x10]; 6529 u8 op_mod[0x10]; 6530 6531 u8 reserved_at_40[0x8]; 6532 u8 uar[0x18]; 6533 6534 u8 reserved_at_60[0x20]; 6535 }; 6536 6537 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6538 u8 status[0x8]; 6539 u8 reserved_at_8[0x18]; 6540 6541 u8 syndrome[0x20]; 6542 6543 u8 reserved_at_40[0x40]; 6544 }; 6545 6546 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6547 u8 opcode[0x10]; 6548 u8 reserved_at_10[0x10]; 6549 6550 u8 reserved_at_20[0x10]; 6551 u8 op_mod[0x10]; 6552 6553 u8 reserved_at_40[0x8]; 6554 u8 transport_domain[0x18]; 6555 6556 u8 reserved_at_60[0x20]; 6557 }; 6558 6559 struct mlx5_ifc_dealloc_q_counter_out_bits { 6560 u8 status[0x8]; 6561 u8 reserved_at_8[0x18]; 6562 6563 u8 syndrome[0x20]; 6564 6565 u8 reserved_at_40[0x40]; 6566 }; 6567 6568 struct mlx5_ifc_dealloc_q_counter_in_bits { 6569 u8 opcode[0x10]; 6570 u8 reserved_at_10[0x10]; 6571 6572 u8 reserved_at_20[0x10]; 6573 u8 op_mod[0x10]; 6574 6575 u8 reserved_at_40[0x18]; 6576 u8 counter_set_id[0x8]; 6577 6578 u8 reserved_at_60[0x20]; 6579 }; 6580 6581 struct mlx5_ifc_dealloc_pd_out_bits { 6582 u8 status[0x8]; 6583 u8 reserved_at_8[0x18]; 6584 6585 u8 syndrome[0x20]; 6586 6587 u8 reserved_at_40[0x40]; 6588 }; 6589 6590 struct mlx5_ifc_dealloc_pd_in_bits { 6591 u8 opcode[0x10]; 6592 u8 reserved_at_10[0x10]; 6593 6594 u8 reserved_at_20[0x10]; 6595 u8 op_mod[0x10]; 6596 6597 u8 reserved_at_40[0x8]; 6598 u8 pd[0x18]; 6599 6600 u8 reserved_at_60[0x20]; 6601 }; 6602 6603 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6604 u8 status[0x8]; 6605 u8 reserved_at_8[0x18]; 6606 6607 u8 syndrome[0x20]; 6608 6609 u8 reserved_at_40[0x40]; 6610 }; 6611 6612 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6613 u8 opcode[0x10]; 6614 u8 reserved_at_10[0x10]; 6615 6616 u8 reserved_at_20[0x10]; 6617 u8 op_mod[0x10]; 6618 6619 u8 flow_counter_id[0x20]; 6620 6621 u8 reserved_at_60[0x20]; 6622 }; 6623 6624 struct mlx5_ifc_create_xrq_out_bits { 6625 u8 status[0x8]; 6626 u8 reserved_at_8[0x18]; 6627 6628 u8 syndrome[0x20]; 6629 6630 u8 reserved_at_40[0x8]; 6631 u8 xrqn[0x18]; 6632 6633 u8 reserved_at_60[0x20]; 6634 }; 6635 6636 struct mlx5_ifc_create_xrq_in_bits { 6637 u8 opcode[0x10]; 6638 u8 reserved_at_10[0x10]; 6639 6640 u8 reserved_at_20[0x10]; 6641 u8 op_mod[0x10]; 6642 6643 u8 reserved_at_40[0x40]; 6644 6645 struct mlx5_ifc_xrqc_bits xrq_context; 6646 }; 6647 6648 struct mlx5_ifc_create_xrc_srq_out_bits { 6649 u8 status[0x8]; 6650 u8 reserved_at_8[0x18]; 6651 6652 u8 syndrome[0x20]; 6653 6654 u8 reserved_at_40[0x8]; 6655 u8 xrc_srqn[0x18]; 6656 6657 u8 reserved_at_60[0x20]; 6658 }; 6659 6660 struct mlx5_ifc_create_xrc_srq_in_bits { 6661 u8 opcode[0x10]; 6662 u8 reserved_at_10[0x10]; 6663 6664 u8 reserved_at_20[0x10]; 6665 u8 op_mod[0x10]; 6666 6667 u8 reserved_at_40[0x40]; 6668 6669 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6670 6671 u8 reserved_at_280[0x600]; 6672 6673 u8 pas[0][0x40]; 6674 }; 6675 6676 struct mlx5_ifc_create_tis_out_bits { 6677 u8 status[0x8]; 6678 u8 reserved_at_8[0x18]; 6679 6680 u8 syndrome[0x20]; 6681 6682 u8 reserved_at_40[0x8]; 6683 u8 tisn[0x18]; 6684 6685 u8 reserved_at_60[0x20]; 6686 }; 6687 6688 struct mlx5_ifc_create_tis_in_bits { 6689 u8 opcode[0x10]; 6690 u8 reserved_at_10[0x10]; 6691 6692 u8 reserved_at_20[0x10]; 6693 u8 op_mod[0x10]; 6694 6695 u8 reserved_at_40[0xc0]; 6696 6697 struct mlx5_ifc_tisc_bits ctx; 6698 }; 6699 6700 struct mlx5_ifc_create_tir_out_bits { 6701 u8 status[0x8]; 6702 u8 reserved_at_8[0x18]; 6703 6704 u8 syndrome[0x20]; 6705 6706 u8 reserved_at_40[0x8]; 6707 u8 tirn[0x18]; 6708 6709 u8 reserved_at_60[0x20]; 6710 }; 6711 6712 struct mlx5_ifc_create_tir_in_bits { 6713 u8 opcode[0x10]; 6714 u8 reserved_at_10[0x10]; 6715 6716 u8 reserved_at_20[0x10]; 6717 u8 op_mod[0x10]; 6718 6719 u8 reserved_at_40[0xc0]; 6720 6721 struct mlx5_ifc_tirc_bits ctx; 6722 }; 6723 6724 struct mlx5_ifc_create_srq_out_bits { 6725 u8 status[0x8]; 6726 u8 reserved_at_8[0x18]; 6727 6728 u8 syndrome[0x20]; 6729 6730 u8 reserved_at_40[0x8]; 6731 u8 srqn[0x18]; 6732 6733 u8 reserved_at_60[0x20]; 6734 }; 6735 6736 struct mlx5_ifc_create_srq_in_bits { 6737 u8 opcode[0x10]; 6738 u8 reserved_at_10[0x10]; 6739 6740 u8 reserved_at_20[0x10]; 6741 u8 op_mod[0x10]; 6742 6743 u8 reserved_at_40[0x40]; 6744 6745 struct mlx5_ifc_srqc_bits srq_context_entry; 6746 6747 u8 reserved_at_280[0x600]; 6748 6749 u8 pas[0][0x40]; 6750 }; 6751 6752 struct mlx5_ifc_create_sq_out_bits { 6753 u8 status[0x8]; 6754 u8 reserved_at_8[0x18]; 6755 6756 u8 syndrome[0x20]; 6757 6758 u8 reserved_at_40[0x8]; 6759 u8 sqn[0x18]; 6760 6761 u8 reserved_at_60[0x20]; 6762 }; 6763 6764 struct mlx5_ifc_create_sq_in_bits { 6765 u8 opcode[0x10]; 6766 u8 reserved_at_10[0x10]; 6767 6768 u8 reserved_at_20[0x10]; 6769 u8 op_mod[0x10]; 6770 6771 u8 reserved_at_40[0xc0]; 6772 6773 struct mlx5_ifc_sqc_bits ctx; 6774 }; 6775 6776 struct mlx5_ifc_create_scheduling_element_out_bits { 6777 u8 status[0x8]; 6778 u8 reserved_at_8[0x18]; 6779 6780 u8 syndrome[0x20]; 6781 6782 u8 reserved_at_40[0x40]; 6783 6784 u8 scheduling_element_id[0x20]; 6785 6786 u8 reserved_at_a0[0x160]; 6787 }; 6788 6789 struct mlx5_ifc_create_scheduling_element_in_bits { 6790 u8 opcode[0x10]; 6791 u8 reserved_at_10[0x10]; 6792 6793 u8 reserved_at_20[0x10]; 6794 u8 op_mod[0x10]; 6795 6796 u8 scheduling_hierarchy[0x8]; 6797 u8 reserved_at_48[0x18]; 6798 6799 u8 reserved_at_60[0xa0]; 6800 6801 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6802 6803 u8 reserved_at_300[0x100]; 6804 }; 6805 6806 struct mlx5_ifc_create_rqt_out_bits { 6807 u8 status[0x8]; 6808 u8 reserved_at_8[0x18]; 6809 6810 u8 syndrome[0x20]; 6811 6812 u8 reserved_at_40[0x8]; 6813 u8 rqtn[0x18]; 6814 6815 u8 reserved_at_60[0x20]; 6816 }; 6817 6818 struct mlx5_ifc_create_rqt_in_bits { 6819 u8 opcode[0x10]; 6820 u8 reserved_at_10[0x10]; 6821 6822 u8 reserved_at_20[0x10]; 6823 u8 op_mod[0x10]; 6824 6825 u8 reserved_at_40[0xc0]; 6826 6827 struct mlx5_ifc_rqtc_bits rqt_context; 6828 }; 6829 6830 struct mlx5_ifc_create_rq_out_bits { 6831 u8 status[0x8]; 6832 u8 reserved_at_8[0x18]; 6833 6834 u8 syndrome[0x20]; 6835 6836 u8 reserved_at_40[0x8]; 6837 u8 rqn[0x18]; 6838 6839 u8 reserved_at_60[0x20]; 6840 }; 6841 6842 struct mlx5_ifc_create_rq_in_bits { 6843 u8 opcode[0x10]; 6844 u8 reserved_at_10[0x10]; 6845 6846 u8 reserved_at_20[0x10]; 6847 u8 op_mod[0x10]; 6848 6849 u8 reserved_at_40[0xc0]; 6850 6851 struct mlx5_ifc_rqc_bits ctx; 6852 }; 6853 6854 struct mlx5_ifc_create_rmp_out_bits { 6855 u8 status[0x8]; 6856 u8 reserved_at_8[0x18]; 6857 6858 u8 syndrome[0x20]; 6859 6860 u8 reserved_at_40[0x8]; 6861 u8 rmpn[0x18]; 6862 6863 u8 reserved_at_60[0x20]; 6864 }; 6865 6866 struct mlx5_ifc_create_rmp_in_bits { 6867 u8 opcode[0x10]; 6868 u8 reserved_at_10[0x10]; 6869 6870 u8 reserved_at_20[0x10]; 6871 u8 op_mod[0x10]; 6872 6873 u8 reserved_at_40[0xc0]; 6874 6875 struct mlx5_ifc_rmpc_bits ctx; 6876 }; 6877 6878 struct mlx5_ifc_create_qp_out_bits { 6879 u8 status[0x8]; 6880 u8 reserved_at_8[0x18]; 6881 6882 u8 syndrome[0x20]; 6883 6884 u8 reserved_at_40[0x8]; 6885 u8 qpn[0x18]; 6886 6887 u8 reserved_at_60[0x20]; 6888 }; 6889 6890 struct mlx5_ifc_create_qp_in_bits { 6891 u8 opcode[0x10]; 6892 u8 reserved_at_10[0x10]; 6893 6894 u8 reserved_at_20[0x10]; 6895 u8 op_mod[0x10]; 6896 6897 u8 reserved_at_40[0x40]; 6898 6899 u8 opt_param_mask[0x20]; 6900 6901 u8 reserved_at_a0[0x20]; 6902 6903 struct mlx5_ifc_qpc_bits qpc; 6904 6905 u8 reserved_at_800[0x80]; 6906 6907 u8 pas[0][0x40]; 6908 }; 6909 6910 struct mlx5_ifc_create_psv_out_bits { 6911 u8 status[0x8]; 6912 u8 reserved_at_8[0x18]; 6913 6914 u8 syndrome[0x20]; 6915 6916 u8 reserved_at_40[0x40]; 6917 6918 u8 reserved_at_80[0x8]; 6919 u8 psv0_index[0x18]; 6920 6921 u8 reserved_at_a0[0x8]; 6922 u8 psv1_index[0x18]; 6923 6924 u8 reserved_at_c0[0x8]; 6925 u8 psv2_index[0x18]; 6926 6927 u8 reserved_at_e0[0x8]; 6928 u8 psv3_index[0x18]; 6929 }; 6930 6931 struct mlx5_ifc_create_psv_in_bits { 6932 u8 opcode[0x10]; 6933 u8 reserved_at_10[0x10]; 6934 6935 u8 reserved_at_20[0x10]; 6936 u8 op_mod[0x10]; 6937 6938 u8 num_psv[0x4]; 6939 u8 reserved_at_44[0x4]; 6940 u8 pd[0x18]; 6941 6942 u8 reserved_at_60[0x20]; 6943 }; 6944 6945 struct mlx5_ifc_create_mkey_out_bits { 6946 u8 status[0x8]; 6947 u8 reserved_at_8[0x18]; 6948 6949 u8 syndrome[0x20]; 6950 6951 u8 reserved_at_40[0x8]; 6952 u8 mkey_index[0x18]; 6953 6954 u8 reserved_at_60[0x20]; 6955 }; 6956 6957 struct mlx5_ifc_create_mkey_in_bits { 6958 u8 opcode[0x10]; 6959 u8 reserved_at_10[0x10]; 6960 6961 u8 reserved_at_20[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 reserved_at_40[0x20]; 6965 6966 u8 pg_access[0x1]; 6967 u8 reserved_at_61[0x1f]; 6968 6969 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6970 6971 u8 reserved_at_280[0x80]; 6972 6973 u8 translations_octword_actual_size[0x20]; 6974 6975 u8 reserved_at_320[0x560]; 6976 6977 u8 klm_pas_mtt[0][0x20]; 6978 }; 6979 6980 struct mlx5_ifc_create_flow_table_out_bits { 6981 u8 status[0x8]; 6982 u8 reserved_at_8[0x18]; 6983 6984 u8 syndrome[0x20]; 6985 6986 u8 reserved_at_40[0x8]; 6987 u8 table_id[0x18]; 6988 6989 u8 reserved_at_60[0x20]; 6990 }; 6991 6992 struct mlx5_ifc_flow_table_context_bits { 6993 u8 encap_en[0x1]; 6994 u8 decap_en[0x1]; 6995 u8 reserved_at_2[0x2]; 6996 u8 table_miss_action[0x4]; 6997 u8 level[0x8]; 6998 u8 reserved_at_10[0x8]; 6999 u8 log_size[0x8]; 7000 7001 u8 reserved_at_20[0x8]; 7002 u8 table_miss_id[0x18]; 7003 7004 u8 reserved_at_40[0x8]; 7005 u8 lag_master_next_table_id[0x18]; 7006 7007 u8 reserved_at_60[0xe0]; 7008 }; 7009 7010 struct mlx5_ifc_create_flow_table_in_bits { 7011 u8 opcode[0x10]; 7012 u8 reserved_at_10[0x10]; 7013 7014 u8 reserved_at_20[0x10]; 7015 u8 op_mod[0x10]; 7016 7017 u8 other_vport[0x1]; 7018 u8 reserved_at_41[0xf]; 7019 u8 vport_number[0x10]; 7020 7021 u8 reserved_at_60[0x20]; 7022 7023 u8 table_type[0x8]; 7024 u8 reserved_at_88[0x18]; 7025 7026 u8 reserved_at_a0[0x20]; 7027 7028 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7029 }; 7030 7031 struct mlx5_ifc_create_flow_group_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x8]; 7038 u8 group_id[0x18]; 7039 7040 u8 reserved_at_60[0x20]; 7041 }; 7042 7043 enum { 7044 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7045 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7046 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7047 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7048 }; 7049 7050 struct mlx5_ifc_create_flow_group_in_bits { 7051 u8 opcode[0x10]; 7052 u8 reserved_at_10[0x10]; 7053 7054 u8 reserved_at_20[0x10]; 7055 u8 op_mod[0x10]; 7056 7057 u8 other_vport[0x1]; 7058 u8 reserved_at_41[0xf]; 7059 u8 vport_number[0x10]; 7060 7061 u8 reserved_at_60[0x20]; 7062 7063 u8 table_type[0x8]; 7064 u8 reserved_at_88[0x18]; 7065 7066 u8 reserved_at_a0[0x8]; 7067 u8 table_id[0x18]; 7068 7069 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7070 7071 u8 reserved_at_c1[0x1f]; 7072 7073 u8 start_flow_index[0x20]; 7074 7075 u8 reserved_at_100[0x20]; 7076 7077 u8 end_flow_index[0x20]; 7078 7079 u8 reserved_at_140[0xa0]; 7080 7081 u8 reserved_at_1e0[0x18]; 7082 u8 match_criteria_enable[0x8]; 7083 7084 struct mlx5_ifc_fte_match_param_bits match_criteria; 7085 7086 u8 reserved_at_1200[0xe00]; 7087 }; 7088 7089 struct mlx5_ifc_create_eq_out_bits { 7090 u8 status[0x8]; 7091 u8 reserved_at_8[0x18]; 7092 7093 u8 syndrome[0x20]; 7094 7095 u8 reserved_at_40[0x18]; 7096 u8 eq_number[0x8]; 7097 7098 u8 reserved_at_60[0x20]; 7099 }; 7100 7101 struct mlx5_ifc_create_eq_in_bits { 7102 u8 opcode[0x10]; 7103 u8 reserved_at_10[0x10]; 7104 7105 u8 reserved_at_20[0x10]; 7106 u8 op_mod[0x10]; 7107 7108 u8 reserved_at_40[0x40]; 7109 7110 struct mlx5_ifc_eqc_bits eq_context_entry; 7111 7112 u8 reserved_at_280[0x40]; 7113 7114 u8 event_bitmask[0x40]; 7115 7116 u8 reserved_at_300[0x580]; 7117 7118 u8 pas[0][0x40]; 7119 }; 7120 7121 struct mlx5_ifc_create_dct_out_bits { 7122 u8 status[0x8]; 7123 u8 reserved_at_8[0x18]; 7124 7125 u8 syndrome[0x20]; 7126 7127 u8 reserved_at_40[0x8]; 7128 u8 dctn[0x18]; 7129 7130 u8 reserved_at_60[0x20]; 7131 }; 7132 7133 struct mlx5_ifc_create_dct_in_bits { 7134 u8 opcode[0x10]; 7135 u8 reserved_at_10[0x10]; 7136 7137 u8 reserved_at_20[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 reserved_at_40[0x40]; 7141 7142 struct mlx5_ifc_dctc_bits dct_context_entry; 7143 7144 u8 reserved_at_280[0x180]; 7145 }; 7146 7147 struct mlx5_ifc_create_cq_out_bits { 7148 u8 status[0x8]; 7149 u8 reserved_at_8[0x18]; 7150 7151 u8 syndrome[0x20]; 7152 7153 u8 reserved_at_40[0x8]; 7154 u8 cqn[0x18]; 7155 7156 u8 reserved_at_60[0x20]; 7157 }; 7158 7159 struct mlx5_ifc_create_cq_in_bits { 7160 u8 opcode[0x10]; 7161 u8 reserved_at_10[0x10]; 7162 7163 u8 reserved_at_20[0x10]; 7164 u8 op_mod[0x10]; 7165 7166 u8 reserved_at_40[0x40]; 7167 7168 struct mlx5_ifc_cqc_bits cq_context; 7169 7170 u8 reserved_at_280[0x600]; 7171 7172 u8 pas[0][0x40]; 7173 }; 7174 7175 struct mlx5_ifc_config_int_moderation_out_bits { 7176 u8 status[0x8]; 7177 u8 reserved_at_8[0x18]; 7178 7179 u8 syndrome[0x20]; 7180 7181 u8 reserved_at_40[0x4]; 7182 u8 min_delay[0xc]; 7183 u8 int_vector[0x10]; 7184 7185 u8 reserved_at_60[0x20]; 7186 }; 7187 7188 enum { 7189 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7190 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7191 }; 7192 7193 struct mlx5_ifc_config_int_moderation_in_bits { 7194 u8 opcode[0x10]; 7195 u8 reserved_at_10[0x10]; 7196 7197 u8 reserved_at_20[0x10]; 7198 u8 op_mod[0x10]; 7199 7200 u8 reserved_at_40[0x4]; 7201 u8 min_delay[0xc]; 7202 u8 int_vector[0x10]; 7203 7204 u8 reserved_at_60[0x20]; 7205 }; 7206 7207 struct mlx5_ifc_attach_to_mcg_out_bits { 7208 u8 status[0x8]; 7209 u8 reserved_at_8[0x18]; 7210 7211 u8 syndrome[0x20]; 7212 7213 u8 reserved_at_40[0x40]; 7214 }; 7215 7216 struct mlx5_ifc_attach_to_mcg_in_bits { 7217 u8 opcode[0x10]; 7218 u8 reserved_at_10[0x10]; 7219 7220 u8 reserved_at_20[0x10]; 7221 u8 op_mod[0x10]; 7222 7223 u8 reserved_at_40[0x8]; 7224 u8 qpn[0x18]; 7225 7226 u8 reserved_at_60[0x20]; 7227 7228 u8 multicast_gid[16][0x8]; 7229 }; 7230 7231 struct mlx5_ifc_arm_xrq_out_bits { 7232 u8 status[0x8]; 7233 u8 reserved_at_8[0x18]; 7234 7235 u8 syndrome[0x20]; 7236 7237 u8 reserved_at_40[0x40]; 7238 }; 7239 7240 struct mlx5_ifc_arm_xrq_in_bits { 7241 u8 opcode[0x10]; 7242 u8 reserved_at_10[0x10]; 7243 7244 u8 reserved_at_20[0x10]; 7245 u8 op_mod[0x10]; 7246 7247 u8 reserved_at_40[0x8]; 7248 u8 xrqn[0x18]; 7249 7250 u8 reserved_at_60[0x10]; 7251 u8 lwm[0x10]; 7252 }; 7253 7254 struct mlx5_ifc_arm_xrc_srq_out_bits { 7255 u8 status[0x8]; 7256 u8 reserved_at_8[0x18]; 7257 7258 u8 syndrome[0x20]; 7259 7260 u8 reserved_at_40[0x40]; 7261 }; 7262 7263 enum { 7264 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7265 }; 7266 7267 struct mlx5_ifc_arm_xrc_srq_in_bits { 7268 u8 opcode[0x10]; 7269 u8 reserved_at_10[0x10]; 7270 7271 u8 reserved_at_20[0x10]; 7272 u8 op_mod[0x10]; 7273 7274 u8 reserved_at_40[0x8]; 7275 u8 xrc_srqn[0x18]; 7276 7277 u8 reserved_at_60[0x10]; 7278 u8 lwm[0x10]; 7279 }; 7280 7281 struct mlx5_ifc_arm_rq_out_bits { 7282 u8 status[0x8]; 7283 u8 reserved_at_8[0x18]; 7284 7285 u8 syndrome[0x20]; 7286 7287 u8 reserved_at_40[0x40]; 7288 }; 7289 7290 enum { 7291 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7292 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7293 }; 7294 7295 struct mlx5_ifc_arm_rq_in_bits { 7296 u8 opcode[0x10]; 7297 u8 reserved_at_10[0x10]; 7298 7299 u8 reserved_at_20[0x10]; 7300 u8 op_mod[0x10]; 7301 7302 u8 reserved_at_40[0x8]; 7303 u8 srq_number[0x18]; 7304 7305 u8 reserved_at_60[0x10]; 7306 u8 lwm[0x10]; 7307 }; 7308 7309 struct mlx5_ifc_arm_dct_out_bits { 7310 u8 status[0x8]; 7311 u8 reserved_at_8[0x18]; 7312 7313 u8 syndrome[0x20]; 7314 7315 u8 reserved_at_40[0x40]; 7316 }; 7317 7318 struct mlx5_ifc_arm_dct_in_bits { 7319 u8 opcode[0x10]; 7320 u8 reserved_at_10[0x10]; 7321 7322 u8 reserved_at_20[0x10]; 7323 u8 op_mod[0x10]; 7324 7325 u8 reserved_at_40[0x8]; 7326 u8 dct_number[0x18]; 7327 7328 u8 reserved_at_60[0x20]; 7329 }; 7330 7331 struct mlx5_ifc_alloc_xrcd_out_bits { 7332 u8 status[0x8]; 7333 u8 reserved_at_8[0x18]; 7334 7335 u8 syndrome[0x20]; 7336 7337 u8 reserved_at_40[0x8]; 7338 u8 xrcd[0x18]; 7339 7340 u8 reserved_at_60[0x20]; 7341 }; 7342 7343 struct mlx5_ifc_alloc_xrcd_in_bits { 7344 u8 opcode[0x10]; 7345 u8 reserved_at_10[0x10]; 7346 7347 u8 reserved_at_20[0x10]; 7348 u8 op_mod[0x10]; 7349 7350 u8 reserved_at_40[0x40]; 7351 }; 7352 7353 struct mlx5_ifc_alloc_uar_out_bits { 7354 u8 status[0x8]; 7355 u8 reserved_at_8[0x18]; 7356 7357 u8 syndrome[0x20]; 7358 7359 u8 reserved_at_40[0x8]; 7360 u8 uar[0x18]; 7361 7362 u8 reserved_at_60[0x20]; 7363 }; 7364 7365 struct mlx5_ifc_alloc_uar_in_bits { 7366 u8 opcode[0x10]; 7367 u8 reserved_at_10[0x10]; 7368 7369 u8 reserved_at_20[0x10]; 7370 u8 op_mod[0x10]; 7371 7372 u8 reserved_at_40[0x40]; 7373 }; 7374 7375 struct mlx5_ifc_alloc_transport_domain_out_bits { 7376 u8 status[0x8]; 7377 u8 reserved_at_8[0x18]; 7378 7379 u8 syndrome[0x20]; 7380 7381 u8 reserved_at_40[0x8]; 7382 u8 transport_domain[0x18]; 7383 7384 u8 reserved_at_60[0x20]; 7385 }; 7386 7387 struct mlx5_ifc_alloc_transport_domain_in_bits { 7388 u8 opcode[0x10]; 7389 u8 reserved_at_10[0x10]; 7390 7391 u8 reserved_at_20[0x10]; 7392 u8 op_mod[0x10]; 7393 7394 u8 reserved_at_40[0x40]; 7395 }; 7396 7397 struct mlx5_ifc_alloc_q_counter_out_bits { 7398 u8 status[0x8]; 7399 u8 reserved_at_8[0x18]; 7400 7401 u8 syndrome[0x20]; 7402 7403 u8 reserved_at_40[0x18]; 7404 u8 counter_set_id[0x8]; 7405 7406 u8 reserved_at_60[0x20]; 7407 }; 7408 7409 struct mlx5_ifc_alloc_q_counter_in_bits { 7410 u8 opcode[0x10]; 7411 u8 reserved_at_10[0x10]; 7412 7413 u8 reserved_at_20[0x10]; 7414 u8 op_mod[0x10]; 7415 7416 u8 reserved_at_40[0x40]; 7417 }; 7418 7419 struct mlx5_ifc_alloc_pd_out_bits { 7420 u8 status[0x8]; 7421 u8 reserved_at_8[0x18]; 7422 7423 u8 syndrome[0x20]; 7424 7425 u8 reserved_at_40[0x8]; 7426 u8 pd[0x18]; 7427 7428 u8 reserved_at_60[0x20]; 7429 }; 7430 7431 struct mlx5_ifc_alloc_pd_in_bits { 7432 u8 opcode[0x10]; 7433 u8 reserved_at_10[0x10]; 7434 7435 u8 reserved_at_20[0x10]; 7436 u8 op_mod[0x10]; 7437 7438 u8 reserved_at_40[0x40]; 7439 }; 7440 7441 struct mlx5_ifc_alloc_flow_counter_out_bits { 7442 u8 status[0x8]; 7443 u8 reserved_at_8[0x18]; 7444 7445 u8 syndrome[0x20]; 7446 7447 u8 flow_counter_id[0x20]; 7448 7449 u8 reserved_at_60[0x20]; 7450 }; 7451 7452 struct mlx5_ifc_alloc_flow_counter_in_bits { 7453 u8 opcode[0x10]; 7454 u8 reserved_at_10[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_at_40[0x40]; 7460 }; 7461 7462 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7463 u8 status[0x8]; 7464 u8 reserved_at_8[0x18]; 7465 7466 u8 syndrome[0x20]; 7467 7468 u8 reserved_at_40[0x40]; 7469 }; 7470 7471 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7472 u8 opcode[0x10]; 7473 u8 reserved_at_10[0x10]; 7474 7475 u8 reserved_at_20[0x10]; 7476 u8 op_mod[0x10]; 7477 7478 u8 reserved_at_40[0x20]; 7479 7480 u8 reserved_at_60[0x10]; 7481 u8 vxlan_udp_port[0x10]; 7482 }; 7483 7484 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_at_8[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_at_40[0x40]; 7491 }; 7492 7493 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7494 u8 opcode[0x10]; 7495 u8 reserved_at_10[0x10]; 7496 7497 u8 reserved_at_20[0x10]; 7498 u8 op_mod[0x10]; 7499 7500 u8 reserved_at_40[0x10]; 7501 u8 rate_limit_index[0x10]; 7502 7503 u8 reserved_at_60[0x20]; 7504 7505 u8 rate_limit[0x20]; 7506 7507 u8 burst_upper_bound[0x20]; 7508 7509 u8 reserved_at_c0[0x10]; 7510 u8 typical_packet_size[0x10]; 7511 7512 u8 reserved_at_e0[0x120]; 7513 }; 7514 7515 struct mlx5_ifc_access_register_out_bits { 7516 u8 status[0x8]; 7517 u8 reserved_at_8[0x18]; 7518 7519 u8 syndrome[0x20]; 7520 7521 u8 reserved_at_40[0x40]; 7522 7523 u8 register_data[0][0x20]; 7524 }; 7525 7526 enum { 7527 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7528 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7529 }; 7530 7531 struct mlx5_ifc_access_register_in_bits { 7532 u8 opcode[0x10]; 7533 u8 reserved_at_10[0x10]; 7534 7535 u8 reserved_at_20[0x10]; 7536 u8 op_mod[0x10]; 7537 7538 u8 reserved_at_40[0x10]; 7539 u8 register_id[0x10]; 7540 7541 u8 argument[0x20]; 7542 7543 u8 register_data[0][0x20]; 7544 }; 7545 7546 struct mlx5_ifc_sltp_reg_bits { 7547 u8 status[0x4]; 7548 u8 version[0x4]; 7549 u8 local_port[0x8]; 7550 u8 pnat[0x2]; 7551 u8 reserved_at_12[0x2]; 7552 u8 lane[0x4]; 7553 u8 reserved_at_18[0x8]; 7554 7555 u8 reserved_at_20[0x20]; 7556 7557 u8 reserved_at_40[0x7]; 7558 u8 polarity[0x1]; 7559 u8 ob_tap0[0x8]; 7560 u8 ob_tap1[0x8]; 7561 u8 ob_tap2[0x8]; 7562 7563 u8 reserved_at_60[0xc]; 7564 u8 ob_preemp_mode[0x4]; 7565 u8 ob_reg[0x8]; 7566 u8 ob_bias[0x8]; 7567 7568 u8 reserved_at_80[0x20]; 7569 }; 7570 7571 struct mlx5_ifc_slrg_reg_bits { 7572 u8 status[0x4]; 7573 u8 version[0x4]; 7574 u8 local_port[0x8]; 7575 u8 pnat[0x2]; 7576 u8 reserved_at_12[0x2]; 7577 u8 lane[0x4]; 7578 u8 reserved_at_18[0x8]; 7579 7580 u8 time_to_link_up[0x10]; 7581 u8 reserved_at_30[0xc]; 7582 u8 grade_lane_speed[0x4]; 7583 7584 u8 grade_version[0x8]; 7585 u8 grade[0x18]; 7586 7587 u8 reserved_at_60[0x4]; 7588 u8 height_grade_type[0x4]; 7589 u8 height_grade[0x18]; 7590 7591 u8 height_dz[0x10]; 7592 u8 height_dv[0x10]; 7593 7594 u8 reserved_at_a0[0x10]; 7595 u8 height_sigma[0x10]; 7596 7597 u8 reserved_at_c0[0x20]; 7598 7599 u8 reserved_at_e0[0x4]; 7600 u8 phase_grade_type[0x4]; 7601 u8 phase_grade[0x18]; 7602 7603 u8 reserved_at_100[0x8]; 7604 u8 phase_eo_pos[0x8]; 7605 u8 reserved_at_110[0x8]; 7606 u8 phase_eo_neg[0x8]; 7607 7608 u8 ffe_set_tested[0x10]; 7609 u8 test_errors_per_lane[0x10]; 7610 }; 7611 7612 struct mlx5_ifc_pvlc_reg_bits { 7613 u8 reserved_at_0[0x8]; 7614 u8 local_port[0x8]; 7615 u8 reserved_at_10[0x10]; 7616 7617 u8 reserved_at_20[0x1c]; 7618 u8 vl_hw_cap[0x4]; 7619 7620 u8 reserved_at_40[0x1c]; 7621 u8 vl_admin[0x4]; 7622 7623 u8 reserved_at_60[0x1c]; 7624 u8 vl_operational[0x4]; 7625 }; 7626 7627 struct mlx5_ifc_pude_reg_bits { 7628 u8 swid[0x8]; 7629 u8 local_port[0x8]; 7630 u8 reserved_at_10[0x4]; 7631 u8 admin_status[0x4]; 7632 u8 reserved_at_18[0x4]; 7633 u8 oper_status[0x4]; 7634 7635 u8 reserved_at_20[0x60]; 7636 }; 7637 7638 struct mlx5_ifc_ptys_reg_bits { 7639 u8 reserved_at_0[0x1]; 7640 u8 an_disable_admin[0x1]; 7641 u8 an_disable_cap[0x1]; 7642 u8 reserved_at_3[0x5]; 7643 u8 local_port[0x8]; 7644 u8 reserved_at_10[0xd]; 7645 u8 proto_mask[0x3]; 7646 7647 u8 an_status[0x4]; 7648 u8 reserved_at_24[0x3c]; 7649 7650 u8 eth_proto_capability[0x20]; 7651 7652 u8 ib_link_width_capability[0x10]; 7653 u8 ib_proto_capability[0x10]; 7654 7655 u8 reserved_at_a0[0x20]; 7656 7657 u8 eth_proto_admin[0x20]; 7658 7659 u8 ib_link_width_admin[0x10]; 7660 u8 ib_proto_admin[0x10]; 7661 7662 u8 reserved_at_100[0x20]; 7663 7664 u8 eth_proto_oper[0x20]; 7665 7666 u8 ib_link_width_oper[0x10]; 7667 u8 ib_proto_oper[0x10]; 7668 7669 u8 reserved_at_160[0x1c]; 7670 u8 connector_type[0x4]; 7671 7672 u8 eth_proto_lp_advertise[0x20]; 7673 7674 u8 reserved_at_1a0[0x60]; 7675 }; 7676 7677 struct mlx5_ifc_mlcr_reg_bits { 7678 u8 reserved_at_0[0x8]; 7679 u8 local_port[0x8]; 7680 u8 reserved_at_10[0x20]; 7681 7682 u8 beacon_duration[0x10]; 7683 u8 reserved_at_40[0x10]; 7684 7685 u8 beacon_remain[0x10]; 7686 }; 7687 7688 struct mlx5_ifc_ptas_reg_bits { 7689 u8 reserved_at_0[0x20]; 7690 7691 u8 algorithm_options[0x10]; 7692 u8 reserved_at_30[0x4]; 7693 u8 repetitions_mode[0x4]; 7694 u8 num_of_repetitions[0x8]; 7695 7696 u8 grade_version[0x8]; 7697 u8 height_grade_type[0x4]; 7698 u8 phase_grade_type[0x4]; 7699 u8 height_grade_weight[0x8]; 7700 u8 phase_grade_weight[0x8]; 7701 7702 u8 gisim_measure_bits[0x10]; 7703 u8 adaptive_tap_measure_bits[0x10]; 7704 7705 u8 ber_bath_high_error_threshold[0x10]; 7706 u8 ber_bath_mid_error_threshold[0x10]; 7707 7708 u8 ber_bath_low_error_threshold[0x10]; 7709 u8 one_ratio_high_threshold[0x10]; 7710 7711 u8 one_ratio_high_mid_threshold[0x10]; 7712 u8 one_ratio_low_mid_threshold[0x10]; 7713 7714 u8 one_ratio_low_threshold[0x10]; 7715 u8 ndeo_error_threshold[0x10]; 7716 7717 u8 mixer_offset_step_size[0x10]; 7718 u8 reserved_at_110[0x8]; 7719 u8 mix90_phase_for_voltage_bath[0x8]; 7720 7721 u8 mixer_offset_start[0x10]; 7722 u8 mixer_offset_end[0x10]; 7723 7724 u8 reserved_at_140[0x15]; 7725 u8 ber_test_time[0xb]; 7726 }; 7727 7728 struct mlx5_ifc_pspa_reg_bits { 7729 u8 swid[0x8]; 7730 u8 local_port[0x8]; 7731 u8 sub_port[0x8]; 7732 u8 reserved_at_18[0x8]; 7733 7734 u8 reserved_at_20[0x20]; 7735 }; 7736 7737 struct mlx5_ifc_pqdr_reg_bits { 7738 u8 reserved_at_0[0x8]; 7739 u8 local_port[0x8]; 7740 u8 reserved_at_10[0x5]; 7741 u8 prio[0x3]; 7742 u8 reserved_at_18[0x6]; 7743 u8 mode[0x2]; 7744 7745 u8 reserved_at_20[0x20]; 7746 7747 u8 reserved_at_40[0x10]; 7748 u8 min_threshold[0x10]; 7749 7750 u8 reserved_at_60[0x10]; 7751 u8 max_threshold[0x10]; 7752 7753 u8 reserved_at_80[0x10]; 7754 u8 mark_probability_denominator[0x10]; 7755 7756 u8 reserved_at_a0[0x60]; 7757 }; 7758 7759 struct mlx5_ifc_ppsc_reg_bits { 7760 u8 reserved_at_0[0x8]; 7761 u8 local_port[0x8]; 7762 u8 reserved_at_10[0x10]; 7763 7764 u8 reserved_at_20[0x60]; 7765 7766 u8 reserved_at_80[0x1c]; 7767 u8 wrps_admin[0x4]; 7768 7769 u8 reserved_at_a0[0x1c]; 7770 u8 wrps_status[0x4]; 7771 7772 u8 reserved_at_c0[0x8]; 7773 u8 up_threshold[0x8]; 7774 u8 reserved_at_d0[0x8]; 7775 u8 down_threshold[0x8]; 7776 7777 u8 reserved_at_e0[0x20]; 7778 7779 u8 reserved_at_100[0x1c]; 7780 u8 srps_admin[0x4]; 7781 7782 u8 reserved_at_120[0x1c]; 7783 u8 srps_status[0x4]; 7784 7785 u8 reserved_at_140[0x40]; 7786 }; 7787 7788 struct mlx5_ifc_pplr_reg_bits { 7789 u8 reserved_at_0[0x8]; 7790 u8 local_port[0x8]; 7791 u8 reserved_at_10[0x10]; 7792 7793 u8 reserved_at_20[0x8]; 7794 u8 lb_cap[0x8]; 7795 u8 reserved_at_30[0x8]; 7796 u8 lb_en[0x8]; 7797 }; 7798 7799 struct mlx5_ifc_pplm_reg_bits { 7800 u8 reserved_at_0[0x8]; 7801 u8 local_port[0x8]; 7802 u8 reserved_at_10[0x10]; 7803 7804 u8 reserved_at_20[0x20]; 7805 7806 u8 port_profile_mode[0x8]; 7807 u8 static_port_profile[0x8]; 7808 u8 active_port_profile[0x8]; 7809 u8 reserved_at_58[0x8]; 7810 7811 u8 retransmission_active[0x8]; 7812 u8 fec_mode_active[0x18]; 7813 7814 u8 reserved_at_80[0x20]; 7815 }; 7816 7817 struct mlx5_ifc_ppcnt_reg_bits { 7818 u8 swid[0x8]; 7819 u8 local_port[0x8]; 7820 u8 pnat[0x2]; 7821 u8 reserved_at_12[0x8]; 7822 u8 grp[0x6]; 7823 7824 u8 clr[0x1]; 7825 u8 reserved_at_21[0x1c]; 7826 u8 prio_tc[0x3]; 7827 7828 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7829 }; 7830 7831 struct mlx5_ifc_mpcnt_reg_bits { 7832 u8 reserved_at_0[0x8]; 7833 u8 pcie_index[0x8]; 7834 u8 reserved_at_10[0xa]; 7835 u8 grp[0x6]; 7836 7837 u8 clr[0x1]; 7838 u8 reserved_at_21[0x1f]; 7839 7840 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7841 }; 7842 7843 struct mlx5_ifc_ppad_reg_bits { 7844 u8 reserved_at_0[0x3]; 7845 u8 single_mac[0x1]; 7846 u8 reserved_at_4[0x4]; 7847 u8 local_port[0x8]; 7848 u8 mac_47_32[0x10]; 7849 7850 u8 mac_31_0[0x20]; 7851 7852 u8 reserved_at_40[0x40]; 7853 }; 7854 7855 struct mlx5_ifc_pmtu_reg_bits { 7856 u8 reserved_at_0[0x8]; 7857 u8 local_port[0x8]; 7858 u8 reserved_at_10[0x10]; 7859 7860 u8 max_mtu[0x10]; 7861 u8 reserved_at_30[0x10]; 7862 7863 u8 admin_mtu[0x10]; 7864 u8 reserved_at_50[0x10]; 7865 7866 u8 oper_mtu[0x10]; 7867 u8 reserved_at_70[0x10]; 7868 }; 7869 7870 struct mlx5_ifc_pmpr_reg_bits { 7871 u8 reserved_at_0[0x8]; 7872 u8 module[0x8]; 7873 u8 reserved_at_10[0x10]; 7874 7875 u8 reserved_at_20[0x18]; 7876 u8 attenuation_5g[0x8]; 7877 7878 u8 reserved_at_40[0x18]; 7879 u8 attenuation_7g[0x8]; 7880 7881 u8 reserved_at_60[0x18]; 7882 u8 attenuation_12g[0x8]; 7883 }; 7884 7885 struct mlx5_ifc_pmpe_reg_bits { 7886 u8 reserved_at_0[0x8]; 7887 u8 module[0x8]; 7888 u8 reserved_at_10[0xc]; 7889 u8 module_status[0x4]; 7890 7891 u8 reserved_at_20[0x60]; 7892 }; 7893 7894 struct mlx5_ifc_pmpc_reg_bits { 7895 u8 module_state_updated[32][0x8]; 7896 }; 7897 7898 struct mlx5_ifc_pmlpn_reg_bits { 7899 u8 reserved_at_0[0x4]; 7900 u8 mlpn_status[0x4]; 7901 u8 local_port[0x8]; 7902 u8 reserved_at_10[0x10]; 7903 7904 u8 e[0x1]; 7905 u8 reserved_at_21[0x1f]; 7906 }; 7907 7908 struct mlx5_ifc_pmlp_reg_bits { 7909 u8 rxtx[0x1]; 7910 u8 reserved_at_1[0x7]; 7911 u8 local_port[0x8]; 7912 u8 reserved_at_10[0x8]; 7913 u8 width[0x8]; 7914 7915 u8 lane0_module_mapping[0x20]; 7916 7917 u8 lane1_module_mapping[0x20]; 7918 7919 u8 lane2_module_mapping[0x20]; 7920 7921 u8 lane3_module_mapping[0x20]; 7922 7923 u8 reserved_at_a0[0x160]; 7924 }; 7925 7926 struct mlx5_ifc_pmaos_reg_bits { 7927 u8 reserved_at_0[0x8]; 7928 u8 module[0x8]; 7929 u8 reserved_at_10[0x4]; 7930 u8 admin_status[0x4]; 7931 u8 reserved_at_18[0x4]; 7932 u8 oper_status[0x4]; 7933 7934 u8 ase[0x1]; 7935 u8 ee[0x1]; 7936 u8 reserved_at_22[0x1c]; 7937 u8 e[0x2]; 7938 7939 u8 reserved_at_40[0x40]; 7940 }; 7941 7942 struct mlx5_ifc_plpc_reg_bits { 7943 u8 reserved_at_0[0x4]; 7944 u8 profile_id[0xc]; 7945 u8 reserved_at_10[0x4]; 7946 u8 proto_mask[0x4]; 7947 u8 reserved_at_18[0x8]; 7948 7949 u8 reserved_at_20[0x10]; 7950 u8 lane_speed[0x10]; 7951 7952 u8 reserved_at_40[0x17]; 7953 u8 lpbf[0x1]; 7954 u8 fec_mode_policy[0x8]; 7955 7956 u8 retransmission_capability[0x8]; 7957 u8 fec_mode_capability[0x18]; 7958 7959 u8 retransmission_support_admin[0x8]; 7960 u8 fec_mode_support_admin[0x18]; 7961 7962 u8 retransmission_request_admin[0x8]; 7963 u8 fec_mode_request_admin[0x18]; 7964 7965 u8 reserved_at_c0[0x80]; 7966 }; 7967 7968 struct mlx5_ifc_plib_reg_bits { 7969 u8 reserved_at_0[0x8]; 7970 u8 local_port[0x8]; 7971 u8 reserved_at_10[0x8]; 7972 u8 ib_port[0x8]; 7973 7974 u8 reserved_at_20[0x60]; 7975 }; 7976 7977 struct mlx5_ifc_plbf_reg_bits { 7978 u8 reserved_at_0[0x8]; 7979 u8 local_port[0x8]; 7980 u8 reserved_at_10[0xd]; 7981 u8 lbf_mode[0x3]; 7982 7983 u8 reserved_at_20[0x20]; 7984 }; 7985 7986 struct mlx5_ifc_pipg_reg_bits { 7987 u8 reserved_at_0[0x8]; 7988 u8 local_port[0x8]; 7989 u8 reserved_at_10[0x10]; 7990 7991 u8 dic[0x1]; 7992 u8 reserved_at_21[0x19]; 7993 u8 ipg[0x4]; 7994 u8 reserved_at_3e[0x2]; 7995 }; 7996 7997 struct mlx5_ifc_pifr_reg_bits { 7998 u8 reserved_at_0[0x8]; 7999 u8 local_port[0x8]; 8000 u8 reserved_at_10[0x10]; 8001 8002 u8 reserved_at_20[0xe0]; 8003 8004 u8 port_filter[8][0x20]; 8005 8006 u8 port_filter_update_en[8][0x20]; 8007 }; 8008 8009 struct mlx5_ifc_pfcc_reg_bits { 8010 u8 reserved_at_0[0x8]; 8011 u8 local_port[0x8]; 8012 u8 reserved_at_10[0xb]; 8013 u8 ppan_mask_n[0x1]; 8014 u8 minor_stall_mask[0x1]; 8015 u8 critical_stall_mask[0x1]; 8016 u8 reserved_at_1e[0x2]; 8017 8018 u8 ppan[0x4]; 8019 u8 reserved_at_24[0x4]; 8020 u8 prio_mask_tx[0x8]; 8021 u8 reserved_at_30[0x8]; 8022 u8 prio_mask_rx[0x8]; 8023 8024 u8 pptx[0x1]; 8025 u8 aptx[0x1]; 8026 u8 pptx_mask_n[0x1]; 8027 u8 reserved_at_43[0x5]; 8028 u8 pfctx[0x8]; 8029 u8 reserved_at_50[0x10]; 8030 8031 u8 pprx[0x1]; 8032 u8 aprx[0x1]; 8033 u8 pprx_mask_n[0x1]; 8034 u8 reserved_at_63[0x5]; 8035 u8 pfcrx[0x8]; 8036 u8 reserved_at_70[0x10]; 8037 8038 u8 device_stall_minor_watermark[0x10]; 8039 u8 device_stall_critical_watermark[0x10]; 8040 8041 u8 reserved_at_a0[0x60]; 8042 }; 8043 8044 struct mlx5_ifc_pelc_reg_bits { 8045 u8 op[0x4]; 8046 u8 reserved_at_4[0x4]; 8047 u8 local_port[0x8]; 8048 u8 reserved_at_10[0x10]; 8049 8050 u8 op_admin[0x8]; 8051 u8 op_capability[0x8]; 8052 u8 op_request[0x8]; 8053 u8 op_active[0x8]; 8054 8055 u8 admin[0x40]; 8056 8057 u8 capability[0x40]; 8058 8059 u8 request[0x40]; 8060 8061 u8 active[0x40]; 8062 8063 u8 reserved_at_140[0x80]; 8064 }; 8065 8066 struct mlx5_ifc_peir_reg_bits { 8067 u8 reserved_at_0[0x8]; 8068 u8 local_port[0x8]; 8069 u8 reserved_at_10[0x10]; 8070 8071 u8 reserved_at_20[0xc]; 8072 u8 error_count[0x4]; 8073 u8 reserved_at_30[0x10]; 8074 8075 u8 reserved_at_40[0xc]; 8076 u8 lane[0x4]; 8077 u8 reserved_at_50[0x8]; 8078 u8 error_type[0x8]; 8079 }; 8080 8081 struct mlx5_ifc_mpegc_reg_bits { 8082 u8 reserved_at_0[0x30]; 8083 u8 field_select[0x10]; 8084 8085 u8 tx_overflow_sense[0x1]; 8086 u8 mark_cqe[0x1]; 8087 u8 mark_cnp[0x1]; 8088 u8 reserved_at_43[0x1b]; 8089 u8 tx_lossy_overflow_oper[0x2]; 8090 8091 u8 reserved_at_60[0x100]; 8092 }; 8093 8094 struct mlx5_ifc_pcam_enhanced_features_bits { 8095 u8 reserved_at_0[0x6d]; 8096 u8 rx_icrc_encapsulated_counter[0x1]; 8097 u8 reserved_at_6e[0x8]; 8098 u8 pfcc_mask[0x1]; 8099 u8 reserved_at_77[0x4]; 8100 u8 rx_buffer_fullness_counters[0x1]; 8101 u8 ptys_connector_type[0x1]; 8102 u8 reserved_at_7d[0x1]; 8103 u8 ppcnt_discard_group[0x1]; 8104 u8 ppcnt_statistical_group[0x1]; 8105 }; 8106 8107 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8108 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8109 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8110 u8 port_access_reg_cap_mask_63_to_32[0x20]; 8111 8112 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8113 u8 pbmc[0x1]; 8114 u8 pptb[0x1]; 8115 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8116 }; 8117 8118 struct mlx5_ifc_pcam_reg_bits { 8119 u8 reserved_at_0[0x8]; 8120 u8 feature_group[0x8]; 8121 u8 reserved_at_10[0x8]; 8122 u8 access_reg_group[0x8]; 8123 8124 u8 reserved_at_20[0x20]; 8125 8126 union { 8127 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8128 u8 reserved_at_0[0x80]; 8129 } port_access_reg_cap_mask; 8130 8131 u8 reserved_at_c0[0x80]; 8132 8133 union { 8134 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8135 u8 reserved_at_0[0x80]; 8136 } feature_cap_mask; 8137 8138 u8 reserved_at_1c0[0xc0]; 8139 }; 8140 8141 struct mlx5_ifc_mcam_enhanced_features_bits { 8142 u8 reserved_at_0[0x74]; 8143 u8 mark_tx_action_cnp[0x1]; 8144 u8 mark_tx_action_cqe[0x1]; 8145 u8 dynamic_tx_overflow[0x1]; 8146 u8 reserved_at_77[0x4]; 8147 u8 pcie_outbound_stalled[0x1]; 8148 u8 tx_overflow_buffer_pkt[0x1]; 8149 u8 mtpps_enh_out_per_adj[0x1]; 8150 u8 mtpps_fs[0x1]; 8151 u8 pcie_performance_group[0x1]; 8152 }; 8153 8154 struct mlx5_ifc_mcam_access_reg_bits { 8155 u8 reserved_at_0[0x1c]; 8156 u8 mcda[0x1]; 8157 u8 mcc[0x1]; 8158 u8 mcqi[0x1]; 8159 u8 reserved_at_1f[0x1]; 8160 8161 u8 regs_95_to_87[0x9]; 8162 u8 mpegc[0x1]; 8163 u8 regs_85_to_68[0x12]; 8164 u8 tracer_registers[0x4]; 8165 8166 u8 regs_63_to_32[0x20]; 8167 u8 regs_31_to_0[0x20]; 8168 }; 8169 8170 struct mlx5_ifc_mcam_reg_bits { 8171 u8 reserved_at_0[0x8]; 8172 u8 feature_group[0x8]; 8173 u8 reserved_at_10[0x8]; 8174 u8 access_reg_group[0x8]; 8175 8176 u8 reserved_at_20[0x20]; 8177 8178 union { 8179 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8180 u8 reserved_at_0[0x80]; 8181 } mng_access_reg_cap_mask; 8182 8183 u8 reserved_at_c0[0x80]; 8184 8185 union { 8186 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8187 u8 reserved_at_0[0x80]; 8188 } mng_feature_cap_mask; 8189 8190 u8 reserved_at_1c0[0x80]; 8191 }; 8192 8193 struct mlx5_ifc_qcam_access_reg_cap_mask { 8194 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8195 u8 qpdpm[0x1]; 8196 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8197 u8 qdpm[0x1]; 8198 u8 qpts[0x1]; 8199 u8 qcap[0x1]; 8200 u8 qcam_access_reg_cap_mask_0[0x1]; 8201 }; 8202 8203 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8204 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8205 u8 qpts_trust_both[0x1]; 8206 }; 8207 8208 struct mlx5_ifc_qcam_reg_bits { 8209 u8 reserved_at_0[0x8]; 8210 u8 feature_group[0x8]; 8211 u8 reserved_at_10[0x8]; 8212 u8 access_reg_group[0x8]; 8213 u8 reserved_at_20[0x20]; 8214 8215 union { 8216 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8217 u8 reserved_at_0[0x80]; 8218 } qos_access_reg_cap_mask; 8219 8220 u8 reserved_at_c0[0x80]; 8221 8222 union { 8223 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8224 u8 reserved_at_0[0x80]; 8225 } qos_feature_cap_mask; 8226 8227 u8 reserved_at_1c0[0x80]; 8228 }; 8229 8230 struct mlx5_ifc_pcap_reg_bits { 8231 u8 reserved_at_0[0x8]; 8232 u8 local_port[0x8]; 8233 u8 reserved_at_10[0x10]; 8234 8235 u8 port_capability_mask[4][0x20]; 8236 }; 8237 8238 struct mlx5_ifc_paos_reg_bits { 8239 u8 swid[0x8]; 8240 u8 local_port[0x8]; 8241 u8 reserved_at_10[0x4]; 8242 u8 admin_status[0x4]; 8243 u8 reserved_at_18[0x4]; 8244 u8 oper_status[0x4]; 8245 8246 u8 ase[0x1]; 8247 u8 ee[0x1]; 8248 u8 reserved_at_22[0x1c]; 8249 u8 e[0x2]; 8250 8251 u8 reserved_at_40[0x40]; 8252 }; 8253 8254 struct mlx5_ifc_pamp_reg_bits { 8255 u8 reserved_at_0[0x8]; 8256 u8 opamp_group[0x8]; 8257 u8 reserved_at_10[0xc]; 8258 u8 opamp_group_type[0x4]; 8259 8260 u8 start_index[0x10]; 8261 u8 reserved_at_30[0x4]; 8262 u8 num_of_indices[0xc]; 8263 8264 u8 index_data[18][0x10]; 8265 }; 8266 8267 struct mlx5_ifc_pcmr_reg_bits { 8268 u8 reserved_at_0[0x8]; 8269 u8 local_port[0x8]; 8270 u8 reserved_at_10[0x2e]; 8271 u8 fcs_cap[0x1]; 8272 u8 reserved_at_3f[0x1f]; 8273 u8 fcs_chk[0x1]; 8274 u8 reserved_at_5f[0x1]; 8275 }; 8276 8277 struct mlx5_ifc_lane_2_module_mapping_bits { 8278 u8 reserved_at_0[0x6]; 8279 u8 rx_lane[0x2]; 8280 u8 reserved_at_8[0x6]; 8281 u8 tx_lane[0x2]; 8282 u8 reserved_at_10[0x8]; 8283 u8 module[0x8]; 8284 }; 8285 8286 struct mlx5_ifc_bufferx_reg_bits { 8287 u8 reserved_at_0[0x6]; 8288 u8 lossy[0x1]; 8289 u8 epsb[0x1]; 8290 u8 reserved_at_8[0x8]; 8291 u8 size[0x10]; 8292 8293 u8 xoff_threshold[0x10]; 8294 u8 xon_threshold[0x10]; 8295 }; 8296 8297 struct mlx5_ifc_set_node_in_bits { 8298 u8 node_description[64][0x8]; 8299 }; 8300 8301 struct mlx5_ifc_register_power_settings_bits { 8302 u8 reserved_at_0[0x18]; 8303 u8 power_settings_level[0x8]; 8304 8305 u8 reserved_at_20[0x60]; 8306 }; 8307 8308 struct mlx5_ifc_register_host_endianness_bits { 8309 u8 he[0x1]; 8310 u8 reserved_at_1[0x1f]; 8311 8312 u8 reserved_at_20[0x60]; 8313 }; 8314 8315 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8316 u8 reserved_at_0[0x20]; 8317 8318 u8 mkey[0x20]; 8319 8320 u8 addressh_63_32[0x20]; 8321 8322 u8 addressl_31_0[0x20]; 8323 }; 8324 8325 struct mlx5_ifc_ud_adrs_vector_bits { 8326 u8 dc_key[0x40]; 8327 8328 u8 ext[0x1]; 8329 u8 reserved_at_41[0x7]; 8330 u8 destination_qp_dct[0x18]; 8331 8332 u8 static_rate[0x4]; 8333 u8 sl_eth_prio[0x4]; 8334 u8 fl[0x1]; 8335 u8 mlid[0x7]; 8336 u8 rlid_udp_sport[0x10]; 8337 8338 u8 reserved_at_80[0x20]; 8339 8340 u8 rmac_47_16[0x20]; 8341 8342 u8 rmac_15_0[0x10]; 8343 u8 tclass[0x8]; 8344 u8 hop_limit[0x8]; 8345 8346 u8 reserved_at_e0[0x1]; 8347 u8 grh[0x1]; 8348 u8 reserved_at_e2[0x2]; 8349 u8 src_addr_index[0x8]; 8350 u8 flow_label[0x14]; 8351 8352 u8 rgid_rip[16][0x8]; 8353 }; 8354 8355 struct mlx5_ifc_pages_req_event_bits { 8356 u8 reserved_at_0[0x10]; 8357 u8 function_id[0x10]; 8358 8359 u8 num_pages[0x20]; 8360 8361 u8 reserved_at_40[0xa0]; 8362 }; 8363 8364 struct mlx5_ifc_eqe_bits { 8365 u8 reserved_at_0[0x8]; 8366 u8 event_type[0x8]; 8367 u8 reserved_at_10[0x8]; 8368 u8 event_sub_type[0x8]; 8369 8370 u8 reserved_at_20[0xe0]; 8371 8372 union mlx5_ifc_event_auto_bits event_data; 8373 8374 u8 reserved_at_1e0[0x10]; 8375 u8 signature[0x8]; 8376 u8 reserved_at_1f8[0x7]; 8377 u8 owner[0x1]; 8378 }; 8379 8380 enum { 8381 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8382 }; 8383 8384 struct mlx5_ifc_cmd_queue_entry_bits { 8385 u8 type[0x8]; 8386 u8 reserved_at_8[0x18]; 8387 8388 u8 input_length[0x20]; 8389 8390 u8 input_mailbox_pointer_63_32[0x20]; 8391 8392 u8 input_mailbox_pointer_31_9[0x17]; 8393 u8 reserved_at_77[0x9]; 8394 8395 u8 command_input_inline_data[16][0x8]; 8396 8397 u8 command_output_inline_data[16][0x8]; 8398 8399 u8 output_mailbox_pointer_63_32[0x20]; 8400 8401 u8 output_mailbox_pointer_31_9[0x17]; 8402 u8 reserved_at_1b7[0x9]; 8403 8404 u8 output_length[0x20]; 8405 8406 u8 token[0x8]; 8407 u8 signature[0x8]; 8408 u8 reserved_at_1f0[0x8]; 8409 u8 status[0x7]; 8410 u8 ownership[0x1]; 8411 }; 8412 8413 struct mlx5_ifc_cmd_out_bits { 8414 u8 status[0x8]; 8415 u8 reserved_at_8[0x18]; 8416 8417 u8 syndrome[0x20]; 8418 8419 u8 command_output[0x20]; 8420 }; 8421 8422 struct mlx5_ifc_cmd_in_bits { 8423 u8 opcode[0x10]; 8424 u8 reserved_at_10[0x10]; 8425 8426 u8 reserved_at_20[0x10]; 8427 u8 op_mod[0x10]; 8428 8429 u8 command[0][0x20]; 8430 }; 8431 8432 struct mlx5_ifc_cmd_if_box_bits { 8433 u8 mailbox_data[512][0x8]; 8434 8435 u8 reserved_at_1000[0x180]; 8436 8437 u8 next_pointer_63_32[0x20]; 8438 8439 u8 next_pointer_31_10[0x16]; 8440 u8 reserved_at_11b6[0xa]; 8441 8442 u8 block_number[0x20]; 8443 8444 u8 reserved_at_11e0[0x8]; 8445 u8 token[0x8]; 8446 u8 ctrl_signature[0x8]; 8447 u8 signature[0x8]; 8448 }; 8449 8450 struct mlx5_ifc_mtt_bits { 8451 u8 ptag_63_32[0x20]; 8452 8453 u8 ptag_31_8[0x18]; 8454 u8 reserved_at_38[0x6]; 8455 u8 wr_en[0x1]; 8456 u8 rd_en[0x1]; 8457 }; 8458 8459 struct mlx5_ifc_query_wol_rol_out_bits { 8460 u8 status[0x8]; 8461 u8 reserved_at_8[0x18]; 8462 8463 u8 syndrome[0x20]; 8464 8465 u8 reserved_at_40[0x10]; 8466 u8 rol_mode[0x8]; 8467 u8 wol_mode[0x8]; 8468 8469 u8 reserved_at_60[0x20]; 8470 }; 8471 8472 struct mlx5_ifc_query_wol_rol_in_bits { 8473 u8 opcode[0x10]; 8474 u8 reserved_at_10[0x10]; 8475 8476 u8 reserved_at_20[0x10]; 8477 u8 op_mod[0x10]; 8478 8479 u8 reserved_at_40[0x40]; 8480 }; 8481 8482 struct mlx5_ifc_set_wol_rol_out_bits { 8483 u8 status[0x8]; 8484 u8 reserved_at_8[0x18]; 8485 8486 u8 syndrome[0x20]; 8487 8488 u8 reserved_at_40[0x40]; 8489 }; 8490 8491 struct mlx5_ifc_set_wol_rol_in_bits { 8492 u8 opcode[0x10]; 8493 u8 reserved_at_10[0x10]; 8494 8495 u8 reserved_at_20[0x10]; 8496 u8 op_mod[0x10]; 8497 8498 u8 rol_mode_valid[0x1]; 8499 u8 wol_mode_valid[0x1]; 8500 u8 reserved_at_42[0xe]; 8501 u8 rol_mode[0x8]; 8502 u8 wol_mode[0x8]; 8503 8504 u8 reserved_at_60[0x20]; 8505 }; 8506 8507 enum { 8508 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8509 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8510 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8511 }; 8512 8513 enum { 8514 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8515 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8516 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8517 }; 8518 8519 enum { 8520 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8521 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8522 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8523 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8524 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8525 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8526 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8527 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8528 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8529 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8530 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8531 }; 8532 8533 struct mlx5_ifc_initial_seg_bits { 8534 u8 fw_rev_minor[0x10]; 8535 u8 fw_rev_major[0x10]; 8536 8537 u8 cmd_interface_rev[0x10]; 8538 u8 fw_rev_subminor[0x10]; 8539 8540 u8 reserved_at_40[0x40]; 8541 8542 u8 cmdq_phy_addr_63_32[0x20]; 8543 8544 u8 cmdq_phy_addr_31_12[0x14]; 8545 u8 reserved_at_b4[0x2]; 8546 u8 nic_interface[0x2]; 8547 u8 log_cmdq_size[0x4]; 8548 u8 log_cmdq_stride[0x4]; 8549 8550 u8 command_doorbell_vector[0x20]; 8551 8552 u8 reserved_at_e0[0xf00]; 8553 8554 u8 initializing[0x1]; 8555 u8 reserved_at_fe1[0x4]; 8556 u8 nic_interface_supported[0x3]; 8557 u8 reserved_at_fe8[0x18]; 8558 8559 struct mlx5_ifc_health_buffer_bits health_buffer; 8560 8561 u8 no_dram_nic_offset[0x20]; 8562 8563 u8 reserved_at_1220[0x6e40]; 8564 8565 u8 reserved_at_8060[0x1f]; 8566 u8 clear_int[0x1]; 8567 8568 u8 health_syndrome[0x8]; 8569 u8 health_counter[0x18]; 8570 8571 u8 reserved_at_80a0[0x17fc0]; 8572 }; 8573 8574 struct mlx5_ifc_mtpps_reg_bits { 8575 u8 reserved_at_0[0xc]; 8576 u8 cap_number_of_pps_pins[0x4]; 8577 u8 reserved_at_10[0x4]; 8578 u8 cap_max_num_of_pps_in_pins[0x4]; 8579 u8 reserved_at_18[0x4]; 8580 u8 cap_max_num_of_pps_out_pins[0x4]; 8581 8582 u8 reserved_at_20[0x24]; 8583 u8 cap_pin_3_mode[0x4]; 8584 u8 reserved_at_48[0x4]; 8585 u8 cap_pin_2_mode[0x4]; 8586 u8 reserved_at_50[0x4]; 8587 u8 cap_pin_1_mode[0x4]; 8588 u8 reserved_at_58[0x4]; 8589 u8 cap_pin_0_mode[0x4]; 8590 8591 u8 reserved_at_60[0x4]; 8592 u8 cap_pin_7_mode[0x4]; 8593 u8 reserved_at_68[0x4]; 8594 u8 cap_pin_6_mode[0x4]; 8595 u8 reserved_at_70[0x4]; 8596 u8 cap_pin_5_mode[0x4]; 8597 u8 reserved_at_78[0x4]; 8598 u8 cap_pin_4_mode[0x4]; 8599 8600 u8 field_select[0x20]; 8601 u8 reserved_at_a0[0x60]; 8602 8603 u8 enable[0x1]; 8604 u8 reserved_at_101[0xb]; 8605 u8 pattern[0x4]; 8606 u8 reserved_at_110[0x4]; 8607 u8 pin_mode[0x4]; 8608 u8 pin[0x8]; 8609 8610 u8 reserved_at_120[0x20]; 8611 8612 u8 time_stamp[0x40]; 8613 8614 u8 out_pulse_duration[0x10]; 8615 u8 out_periodic_adjustment[0x10]; 8616 u8 enhanced_out_periodic_adjustment[0x20]; 8617 8618 u8 reserved_at_1c0[0x20]; 8619 }; 8620 8621 struct mlx5_ifc_mtppse_reg_bits { 8622 u8 reserved_at_0[0x18]; 8623 u8 pin[0x8]; 8624 u8 event_arm[0x1]; 8625 u8 reserved_at_21[0x1b]; 8626 u8 event_generation_mode[0x4]; 8627 u8 reserved_at_40[0x40]; 8628 }; 8629 8630 struct mlx5_ifc_mcqi_cap_bits { 8631 u8 supported_info_bitmask[0x20]; 8632 8633 u8 component_size[0x20]; 8634 8635 u8 max_component_size[0x20]; 8636 8637 u8 log_mcda_word_size[0x4]; 8638 u8 reserved_at_64[0xc]; 8639 u8 mcda_max_write_size[0x10]; 8640 8641 u8 rd_en[0x1]; 8642 u8 reserved_at_81[0x1]; 8643 u8 match_chip_id[0x1]; 8644 u8 match_psid[0x1]; 8645 u8 check_user_timestamp[0x1]; 8646 u8 match_base_guid_mac[0x1]; 8647 u8 reserved_at_86[0x1a]; 8648 }; 8649 8650 struct mlx5_ifc_mcqi_reg_bits { 8651 u8 read_pending_component[0x1]; 8652 u8 reserved_at_1[0xf]; 8653 u8 component_index[0x10]; 8654 8655 u8 reserved_at_20[0x20]; 8656 8657 u8 reserved_at_40[0x1b]; 8658 u8 info_type[0x5]; 8659 8660 u8 info_size[0x20]; 8661 8662 u8 offset[0x20]; 8663 8664 u8 reserved_at_a0[0x10]; 8665 u8 data_size[0x10]; 8666 8667 u8 data[0][0x20]; 8668 }; 8669 8670 struct mlx5_ifc_mcc_reg_bits { 8671 u8 reserved_at_0[0x4]; 8672 u8 time_elapsed_since_last_cmd[0xc]; 8673 u8 reserved_at_10[0x8]; 8674 u8 instruction[0x8]; 8675 8676 u8 reserved_at_20[0x10]; 8677 u8 component_index[0x10]; 8678 8679 u8 reserved_at_40[0x8]; 8680 u8 update_handle[0x18]; 8681 8682 u8 handle_owner_type[0x4]; 8683 u8 handle_owner_host_id[0x4]; 8684 u8 reserved_at_68[0x1]; 8685 u8 control_progress[0x7]; 8686 u8 error_code[0x8]; 8687 u8 reserved_at_78[0x4]; 8688 u8 control_state[0x4]; 8689 8690 u8 component_size[0x20]; 8691 8692 u8 reserved_at_a0[0x60]; 8693 }; 8694 8695 struct mlx5_ifc_mcda_reg_bits { 8696 u8 reserved_at_0[0x8]; 8697 u8 update_handle[0x18]; 8698 8699 u8 offset[0x20]; 8700 8701 u8 reserved_at_40[0x10]; 8702 u8 size[0x10]; 8703 8704 u8 reserved_at_60[0x20]; 8705 8706 u8 data[0][0x20]; 8707 }; 8708 8709 union mlx5_ifc_ports_control_registers_document_bits { 8710 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8711 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8712 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8713 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8714 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8715 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8716 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8717 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8718 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8719 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8720 struct mlx5_ifc_paos_reg_bits paos_reg; 8721 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8722 struct mlx5_ifc_peir_reg_bits peir_reg; 8723 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8724 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8725 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8726 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8727 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8728 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8729 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8730 struct mlx5_ifc_plib_reg_bits plib_reg; 8731 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8732 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8733 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8734 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8735 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8736 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8737 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8738 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8739 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8740 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8741 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8742 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8743 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8744 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8745 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8746 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8747 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8748 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8749 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8750 struct mlx5_ifc_pude_reg_bits pude_reg; 8751 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8752 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8753 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8754 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8755 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8756 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8757 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8758 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8759 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8760 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8761 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8762 u8 reserved_at_0[0x60e0]; 8763 }; 8764 8765 union mlx5_ifc_debug_enhancements_document_bits { 8766 struct mlx5_ifc_health_buffer_bits health_buffer; 8767 u8 reserved_at_0[0x200]; 8768 }; 8769 8770 union mlx5_ifc_uplink_pci_interface_document_bits { 8771 struct mlx5_ifc_initial_seg_bits initial_seg; 8772 u8 reserved_at_0[0x20060]; 8773 }; 8774 8775 struct mlx5_ifc_set_flow_table_root_out_bits { 8776 u8 status[0x8]; 8777 u8 reserved_at_8[0x18]; 8778 8779 u8 syndrome[0x20]; 8780 8781 u8 reserved_at_40[0x40]; 8782 }; 8783 8784 struct mlx5_ifc_set_flow_table_root_in_bits { 8785 u8 opcode[0x10]; 8786 u8 reserved_at_10[0x10]; 8787 8788 u8 reserved_at_20[0x10]; 8789 u8 op_mod[0x10]; 8790 8791 u8 other_vport[0x1]; 8792 u8 reserved_at_41[0xf]; 8793 u8 vport_number[0x10]; 8794 8795 u8 reserved_at_60[0x20]; 8796 8797 u8 table_type[0x8]; 8798 u8 reserved_at_88[0x18]; 8799 8800 u8 reserved_at_a0[0x8]; 8801 u8 table_id[0x18]; 8802 8803 u8 reserved_at_c0[0x8]; 8804 u8 underlay_qpn[0x18]; 8805 u8 reserved_at_e0[0x120]; 8806 }; 8807 8808 enum { 8809 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8810 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8811 }; 8812 8813 struct mlx5_ifc_modify_flow_table_out_bits { 8814 u8 status[0x8]; 8815 u8 reserved_at_8[0x18]; 8816 8817 u8 syndrome[0x20]; 8818 8819 u8 reserved_at_40[0x40]; 8820 }; 8821 8822 struct mlx5_ifc_modify_flow_table_in_bits { 8823 u8 opcode[0x10]; 8824 u8 reserved_at_10[0x10]; 8825 8826 u8 reserved_at_20[0x10]; 8827 u8 op_mod[0x10]; 8828 8829 u8 other_vport[0x1]; 8830 u8 reserved_at_41[0xf]; 8831 u8 vport_number[0x10]; 8832 8833 u8 reserved_at_60[0x10]; 8834 u8 modify_field_select[0x10]; 8835 8836 u8 table_type[0x8]; 8837 u8 reserved_at_88[0x18]; 8838 8839 u8 reserved_at_a0[0x8]; 8840 u8 table_id[0x18]; 8841 8842 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8843 }; 8844 8845 struct mlx5_ifc_ets_tcn_config_reg_bits { 8846 u8 g[0x1]; 8847 u8 b[0x1]; 8848 u8 r[0x1]; 8849 u8 reserved_at_3[0x9]; 8850 u8 group[0x4]; 8851 u8 reserved_at_10[0x9]; 8852 u8 bw_allocation[0x7]; 8853 8854 u8 reserved_at_20[0xc]; 8855 u8 max_bw_units[0x4]; 8856 u8 reserved_at_30[0x8]; 8857 u8 max_bw_value[0x8]; 8858 }; 8859 8860 struct mlx5_ifc_ets_global_config_reg_bits { 8861 u8 reserved_at_0[0x2]; 8862 u8 r[0x1]; 8863 u8 reserved_at_3[0x1d]; 8864 8865 u8 reserved_at_20[0xc]; 8866 u8 max_bw_units[0x4]; 8867 u8 reserved_at_30[0x8]; 8868 u8 max_bw_value[0x8]; 8869 }; 8870 8871 struct mlx5_ifc_qetc_reg_bits { 8872 u8 reserved_at_0[0x8]; 8873 u8 port_number[0x8]; 8874 u8 reserved_at_10[0x30]; 8875 8876 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8877 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8878 }; 8879 8880 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8881 u8 e[0x1]; 8882 u8 reserved_at_01[0x0b]; 8883 u8 prio[0x04]; 8884 }; 8885 8886 struct mlx5_ifc_qpdpm_reg_bits { 8887 u8 reserved_at_0[0x8]; 8888 u8 local_port[0x8]; 8889 u8 reserved_at_10[0x10]; 8890 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8891 }; 8892 8893 struct mlx5_ifc_qpts_reg_bits { 8894 u8 reserved_at_0[0x8]; 8895 u8 local_port[0x8]; 8896 u8 reserved_at_10[0x2d]; 8897 u8 trust_state[0x3]; 8898 }; 8899 8900 struct mlx5_ifc_pptb_reg_bits { 8901 u8 reserved_at_0[0x2]; 8902 u8 mm[0x2]; 8903 u8 reserved_at_4[0x4]; 8904 u8 local_port[0x8]; 8905 u8 reserved_at_10[0x6]; 8906 u8 cm[0x1]; 8907 u8 um[0x1]; 8908 u8 pm[0x8]; 8909 8910 u8 prio_x_buff[0x20]; 8911 8912 u8 pm_msb[0x8]; 8913 u8 reserved_at_48[0x10]; 8914 u8 ctrl_buff[0x4]; 8915 u8 untagged_buff[0x4]; 8916 }; 8917 8918 struct mlx5_ifc_pbmc_reg_bits { 8919 u8 reserved_at_0[0x8]; 8920 u8 local_port[0x8]; 8921 u8 reserved_at_10[0x10]; 8922 8923 u8 xoff_timer_value[0x10]; 8924 u8 xoff_refresh[0x10]; 8925 8926 u8 reserved_at_40[0x9]; 8927 u8 fullness_threshold[0x7]; 8928 u8 port_buffer_size[0x10]; 8929 8930 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8931 8932 u8 reserved_at_2e0[0x80]; 8933 }; 8934 8935 struct mlx5_ifc_qtct_reg_bits { 8936 u8 reserved_at_0[0x8]; 8937 u8 port_number[0x8]; 8938 u8 reserved_at_10[0xd]; 8939 u8 prio[0x3]; 8940 8941 u8 reserved_at_20[0x1d]; 8942 u8 tclass[0x3]; 8943 }; 8944 8945 struct mlx5_ifc_mcia_reg_bits { 8946 u8 l[0x1]; 8947 u8 reserved_at_1[0x7]; 8948 u8 module[0x8]; 8949 u8 reserved_at_10[0x8]; 8950 u8 status[0x8]; 8951 8952 u8 i2c_device_address[0x8]; 8953 u8 page_number[0x8]; 8954 u8 device_address[0x10]; 8955 8956 u8 reserved_at_40[0x10]; 8957 u8 size[0x10]; 8958 8959 u8 reserved_at_60[0x20]; 8960 8961 u8 dword_0[0x20]; 8962 u8 dword_1[0x20]; 8963 u8 dword_2[0x20]; 8964 u8 dword_3[0x20]; 8965 u8 dword_4[0x20]; 8966 u8 dword_5[0x20]; 8967 u8 dword_6[0x20]; 8968 u8 dword_7[0x20]; 8969 u8 dword_8[0x20]; 8970 u8 dword_9[0x20]; 8971 u8 dword_10[0x20]; 8972 u8 dword_11[0x20]; 8973 }; 8974 8975 struct mlx5_ifc_dcbx_param_bits { 8976 u8 dcbx_cee_cap[0x1]; 8977 u8 dcbx_ieee_cap[0x1]; 8978 u8 dcbx_standby_cap[0x1]; 8979 u8 reserved_at_0[0x5]; 8980 u8 port_number[0x8]; 8981 u8 reserved_at_10[0xa]; 8982 u8 max_application_table_size[6]; 8983 u8 reserved_at_20[0x15]; 8984 u8 version_oper[0x3]; 8985 u8 reserved_at_38[5]; 8986 u8 version_admin[0x3]; 8987 u8 willing_admin[0x1]; 8988 u8 reserved_at_41[0x3]; 8989 u8 pfc_cap_oper[0x4]; 8990 u8 reserved_at_48[0x4]; 8991 u8 pfc_cap_admin[0x4]; 8992 u8 reserved_at_50[0x4]; 8993 u8 num_of_tc_oper[0x4]; 8994 u8 reserved_at_58[0x4]; 8995 u8 num_of_tc_admin[0x4]; 8996 u8 remote_willing[0x1]; 8997 u8 reserved_at_61[3]; 8998 u8 remote_pfc_cap[4]; 8999 u8 reserved_at_68[0x14]; 9000 u8 remote_num_of_tc[0x4]; 9001 u8 reserved_at_80[0x18]; 9002 u8 error[0x8]; 9003 u8 reserved_at_a0[0x160]; 9004 }; 9005 9006 struct mlx5_ifc_lagc_bits { 9007 u8 reserved_at_0[0x1d]; 9008 u8 lag_state[0x3]; 9009 9010 u8 reserved_at_20[0x14]; 9011 u8 tx_remap_affinity_2[0x4]; 9012 u8 reserved_at_38[0x4]; 9013 u8 tx_remap_affinity_1[0x4]; 9014 }; 9015 9016 struct mlx5_ifc_create_lag_out_bits { 9017 u8 status[0x8]; 9018 u8 reserved_at_8[0x18]; 9019 9020 u8 syndrome[0x20]; 9021 9022 u8 reserved_at_40[0x40]; 9023 }; 9024 9025 struct mlx5_ifc_create_lag_in_bits { 9026 u8 opcode[0x10]; 9027 u8 reserved_at_10[0x10]; 9028 9029 u8 reserved_at_20[0x10]; 9030 u8 op_mod[0x10]; 9031 9032 struct mlx5_ifc_lagc_bits ctx; 9033 }; 9034 9035 struct mlx5_ifc_modify_lag_out_bits { 9036 u8 status[0x8]; 9037 u8 reserved_at_8[0x18]; 9038 9039 u8 syndrome[0x20]; 9040 9041 u8 reserved_at_40[0x40]; 9042 }; 9043 9044 struct mlx5_ifc_modify_lag_in_bits { 9045 u8 opcode[0x10]; 9046 u8 reserved_at_10[0x10]; 9047 9048 u8 reserved_at_20[0x10]; 9049 u8 op_mod[0x10]; 9050 9051 u8 reserved_at_40[0x20]; 9052 u8 field_select[0x20]; 9053 9054 struct mlx5_ifc_lagc_bits ctx; 9055 }; 9056 9057 struct mlx5_ifc_query_lag_out_bits { 9058 u8 status[0x8]; 9059 u8 reserved_at_8[0x18]; 9060 9061 u8 syndrome[0x20]; 9062 9063 struct mlx5_ifc_lagc_bits ctx; 9064 }; 9065 9066 struct mlx5_ifc_query_lag_in_bits { 9067 u8 opcode[0x10]; 9068 u8 reserved_at_10[0x10]; 9069 9070 u8 reserved_at_20[0x10]; 9071 u8 op_mod[0x10]; 9072 9073 u8 reserved_at_40[0x40]; 9074 }; 9075 9076 struct mlx5_ifc_destroy_lag_out_bits { 9077 u8 status[0x8]; 9078 u8 reserved_at_8[0x18]; 9079 9080 u8 syndrome[0x20]; 9081 9082 u8 reserved_at_40[0x40]; 9083 }; 9084 9085 struct mlx5_ifc_destroy_lag_in_bits { 9086 u8 opcode[0x10]; 9087 u8 reserved_at_10[0x10]; 9088 9089 u8 reserved_at_20[0x10]; 9090 u8 op_mod[0x10]; 9091 9092 u8 reserved_at_40[0x40]; 9093 }; 9094 9095 struct mlx5_ifc_create_vport_lag_out_bits { 9096 u8 status[0x8]; 9097 u8 reserved_at_8[0x18]; 9098 9099 u8 syndrome[0x20]; 9100 9101 u8 reserved_at_40[0x40]; 9102 }; 9103 9104 struct mlx5_ifc_create_vport_lag_in_bits { 9105 u8 opcode[0x10]; 9106 u8 reserved_at_10[0x10]; 9107 9108 u8 reserved_at_20[0x10]; 9109 u8 op_mod[0x10]; 9110 9111 u8 reserved_at_40[0x40]; 9112 }; 9113 9114 struct mlx5_ifc_destroy_vport_lag_out_bits { 9115 u8 status[0x8]; 9116 u8 reserved_at_8[0x18]; 9117 9118 u8 syndrome[0x20]; 9119 9120 u8 reserved_at_40[0x40]; 9121 }; 9122 9123 struct mlx5_ifc_destroy_vport_lag_in_bits { 9124 u8 opcode[0x10]; 9125 u8 reserved_at_10[0x10]; 9126 9127 u8 reserved_at_20[0x10]; 9128 u8 op_mod[0x10]; 9129 9130 u8 reserved_at_40[0x40]; 9131 }; 9132 9133 struct mlx5_ifc_alloc_memic_in_bits { 9134 u8 opcode[0x10]; 9135 u8 reserved_at_10[0x10]; 9136 9137 u8 reserved_at_20[0x10]; 9138 u8 op_mod[0x10]; 9139 9140 u8 reserved_at_30[0x20]; 9141 9142 u8 reserved_at_40[0x18]; 9143 u8 log_memic_addr_alignment[0x8]; 9144 9145 u8 range_start_addr[0x40]; 9146 9147 u8 range_size[0x20]; 9148 9149 u8 memic_size[0x20]; 9150 }; 9151 9152 struct mlx5_ifc_alloc_memic_out_bits { 9153 u8 status[0x8]; 9154 u8 reserved_at_8[0x18]; 9155 9156 u8 syndrome[0x20]; 9157 9158 u8 memic_start_addr[0x40]; 9159 }; 9160 9161 struct mlx5_ifc_dealloc_memic_in_bits { 9162 u8 opcode[0x10]; 9163 u8 reserved_at_10[0x10]; 9164 9165 u8 reserved_at_20[0x10]; 9166 u8 op_mod[0x10]; 9167 9168 u8 reserved_at_40[0x40]; 9169 9170 u8 memic_start_addr[0x40]; 9171 9172 u8 memic_size[0x20]; 9173 9174 u8 reserved_at_e0[0x20]; 9175 }; 9176 9177 struct mlx5_ifc_dealloc_memic_out_bits { 9178 u8 status[0x8]; 9179 u8 reserved_at_8[0x18]; 9180 9181 u8 syndrome[0x20]; 9182 9183 u8 reserved_at_40[0x40]; 9184 }; 9185 9186 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9187 u8 opcode[0x10]; 9188 u8 uid[0x10]; 9189 9190 u8 reserved_at_20[0x10]; 9191 u8 obj_type[0x10]; 9192 9193 u8 obj_id[0x20]; 9194 9195 u8 reserved_at_60[0x20]; 9196 }; 9197 9198 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9199 u8 status[0x8]; 9200 u8 reserved_at_8[0x18]; 9201 9202 u8 syndrome[0x20]; 9203 9204 u8 obj_id[0x20]; 9205 9206 u8 reserved_at_60[0x20]; 9207 }; 9208 9209 struct mlx5_ifc_umem_bits { 9210 u8 modify_field_select[0x40]; 9211 9212 u8 reserved_at_40[0x5b]; 9213 u8 log_page_size[0x5]; 9214 9215 u8 page_offset[0x20]; 9216 9217 u8 num_of_mtt[0x40]; 9218 9219 struct mlx5_ifc_mtt_bits mtt[0]; 9220 }; 9221 9222 struct mlx5_ifc_uctx_bits { 9223 u8 modify_field_select[0x40]; 9224 9225 u8 reserved_at_40[0x1c0]; 9226 }; 9227 9228 struct mlx5_ifc_create_umem_in_bits { 9229 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9230 struct mlx5_ifc_umem_bits umem; 9231 }; 9232 9233 struct mlx5_ifc_create_uctx_in_bits { 9234 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9235 struct mlx5_ifc_uctx_bits uctx; 9236 }; 9237 9238 struct mlx5_ifc_mtrc_string_db_param_bits { 9239 u8 string_db_base_address[0x20]; 9240 9241 u8 reserved_at_20[0x8]; 9242 u8 string_db_size[0x18]; 9243 }; 9244 9245 struct mlx5_ifc_mtrc_cap_bits { 9246 u8 trace_owner[0x1]; 9247 u8 trace_to_memory[0x1]; 9248 u8 reserved_at_2[0x4]; 9249 u8 trc_ver[0x2]; 9250 u8 reserved_at_8[0x14]; 9251 u8 num_string_db[0x4]; 9252 9253 u8 first_string_trace[0x8]; 9254 u8 num_string_trace[0x8]; 9255 u8 reserved_at_30[0x28]; 9256 9257 u8 log_max_trace_buffer_size[0x8]; 9258 9259 u8 reserved_at_60[0x20]; 9260 9261 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9262 9263 u8 reserved_at_280[0x180]; 9264 }; 9265 9266 struct mlx5_ifc_mtrc_conf_bits { 9267 u8 reserved_at_0[0x1c]; 9268 u8 trace_mode[0x4]; 9269 u8 reserved_at_20[0x18]; 9270 u8 log_trace_buffer_size[0x8]; 9271 u8 trace_mkey[0x20]; 9272 u8 reserved_at_60[0x3a0]; 9273 }; 9274 9275 struct mlx5_ifc_mtrc_stdb_bits { 9276 u8 string_db_index[0x4]; 9277 u8 reserved_at_4[0x4]; 9278 u8 read_size[0x18]; 9279 u8 start_offset[0x20]; 9280 u8 string_db_data[0]; 9281 }; 9282 9283 struct mlx5_ifc_mtrc_ctrl_bits { 9284 u8 trace_status[0x2]; 9285 u8 reserved_at_2[0x2]; 9286 u8 arm_event[0x1]; 9287 u8 reserved_at_5[0xb]; 9288 u8 modify_field_select[0x10]; 9289 u8 reserved_at_20[0x2b]; 9290 u8 current_timestamp52_32[0x15]; 9291 u8 current_timestamp31_0[0x20]; 9292 u8 reserved_at_80[0x180]; 9293 }; 9294 9295 #endif /* MLX5_IFC_H */ 9296