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Searched refs:tegra_clk_register_divider (Results 1 – 9 of 9) sorted by relevance

/linux-4.19.296/drivers/clk/tegra/
Dclk-tegra-audio.c204 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra_audio_clk_init()
248 clk = tegra_clk_register_divider(data->div_name, in tegra_audio_clk_init()
Dclk-tegra30.c837 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra30_pll_init()
851 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra30_pll_init()
923 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", in tegra30_super_clk_init()
932 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", in tegra30_super_clk_init()
941 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", in tegra30_super_clk_init()
958 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", in tegra30_super_clk_init()
967 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", in tegra30_super_clk_init()
976 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", in tegra30_super_clk_init()
Dclk-divider.c129 struct clk *tegra_clk_register_divider(const char *name, in tegra_clk_register_divider() function
Dclk-tegra20.c646 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra20_pll_init()
660 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra20_pll_init()
694 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra20_pll_init()
820 clk = tegra_clk_register_divider("emc", "emc_mux", in tegra20_emc_clk_init()
Dclk-tegra-periph.c954 clk = tegra_clk_register_divider(data->name, in div_clk_init()
991 clk = tegra_clk_register_divider(data->div_name, "pll_p", in init_pllp()
1012 clk = tegra_clk_register_divider("pll_p_out4_div", in init_pllp()
Dclk-tegra114.c938 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra114_pll_init()
962 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra114_pll_init()
Dclk.h86 struct clk *tegra_clk_register_divider(const char *name,
Dclk-tegra210.c3073 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra210_pll_init()
3134 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out", in tegra210_pll_init()
3145 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out", in tegra210_pll_init()
3202 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco", in tegra210_pll_init()
3243 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0", in tegra210_pll_init()
Dclk-tegra124.c1063 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra124_pll_init()
1097 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra124_pll_init()