| /linux-4.19.296/include/media/ |
| D | v4l2-rect.h | 21 r->width = size->width; in v4l2_rect_set_size_to()
33 if (r->width < min_size->width) in v4l2_rect_set_min_size()
34 r->width = min_size->width; in v4l2_rect_set_min_size()
47 if (r->width > max_size->width) in v4l2_rect_set_max_size()
48 r->width = max_size->width; in v4l2_rect_set_max_size()
66 if (r->left + r->width > boundary->left + boundary->width) in v4l2_rect_map_inside()
67 r->left = boundary->left + boundary->width - r->width; in v4l2_rect_map_inside()
82 return r1->width == r2->width && r1->height == r2->height; in v4l2_rect_same_size()
100 right = min(r1->left + r1->width, r2->left + r2->width); in v4l2_rect_intersect()
102 r->width = max(0, right - r->left); in v4l2_rect_intersect()
[all …]
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| D | v4l2-mediabus.h | 108 pix_fmt->width = mbus_fmt->width; in v4l2_fill_pix_format()
130 mbus_fmt->width = pix_fmt->width; in v4l2_fill_mbus_format()
151 pix_mp_fmt->width = mbus_fmt->width; in v4l2_fill_pix_format_mplane()
171 mbus_fmt->width = pix_mp_fmt->width; in v4l2_fill_mbus_format_mplane()
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| /linux-4.19.296/drivers/clk/meson/ |
| D | clkc.h | 13 #define PMASK(width) GENMASK(width - 1, 0) argument
14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
17 #define PARM_GET(width, shift, reg) \ argument
18 (((reg) & SETPMASK(width, shift)) >> (shift))
19 #define PARM_SET(width, shift, reg, val) \ argument
20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
22 #define MESON_PARM_APPLICABLE(p) (!!((p)->width))
27 u8 width; member
35 return PARM_GET(p->width, p->shift, val); in meson_parm_read()
[all …]
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| D | axg.c | 30 .width = 9,
35 .width = 5,
40 .width = 2,
45 .width = 12,
50 .width = 1,
55 .width = 1,
71 .width = 9,
76 .width = 5,
81 .width = 2,
86 .width = 1,
[all …]
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| D | clk-phase.c | 18 int meson_clk_degrees_from_val(unsigned int val, unsigned int width) in meson_clk_degrees_from_val() argument
20 return phase_step(width) * val; in meson_clk_degrees_from_val()
24 unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width) in meson_clk_degrees_to_val() argument
26 unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width)); in meson_clk_degrees_to_val()
32 return val % (1 << width); in meson_clk_degrees_to_val()
44 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
53 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
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| D | gxbb.c | 183 .width = 9,
188 .width = 5,
193 .width = 2,
198 .width = 12,
203 .width = 1,
208 .width = 1,
235 .width = 9,
240 .width = 5,
245 .width = 12,
250 .width = 2,
[all …]
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| D | meson8b.c | 102 .width = 9,
107 .width = 5,
112 .width = 2,
117 .width = 12,
122 .width = 1,
127 .width = 1,
143 .width = 9,
148 .width = 5,
153 .width = 2,
158 .width = 1,
[all …]
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| /linux-4.19.296/drivers/clk/ |
| D | clk-divider.c | 32 u8 width) in _get_table_maxdiv() argument
34 unsigned int maxdiv = 0, mask = clk_div_mask(width); in _get_table_maxdiv()
54 static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width, in _get_maxdiv() argument
58 return clk_div_mask(width); in _get_maxdiv()
60 return 1 << clk_div_mask(width); in _get_maxdiv()
62 return _get_table_maxdiv(table, width); in _get_maxdiv()
63 return clk_div_mask(width) + 1; in _get_maxdiv()
78 unsigned int val, unsigned long flags, u8 width) in _get_div() argument
85 return val ? val : clk_div_mask(width) + 1; in _get_div()
103 unsigned int div, unsigned long flags, u8 width) in _get_val() argument
[all …]
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| D | clk-axm5516.c | 82 u32 width; member
97 div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1)); in axxia_divclk_recalc_rate()
117 u32 width; member
131 parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1); in axxia_clkmux_get_parent()
220 .width = 4,
234 .width = 4,
248 .width = 4,
262 .width = 4,
276 .width = 4,
290 .width = 4,
[all …]
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| /linux-4.19.296/drivers/clk/hisilicon/ |
| D | clkdivider-hi6220.c | 23 #define div_mask(width) ((1 << (width)) - 1) argument
40 u8 width; member
56 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
59 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in hi6220_clkdiv_recalc_rate()
68 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_round_rate()
80 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_set_rate()
86 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
106 u8 shift, u8 width, u32 mask_bit, spinlock_t *lock) in hi6220_register_clkdiv() argument
121 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
144 div->width = width; in hi6220_register_clkdiv()
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| /linux-4.19.296/drivers/clk/sunxi-ng/ |
| D | ccu_nkmp.c | 104 n &= (1 << nkmp->n.width) - 1; in ccu_nkmp_recalc_rate()
110 k &= (1 << nkmp->k.width) - 1; in ccu_nkmp_recalc_rate()
116 m &= (1 << nkmp->m.width) - 1; in ccu_nkmp_recalc_rate()
122 p &= (1 << nkmp->p.width) - 1; in ccu_nkmp_recalc_rate()
141 _nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width; in ccu_nkmp_round_rate()
143 _nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width; in ccu_nkmp_round_rate()
145 _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width; in ccu_nkmp_round_rate()
147 _nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1); in ccu_nkmp_round_rate()
172 _nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width; in ccu_nkmp_set_rate()
174 _nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width; in ccu_nkmp_set_rate()
[all …]
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| D | ccu_nkm.c | 84 n &= (1 << nkm->n.width) - 1; in ccu_nkm_recalc_rate()
90 k &= (1 << nkm->k.width) - 1; in ccu_nkm_recalc_rate()
96 m &= (1 << nkm->m.width) - 1; in ccu_nkm_recalc_rate()
119 _nkm.max_n = nkm->n.max ?: 1 << nkm->n.width; in ccu_nkm_round_rate()
121 _nkm.max_k = nkm->k.max ?: 1 << nkm->k.width; in ccu_nkm_round_rate()
123 _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width; in ccu_nkm_round_rate()
159 _nkm.max_n = nkm->n.max ?: 1 << nkm->n.width; in ccu_nkm_set_rate()
161 _nkm.max_k = nkm->k.max ?: 1 << nkm->k.width; in ccu_nkm_set_rate()
163 _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width; in ccu_nkm_set_rate()
170 reg &= ~GENMASK(nkm->n.width + nkm->n.shift - 1, nkm->n.shift); in ccu_nkm_set_rate()
[all …]
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| /linux-4.19.296/drivers/clk/mxs/ |
| D | clk-frac.c | 33 u8 width; member
47 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
50 return tmp_rate >> frac->width; in clk_frac_recalc_rate()
65 tmp <<= frac->width; in clk_frac_round_rate()
73 result = tmp_rate >> frac->width; in clk_frac_round_rate()
74 if ((result << frac->width) < tmp_rate) in clk_frac_round_rate()
91 tmp <<= frac->width; in clk_frac_set_rate()
101 val &= ~(((1 << frac->width) - 1) << frac->shift); in clk_frac_set_rate()
117 void __iomem *reg, u8 shift, u8 width, u8 busy) in mxs_clk_frac() argument
135 frac->width = width; in mxs_clk_frac()
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| /linux-4.19.296/include/video/ |
| D | omapvrfb.h | 42 extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
44 extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
45 extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
47 u16 width, u16 height,
56 static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, in omap_vrfb_adjust_size() argument
58 static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) in omap_vrfb_min_phys_size() argument
60 static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) in omap_vrfb_max_height() argument
63 u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} in omap_vrfb_setup() argument
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| /linux-4.19.296/drivers/clk/imx/ |
| D | clk.h | 61 void __iomem *reg, u8 shift, u8 width,
65 u8 width, void __iomem *busy_reg, u8 busy_shift,
69 void __iomem *reg, u8 shift, u8 width,
73 u8 shift, u8 width, const char * const *parents,
82 u8 shift, u8 width, const char * const *parents, in imx_clk_mux_ldb() argument
87 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); in imx_clk_mux_ldb()
98 void __iomem *reg, u8 shift, u8 width) in imx_clk_divider() argument
101 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider()
105 const char *parent, void __iomem *reg, u8 shift, u8 width, in imx_clk_divider_flags() argument
109 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider_flags()
[all …]
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| /linux-4.19.296/drivers/clk/sprd/ |
| D | sc9860-clk.c | 127 { .shift = 20, .width = 1 }, /* lock_done */
128 { .shift = 19, .width = 1 }, /* div_s */
129 { .shift = 18, .width = 1 }, /* mod_en */
130 { .shift = 17, .width = 1 }, /* sdm_en */
131 { .shift = 0, .width = 0 }, /* refin */
132 { .shift = 11, .width = 2 }, /* ibias */
133 { .shift = 0, .width = 7 }, /* n */
134 { .shift = 57, .width = 7 }, /* nint */
135 { .shift = 32, .width = 23}, /* kint */
136 { .shift = 0, .width = 0 }, /* prediv */
[all …]
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| D | div.c | 18 NULL, div->width, 0); in sprd_div_helper_round_rate()
40 val &= (1 << div->width) - 1; in sprd_div_helper_recalc_rate()
43 div->width); in sprd_div_helper_recalc_rate()
64 div->width, 0); in sprd_div_helper_set_rate()
67 reg &= ~GENMASK(div->width + div->shift - 1, div->shift); in sprd_div_helper_set_rate()
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| /linux-4.19.296/drivers/clk/qcom/ |
| D | clk-regmap-divider.c | 35 val &= BIT(divider->width) - 1; in div_round_ro_rate()
37 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
46 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
57 div = divider_get_val(rate, parent_rate, NULL, divider->width, in div_set_rate()
61 (BIT(divider->width) - 1) << divider->shift, in div_set_rate()
74 div &= BIT(divider->width) - 1; in div_recalc_rate()
77 CLK_DIVIDER_ROUND_CLOSEST, divider->width); in div_recalc_rate()
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| /linux-4.19.296/drivers/clk/rockchip/ |
| D | clk-half-divider.c | 10 #define div_mask(width) ((1 << (width)) - 1) argument
28 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
35 unsigned long *best_parent_rate, u8 width, in clk_half_divider_bestdiv() argument
45 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
87 bestdiv = div_mask(width); in clk_half_divider_bestdiv()
101 divider->width, in clk_half_divider_round_rate()
117 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
125 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
128 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
210 div->width = div_width; in rockchip_clk_register_halfdiv()
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| D | clk-muxgrf.c | 25 u32 width; member
34 unsigned int mask = GENMASK(mux->width - 1, 0); in rockchip_muxgrf_get_parent()
48 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); in rockchip_muxgrf_set_parent()
69 int shift, int width, int mux_flags) in rockchip_clk_register_muxgrf() argument
94 muxgrf_clock->width = width; in rockchip_clk_register_muxgrf()
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| /linux-4.19.296/drivers/clk/ti/ |
| D | divider.c | 29 #define div_mask(d) ((1 << ((d)->width)) - 1)
281 u8 shift, u8 width, s8 latch, in _register_divider() argument
290 if (width + shift > 16) { in _register_divider()
310 div->width = width; in _register_divider()
326 u8 flags, u8 *width, in ti_clk_parse_divider_data() argument
351 *width = fls(val); in ti_clk_parse_divider_data()
376 *width = 0; in ti_clk_parse_divider_data()
383 *width = i; in ti_clk_parse_divider_data()
386 *width = fls(*width); in ti_clk_parse_divider_data()
393 _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width) in _get_div_table_from_setup() argument
[all …]
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| /linux-4.19.296/drivers/media/usb/gspca/stv06xx/ |
| D | stv06xx_hdcs.c | 73 int width, height; member
285 unsigned int width, unsigned int height) in hdcs_set_size() argument
293 width = (width + 3) & ~0x3; in hdcs_set_size()
296 if (width > hdcs->array.width) in hdcs_set_size()
297 width = hdcs->array.width; in hdcs_set_size()
315 x = hdcs->array.left + (hdcs->array.width - width) / 2; in hdcs_set_size()
320 win[3] = (x + width) / 4 - 1; in hdcs_set_size()
327 hdcs->w = width; in hdcs_set_size()
386 hdcs->array.width = HDCS_1X00_DEF_WIDTH; in hdcs_probe_1x00()
448 hdcs->array.width = HDCS_1020_DEF_WIDTH; in hdcs_probe_1020()
[all …]
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| /linux-4.19.296/drivers/media/usb/gspca/ |
| D | stk1135.c | 310 u16 width, height; in stk1135_configure_mt9m112() local
316 width = gspca_dev->pixfmt.width; in stk1135_configure_mt9m112()
318 if (width <= 640 && height <= 512) { /* context A (half readout speed)*/ in stk1135_configure_mt9m112()
319 sensor_write(gspca_dev, 0x1a7, width); in stk1135_configure_mt9m112()
326 sensor_write(gspca_dev, 0x1a1, width); in stk1135_configure_mt9m112()
442 u16 width, height; in sd_start() local
456 width = gspca_dev->pixfmt.width; in sd_start()
458 reg_w(gspca_dev, STK1135_REG_CIEPO + 0, width & 0xff); in sd_start()
459 reg_w(gspca_dev, STK1135_REG_CIEPO + 1, width >> 8); in sd_start()
617 fmt->fmt.pix.width = clamp(fmt->fmt.pix.width, 32U, 1280U); in stk1135_try_fmt()
[all …]
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| /linux-4.19.296/drivers/misc/eeprom/ |
| D | eeprom_93cx6.c | 194 command = (PCI_EEPROM_READ_OPCODE << eeprom->width) | word; in eeprom_93cx6_read()
196 PCI_EEPROM_WIDTH_OPCODE + eeprom->width); in eeprom_93cx6_read()
260 command = (PCI_EEPROM_READ_OPCODE << (eeprom->width + 1)) | byte; in eeprom_93cx6_readb()
262 PCI_EEPROM_WIDTH_OPCODE + eeprom->width + 1); in eeprom_93cx6_readb()
315 command <<= (eeprom->width - 2); in eeprom_93cx6_wren()
318 PCI_EEPROM_WIDTH_OPCODE + eeprom->width); in eeprom_93cx6_wren()
345 command = PCI_EEPROM_WRITE_OPCODE << eeprom->width; in eeprom_93cx6_write()
350 PCI_EEPROM_WIDTH_OPCODE + eeprom->width); in eeprom_93cx6_write()
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| /linux-4.19.296/drivers/clk/actions/ |
| D | owl-divider.c | 22 div_hw->table, div_hw->width, in owl_divider_helper_round_rate()
44 val &= (1 << div_hw->width) - 1; in owl_divider_helper_recalc_rate()
49 div_hw->width); in owl_divider_helper_recalc_rate()
70 div_hw->width, 0); in owl_divider_helper_set_rate()
73 reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift); in owl_divider_helper_set_rate()
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