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Searched refs:writel (Results 1 – 25 of 427) sorted by relevance

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/linux-4.19.296/drivers/irqchip/
Dirq-sun4i.c46 writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_irq_ack()
57 writel(val & ~(1 << irq_off), in sun4i_irq_mask()
69 writel(val | (1 << irq_off), in sun4i_irq_unmask()
104 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); in sun4i_of_init()
105 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); in sun4i_of_init()
106 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); in sun4i_of_init()
109 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); in sun4i_of_init()
110 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); in sun4i_of_init()
111 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); in sun4i_of_init()
114 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_of_init()
[all …]
Dirq-aspeed-vic.c73 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
74 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
77 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
78 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
81 writel(0, vic->base + AVIC_INT_SELECT); in vic_init_hw()
82 writel(0, vic->base + AVIC_INT_SELECT + 4); in vic_init_hw()
94 writel(0xffffffff, vic->base + AVIC_EDGE_CLR); in vic_init_hw()
95 writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4); in vic_init_hw()
125 writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4); in avic_ack_irq()
134 writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4); in avic_mask_irq()
[all …]
Dirq-vic.c105 writel(VIC_VECT_CNTL_ENABLE | i, reg); in vic_init2()
108 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2()
121 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
122 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic()
125 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic()
126 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); in resume_one_vic()
130 writel(vic->soft_int, base + VIC_INT_SOFT); in resume_one_vic()
131 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); in resume_one_vic()
156 writel(vic->resume_irqs, base + VIC_INT_ENABLE); in suspend_one_vic()
157 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); in suspend_one_vic()
[all …]
Dirq-armada-370-xp.c177 writel(hwirq, main_int_base + in armada_370_xp_irq_mask()
180 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_mask()
189 writel(hwirq, main_int_base + in armada_370_xp_irq_unmask()
192 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_unmask()
293 writel(reg, per_cpu_int_base + in armada_370_xp_msi_init()
297 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); in armada_370_xp_msi_init()
326 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); in armada_xp_set_affinity()
351 writel(hw, per_cpu_int_base + in armada_370_xp_mpic_irq_map()
354 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); in armada_370_xp_mpic_irq_map()
380 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); in armada_xp_mpic_smp_cpu_init()
[all …]
/linux-4.19.296/drivers/i2c/busses/
Di2c-lpc2k.c92 writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_reset()
93 writel(0, i2c->base + LPC24XX_I2ADDR); in i2c_lpc2k_reset()
94 writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_reset()
105 writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_clear_arb()
138 writel(data, i2c->base + LPC24XX_I2DAT); in i2c_lpc2k_pump_msg()
139 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_pump_msg()
149 writel(i2c->msg->buf[i2c->msg_idx], in i2c_lpc2k_pump_msg()
153 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_pump_msg()
154 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_pump_msg()
169 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_pump_msg()
[all …]
Di2c-bcm-kona.c176 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
182 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
189 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
196 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
208 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, in bcm_kona_i2c_enable_clock()
214 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, in bcm_kona_i2c_disable_clock()
228 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, in bcm_kona_i2c_isr()
231 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); in bcm_kona_i2c_isr()
264 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); in bcm_kona_send_i2c_cmd()
276 writel(0, dev->base + IER_OFFSET); in bcm_kona_send_i2c_cmd()
[all …]
Di2c-sirf.c115 writel(regval, in i2c_sirfsoc_queue_cmd()
128 writel(regval, in i2c_sirfsoc_queue_cmd()
130 writel(siic->buf[siic->finished_len++], in i2c_sirfsoc_queue_cmd()
137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); in i2c_sirfsoc_queue_cmd()
148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq()
160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, in i2c_sirfsoc_irq()
175 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq()
191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address()
199 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address()
210 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, in i2c_sirfsoc_xfer_msg()
[all …]
Di2c-exynos5.c263 writel(readl(i2c->regs + HSI2C_INT_STATUS), in exynos5_i2c_clr_pend_irq()
342 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); in exynos5_i2c_set_timing()
343 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); in exynos5_i2c_set_timing()
344 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing()
346 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); in exynos5_i2c_set_timing()
347 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); in exynos5_i2c_set_timing()
348 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing()
350 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); in exynos5_i2c_set_timing()
377 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
379 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), in exynos5_i2c_init()
[all …]
Di2c-bcm-iproc.c149 writel(tmp, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_isr()
153 writel(val, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_isr()
164 writel(status, iproc_i2c->base + IS_OFFSET); in bcm_iproc_i2c_isr()
177 writel(val, iproc_i2c->base + CFG_OFFSET); in bcm_iproc_i2c_init()
184 writel(val, iproc_i2c->base + CFG_OFFSET); in bcm_iproc_i2c_init()
188 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); in bcm_iproc_i2c_init()
190 writel(0, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_init()
193 writel(0xffffffff, iproc_i2c->base + IS_OFFSET); in bcm_iproc_i2c_init()
208 writel(val, iproc_i2c->base + CFG_OFFSET); in bcm_iproc_i2c_enable_disable()
271 writel(addr, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
[all …]
Di2c-axxia.c115 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); in i2c_int_disable()
123 writel(int_en | mask, idev->base + MST_INT_ENABLE); in i2c_int_enable()
148 writel(0x01, idev->base + SOFT_RESET); in axxia_i2c_init()
158 writel(0x1, idev->base + GLOBAL_CONTROL); in axxia_i2c_init()
173 writel(t_high, idev->base + SCL_HIGH_PERIOD); in axxia_i2c_init()
175 writel(t_low, idev->base + SCL_LOW_PERIOD); in axxia_i2c_init()
177 writel(t_setup, idev->base + SDA_SETUP_TIME); in axxia_i2c_init()
179 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); in axxia_i2c_init()
181 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); in axxia_i2c_init()
196 writel(prescale, idev->base + TIMER_CLOCK_DIV); in axxia_i2c_init()
[all …]
/linux-4.19.296/drivers/gpio/
Dgpio-sta2x11.c73 writel(bit, &regs->dats); in gsta_gpio_set()
75 writel(bit, &regs->datc); in gsta_gpio_set()
94 writel(bit, &regs->dirs); in gsta_gpio_direction_output()
97 writel(bit, &regs->dats); in gsta_gpio_direction_output()
99 writel(bit, &regs->datc); in gsta_gpio_direction_output()
109 writel(bit, &regs->dirc); in gsta_gpio_direction_input()
177 writel(val | bit, &regs->afsela); in gsta_set_config()
186 writel(bit, &regs->dirs); in gsta_set_config()
187 writel(bit, &regs->datc); in gsta_set_config()
190 writel(bit, &regs->dirs); in gsta_set_config()
[all …]
/linux-4.19.296/drivers/isdn/hisax/
Dtelespci.c51 writel(WRITE_ADDR_ISAC | off, adr + 0x200); in readisac()
55 writel(READ_DATA_ISAC, adr + 0x200); in readisac()
68 writel(WRITE_ADDR_ISAC | off, adr + 0x200); in writeisac()
72 writel(WRITE_DATA_ISAC | data, adr + 0x200); in writeisac()
83 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in readhscx()
87 writel(READ_DATA_HSCX, adr + 0x200); in readhscx()
99 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in writehscx()
103 writel(WRITE_DATA_HSCX | data, adr + 0x200); in writehscx()
117 writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200); in read_fifo_isac()
119 writel(READ_DATA_ISAC, adr + 0x200); in read_fifo_isac()
[all …]
/linux-4.19.296/drivers/nvmem/
Dimx-ocotp.c122 writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR); in imx_ocotp_clr_err_if_set()
225 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); in imx_ocotp_set_imx6_timing()
246 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); in imx_ocotp_set_imx7_timing()
319 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); in imx_ocotp_write()
347 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); in imx_ocotp_write()
348 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); in imx_ocotp_write()
349 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); in imx_ocotp_write()
350 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); in imx_ocotp_write()
353 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); in imx_ocotp_write()
354 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); in imx_ocotp_write()
[all …]
Drockchip-efuse.c76 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
79 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
82 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
86 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
90 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
96 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
133 writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | in rockchip_rk3328_efuse_read()
143 writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS); in rockchip_rk3328_efuse_read()
185 writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, in rockchip_rk3399_efuse_read()
189 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | in rockchip_rk3399_efuse_read()
[all …]
/linux-4.19.296/drivers/misc/
Dspear13xx_pcie_gadget.c72 writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
74 writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
82 writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
84 writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
123 writel(val, va_address); in spear_dbi_write_reg()
247 writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID), in pcie_gadget_link_store()
250 writel(readl(&app_reg->app_ctrl_0) in pcie_gadget_link_store()
345 writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID), in pcie_gadget_inta_store()
348 writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID), in pcie_gadget_inta_store()
383 writel(ven_msi, &app_reg->ven_msi_1); in pcie_gadget_send_msi_store()
[all …]
Dtifm_7xx1.c54 writel(TIFM_IRQ_ENABLE, fm->addr + FM_CLEAR_INTERRUPT_ENABLE); in tifm_7xx1_isr()
69 writel(irq_status, fm->addr + FM_INTERRUPT_STATUS); in tifm_7xx1_isr()
74 writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE); in tifm_7xx1_isr()
87 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_toggle_sock_power()
101 writel(readl(sock_addr + SOCK_CONTROL) | TIFM_CTRL_LED, in tifm_7xx1_toggle_sock_power()
109 writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00, in tifm_7xx1_toggle_sock_power()
121 writel(readl(sock_addr + SOCK_CONTROL) & (~TIFM_CTRL_LED), in tifm_7xx1_toggle_sock_power()
129 writel((~TIFM_CTRL_POWER_MASK) & readl(sock_addr + SOCK_CONTROL), in tifm_7xx1_sock_power_off()
175 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_switch_media()
202 writel(TIFM_IRQ_FIFOMASK(socket_change_set) in tifm_7xx1_switch_media()
[all …]
/linux-4.19.296/drivers/virtio/
Dvirtio_mmio.c117 writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features()
121 writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features()
141 writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features()
142 writel((u32)(vdev->features >> 32), in vm_finalize_features()
145 writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features()
146 writel((u32)vdev->features, in vm_finalize_features()
224 writel(le32_to_cpu(l), base + offset); in vm_set()
228 writel(le32_to_cpu(l), base + offset); in vm_set()
230 writel(le32_to_cpu(l), base + offset + sizeof l); in vm_set()
261 writel(status, vm_dev->base + VIRTIO_MMIO_STATUS); in vm_set_status()
[all …]
/linux-4.19.296/drivers/rtc/
Drtc-stmp3xxx.c91 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG); in stmp3xxx_wdt_set_timeout()
92 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, in stmp3xxx_wdt_set_timeout()
94 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, in stmp3xxx_wdt_set_timeout()
97 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, in stmp3xxx_wdt_set_timeout()
99 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, in stmp3xxx_wdt_set_timeout()
171 writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS); in stmp3xxx_rtc_set_mmss()
182 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ, in stmp3xxx_rtc_interrupt()
196 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | in stmp3xxx_alarm_irq_enable()
200 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, in stmp3xxx_alarm_irq_enable()
203 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | in stmp3xxx_alarm_irq_enable()
[all …]
Drtc-sun6i.c175 writel(val, rtc->base + SUN6I_LOSC_CTRL); in sun6i_rtc_osc_set_parent()
218 writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC, in sun6i_rtc_clk_init()
290 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_alarmirq()
313 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, in sun6i_rtc_setaie()
318 writel(alrm_val, chip->base + SUN6I_ALRM_EN); in sun6i_rtc_setaie()
319 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); in sun6i_rtc_setaie()
320 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); in sun6i_rtc_setaie()
407 writel(0, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_setalarm()
410 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_setalarm()
471 writel(time, chip->base + SUN6I_RTC_HMS); in sun6i_rtc_settime()
[all …]
/linux-4.19.296/drivers/memstick/host/
Dtifm_ms.c142 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data()
144 writel(host->io_word, sock->addr + SOCK_MS_DATA); in tifm_ms_write_data()
157 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data()
238 writel(TIFM_MS_SYS_FDIR in tifm_ms_transfer_data()
241 writel(host->io_word, sock->addr + SOCK_MS_DATA); in tifm_ms_transfer_data()
243 writel(TIFM_MS_SYS_FDIR in tifm_ms_transfer_data()
246 writel(0, sock->addr + SOCK_MS_DATA); in tifm_ms_transfer_data()
279 writel(TIFM_FIFO_INT_SETALL, in tifm_ms_issue_cmd()
281 writel(TIFM_FIFO_ENABLE, in tifm_ms_issue_cmd()
294 writel(ilog2(data_len) - 2, in tifm_ms_issue_cmd()
[all …]
Djmb38x_ms.c238 writel(host->io_word[0], host->addr + DATA); in jmb38x_ms_write_data()
358 writel(host->io_word[0], host->addr + TPC_P0); in jmb38x_ms_transfer_data()
359 writel(host->io_word[1], host->addr + TPC_P1); in jmb38x_ms_transfer_data()
361 writel(host->io_word[0], host->addr + DATA); in jmb38x_ms_transfer_data()
431 writel(sg_dma_address(&host->req->sg), in jmb38x_ms_issue_cmd()
433 writel(((1 << 16) & BLOCK_COUNT_MASK) in jmb38x_ms_issue_cmd()
436 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL); in jmb38x_ms_issue_cmd()
438 writel(((1 << 16) & BLOCK_COUNT_MASK) in jmb38x_ms_issue_cmd()
446 writel(t_val, host->addr + INT_STATUS_ENABLE); in jmb38x_ms_issue_cmd()
447 writel(t_val, host->addr + INT_SIGNAL_ENABLE); in jmb38x_ms_issue_cmd()
[all …]
/linux-4.19.296/drivers/auxdisplay/
Darm-charlcd.c83 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_interrupt()
99 writel(0x00, lcd->virtbase + CHAR_MASK); in charlcd_wait_complete_irq()
133 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_char()
151 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_char()
167 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_bf()
169 writel(0x01, lcd->virtbase + CHAR_MASK); in charlcd_4bit_read_bf()
191 writel(cmdhi, lcd->virtbase + CHAR_COM); in charlcd_4bit_command()
193 writel(cmdlo, lcd->virtbase + CHAR_COM); in charlcd_4bit_command()
202 writel(chhi, lcd->virtbase + CHAR_DAT); in charlcd_4bit_char()
204 writel(chlo, lcd->virtbase + CHAR_DAT); in charlcd_4bit_char()
[all …]
/linux-4.19.296/drivers/iio/adc/
Dmxs-lradc-adc.c165 writel(LRADC_CTRL1_LRADC_IRQ_EN(0), in mxs_lradc_adc_read_single()
167 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
171 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, in mxs_lradc_adc_read_single()
174 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, in mxs_lradc_adc_read_single()
178 writel(LRADC_CTRL4_LRADCSELECT_MASK(0), in mxs_lradc_adc_read_single()
180 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
182 writel(0, adc->base + LRADC_CH(0)); in mxs_lradc_adc_read_single()
185 writel(LRADC_CTRL1_LRADC_IRQ_EN(0), in mxs_lradc_adc_read_single()
187 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
201 writel(LRADC_CTRL1_LRADC_IRQ_EN(0), in mxs_lradc_adc_read_single()
[all …]
/linux-4.19.296/drivers/clk/mediatek/
Dclk-pll.c97 writel(r, pll->tuner_en_addr); in __mtk_pll_tuner_enable()
100 writel(r, pll->tuner_addr); in __mtk_pll_tuner_enable()
110 writel(r, pll->tuner_en_addr); in __mtk_pll_tuner_disable()
113 writel(r, pll->tuner_addr); in __mtk_pll_tuner_disable()
135 writel(val, pll->pd_addr); in mtk_pll_set_rate_regs()
143 writel(val, pll->pcw_addr); in mtk_pll_set_rate_regs()
150 writel(con1, pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
152 writel(con1 + 1, pll->tuner_addr); in mtk_pll_set_rate_regs()
252 writel(r, pll->pwr_addr); in mtk_pll_prepare()
256 writel(r, pll->pwr_addr); in mtk_pll_prepare()
[all …]
/linux-4.19.296/include/linux/
Dgoldfish.h16 writel(lower_32_bits(addr), portl); in gf_write_ptr()
18 writel(upper_32_bits(addr), porth); in gf_write_ptr()
26 writel(lower_32_bits(addr), portl); in gf_write_dma_addr()
28 writel(upper_32_bits(addr), porth); in gf_write_dma_addr()

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