/linux-4.19.296/drivers/irqchip/ |
D | irq-gic-common.c | 85 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); in gic_configure_irq() 110 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, in gic_dist_config() 117 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); in gic_dist_config() 124 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config() 126 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config() 143 writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR); in gic_cpu_config() 144 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); in gic_cpu_config() 145 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); in gic_cpu_config() 151 writel_relaxed(GICD_INT_DEF_PRI_X4, in gic_cpu_config()
|
D | irq-sa11x0.c | 43 writel_relaxed(reg, iobase + ICMR); in sa1100_mask_irq() 52 writel_relaxed(reg, iobase + ICMR); in sa1100_unmask_irq() 103 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); in sa1100irq_suspend() 113 writel_relaxed(st->iccr, iobase + ICCR); in sa1100irq_resume() 114 writel_relaxed(st->iclr, iobase + ICLR); in sa1100irq_resume() 116 writel_relaxed(st->icmr, iobase + ICMR); in sa1100irq_resume() 158 writel_relaxed(0, iobase + ICMR); in sa11x0_init_irq_nodt() 161 writel_relaxed(0, iobase + ICLR); in sa11x0_init_irq_nodt() 167 writel_relaxed(1, iobase + ICCR); in sa11x0_init_irq_nodt()
|
D | irq-sirfsoc.c | 79 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_init() 80 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_init() 82 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_init() 83 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_init() 116 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_resume() 117 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_resume() 118 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_resume() 119 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_resume()
|
D | irq-tegra.c | 97 writel_relaxed(mask, base + reg); in tegra_ictlr_write_mask() 160 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_suspend() 163 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_suspend() 166 writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET); in tegra_ictlr_suspend() 182 writel_relaxed(lic->cpu_iep[i], in tegra_ictlr_resume() 184 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_resume() 185 writel_relaxed(lic->cpu_ier[i], in tegra_ictlr_resume() 187 writel_relaxed(lic->cop_iep[i], in tegra_ictlr_resume() 189 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_resume() 190 writel_relaxed(lic->cop_ier[i], in tegra_ictlr_resume() [all …]
|
D | irq-sni-exiu.c | 56 writel_relaxed(val, data->base + EIMASK); in exiu_irq_mask() 66 writel_relaxed(val, data->base + EIMASK); in exiu_irq_unmask() 76 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_enable() 79 writel_relaxed(val, data->base + EIMASK); in exiu_irq_enable() 93 writel_relaxed(val, data->base + EILVL); in exiu_irq_set_type() 100 writel_relaxed(val, data->base + EIEDG); in exiu_irq_set_type() 102 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_set_type() 205 writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR); in exiu_init() 206 writel_relaxed(0xFFFFFFFF, data->base + EIMASK); in exiu_init()
|
D | irq-hip04.c | 99 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR + in hip04_mask_irq() 109 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + in hip04_unmask_irq() 116 writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI); in hip04_eoi_irq() 165 writel_relaxed(val | bit, reg); in hip04_irq_set_affinity() 188 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in hip04_handle_irq() 237 writel_relaxed(0, base + GIC_DIST_CTRL); in hip04_irq_dist_init() 245 writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); in hip04_irq_dist_init() 249 writel_relaxed(1, base + GIC_DIST_CTRL); in hip04_irq_dist_init() 276 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); in hip04_irq_cpu_init() 277 writel_relaxed(1, base + GIC_CPU_CTRL); in hip04_irq_cpu_init() [all …]
|
D | irq-gic.c | 196 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); in gic_poke_irq() 232 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); in gic_eoi_irq() 241 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); in gic_eoimode1_eoi_irq() 357 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in gic_handle_irq() 363 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in gic_handle_irq() 365 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); in gic_handle_irq() 466 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); in gic_cpu_if_up() 474 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up() 485 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); in gic_dist_init() 494 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); in gic_dist_init() [all …]
|
D | irq-dw-apb-ictl.c | 60 writel_relaxed(~0, gc->reg_base + ct->regs.enable); in dw_apb_ictl_resume() 61 writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); in dw_apb_ictl_resume() 112 writel_relaxed(~0, iobase + APB_INT_MASK_L); in dw_apb_ictl_init() 113 writel_relaxed(~0, iobase + APB_INT_MASK_H); in dw_apb_ictl_init() 114 writel_relaxed(~0, iobase + APB_INT_ENABLE_L); in dw_apb_ictl_init() 115 writel_relaxed(~0, iobase + APB_INT_ENABLE_H); in dw_apb_ictl_init()
|
D | irq-mvebu-icu.c | 59 writel_relaxed(msg[0].address_hi, icu->base + ICU_SETSPI_NSR_AH); in mvebu_icu_init() 60 writel_relaxed(msg[0].address_lo, icu->base + ICU_SETSPI_NSR_AL); in mvebu_icu_init() 61 writel_relaxed(msg[1].address_hi, icu->base + ICU_CLRSPI_NSR_AH); in mvebu_icu_init() 62 writel_relaxed(msg[1].address_lo, icu->base + ICU_CLRSPI_NSR_AL); in mvebu_icu_init() 85 writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); in mvebu_icu_write_msg() 97 writel_relaxed(icu_int, in mvebu_icu_write_msg() 99 writel_relaxed(icu_int, in mvebu_icu_write_msg() 263 writel_relaxed(0x0, icu->base + ICU_INT_CFG(i)); in mvebu_icu_probe()
|
/linux-4.19.296/drivers/rtc/ |
D | rtc-rtd119x.c | 62 writel_relaxed(val, data->base + RTD_RTCCR); in rtd119x_rtc_reset() 77 writel_relaxed(0x5a, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled() 79 writel_relaxed(0, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled() 146 writel_relaxed((tm->tm_sec << 1) & RTD_RTCSEC_RTCSEC_MASK, data->base + RTD_RTCSEC); in rtd119x_rtc_set_time() 147 writel_relaxed(tm->tm_min & RTD_RTCMIN_RTCMIN_MASK, data->base + RTD_RTCMIN); in rtd119x_rtc_set_time() 148 writel_relaxed(tm->tm_hour & RTD_RTCHR_RTCHR_MASK, data->base + RTD_RTCHR); in rtd119x_rtc_set_time() 149 writel_relaxed(day & RTD_RTCDATE1_RTCDATE1_MASK, data->base + RTD_RTCDATE1); in rtd119x_rtc_set_time() 150 writel_relaxed((day >> 8) & RTD_RTCDATE2_RTCDATE2_MASK, data->base + RTD_RTCDATE2); in rtd119x_rtc_set_time() 198 writel_relaxed(RTD_RTCACR_RTCPWR, data->base + RTD_RTCACR); in rtd119x_rtc_probe() 202 writel_relaxed(0, data->base + RTD_RTCMIN); in rtd119x_rtc_probe() [all …]
|
D | rtc-st-lpc.c | 64 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm() 66 writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF); in st_rtc_set_hw_alarm() 67 writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF); in st_rtc_set_hw_alarm() 68 writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_set_hw_alarm() 70 writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm() 119 writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF); in st_rtc_set_time() 120 writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF); in st_rtc_set_time() 121 writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF); in st_rtc_set_time() 282 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_suspend() 283 writel_relaxed(0, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_suspend() [all …]
|
D | rtc-sa1100.c | 61 writel_relaxed(0, info->rtsr); in sa1100_rtc_interrupt() 68 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); in sa1100_rtc_interrupt() 77 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); in sa1100_rtc_interrupt() 83 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); in sa1100_rtc_interrupt() 109 writel_relaxed(rtsr, info->rtsr); in sa1100_rtc_alarm_irq_enable() 130 writel_relaxed(time, info->rcnr); in sa1100_rtc_set_time() 155 writel_relaxed(readl_relaxed(info->rtsr) & in sa1100_rtc_set_alarm() 157 writel_relaxed(time, info->rtar); in sa1100_rtc_set_alarm() 159 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm() 161 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm() [all …]
|
/linux-4.19.296/drivers/gpio/ |
D | gpio-sa1100.c | 52 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set() 68 writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr); in sa1100_direction_input() 81 writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr); in sa1100_direction_output() 121 writel_relaxed(grer, base + R_GRER); in sa1100_update_edge_regs() 122 writel_relaxed(gfer, base + R_GFER); in sa1100_update_edge_regs() 157 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); in sa1100_gpio_ack() 241 writel_relaxed(mask, gedr); in sa1100_gpio_handler() 262 writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER); in sa1100_gpio_suspend() 263 writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER); in sa1100_gpio_suspend() 268 writel_relaxed(readl_relaxed(sgc->membase + R_GEDR), in sa1100_gpio_suspend() [all …]
|
D | gpio-pxa.c | 284 writel_relaxed(value, base + GPDR_OFFSET); in pxa_gpio_direction_input() 298 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); in pxa_gpio_direction_output() 313 writel_relaxed(tmp, base + GPDR_OFFSET); in pxa_gpio_direction_output() 331 writel_relaxed(GPIO_bit(offset), in pxa_gpio_set() 399 writel_relaxed(grer, c->regbase + GRER_OFFSET); in update_edge_detect() 400 writel_relaxed(gfer, c->regbase + GFER_OFFSET); in update_edge_detect() 426 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type() 428 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type() 460 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); in pxa_gpio_demux_handler() 497 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); in pxa_ack_muxed_gpio() [all …]
|
D | gpio-omap.c | 112 writel_relaxed(l, reg); in omap_set_gpio_direction() 132 writel_relaxed(l, reg); in omap_set_gpio_dataout_reg() 148 writel_relaxed(l, reg); in omap_set_gpio_dataout_mask() 175 writel_relaxed(l, reg + bank->regs->set_dataout); in omap_set_gpio_dataout_reg_multiple() 179 writel_relaxed(l, reg + bank->regs->clr_dataout); in omap_set_gpio_dataout_reg_multiple() 191 writel_relaxed(l, reg); in omap_set_gpio_dataout_mask_multiple() 220 writel_relaxed(l, base + reg); in omap_gpio_rmw() 229 writel_relaxed(bank->dbck_enable_mask, in omap_gpio_dbck_enable() 242 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable() 282 writel_relaxed(debounce, reg); in omap2_set_gpio_debounce() [all …]
|
D | gpio-davinci.c | 78 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction() 82 writel_relaxed(temp, &g->dir); in __davinci_direction() 129 writel_relaxed(__gpio_mask(offset), in davinci_gpio_set() 297 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable() 298 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable() 312 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable() 314 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable() 361 writel_relaxed(status, &g->intstat); in gpio_irq_handler() 425 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) in gpio_irq_type_unbanked() 427 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) in gpio_irq_type_unbanked() [all …]
|
/linux-4.19.296/drivers/i2c/busses/ |
D | i2c-st.c | 202 writel_relaxed(readl_relaxed(reg) | mask, reg); in st_i2c_set_bits() 207 writel_relaxed(readl_relaxed(reg) & ~mask, reg); in st_i2c_clr_bits() 283 writel_relaxed(val, i2c_dev->base + SSC_CLR); in st_i2c_hw_config() 287 writel_relaxed(val, i2c_dev->base + SSC_CTL); in st_i2c_hw_config() 294 writel_relaxed(val, i2c_dev->base + SSC_BRG); in st_i2c_hw_config() 297 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); in st_i2c_hw_config() 300 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); in st_i2c_hw_config() 304 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); in st_i2c_hw_config() 308 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); in st_i2c_hw_config() 312 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); in st_i2c_hw_config() [all …]
|
D | i2c-hix5hd2.c | 105 writel_relaxed(val, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_pend_irq() 112 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_all_irq() 117 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_disable_irq() 122 writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL, in hix5hd2_i2c_enable_irq() 133 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate() 138 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); in hix5hd2_i2c_drv_setrate() 139 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); in hix5hd2_i2c_drv_setrate() 142 writel_relaxed(val, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate() 197 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); in hix5hd2_rw_handle_stop() 207 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); in hix5hd2_read_handle() [all …]
|
/linux-4.19.296/drivers/cpufreq/ |
D | s5pv210-cpufreq.c | 223 writel_relaxed(tmp1, reg); in s5pv210_set_refresh() 303 writel_relaxed(reg, S5P_CLK_DIV2); in s5pv210_target() 318 writel_relaxed(reg, S5P_CLK_SRC2); in s5pv210_target() 336 writel_relaxed(reg, S5P_CLK_SRC0); in s5pv210_target() 361 writel_relaxed(reg, S5P_CLK_DIV0); in s5pv210_target() 375 writel_relaxed(reg, S5P_ARM_MCS_CON); in s5pv210_target() 379 writel_relaxed(0x2cf, S5P_APLL_LOCK); in s5pv210_target() 387 writel_relaxed(APLL_VAL_1000, S5P_APLL_CON); in s5pv210_target() 389 writel_relaxed(APLL_VAL_800, S5P_APLL_CON); in s5pv210_target() 404 writel_relaxed(reg, S5P_CLK_SRC2); in s5pv210_target() [all …]
|
/linux-4.19.296/drivers/clk/tegra/ |
D | clk-tegra210.c | 506 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable() 516 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start() 528 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable() 538 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start() 558 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw() 567 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war() 569 writel_relaxed(val, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war() 581 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); in tegra210_venc_mbist_war() 585 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war() 587 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war() [all …]
|
D | clk-periph-gate.c | 33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg)) 35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg)) 40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) 87 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable() 88 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable() 90 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
|
/linux-4.19.296/drivers/media/rc/ |
D | ir-hix5hd2.c | 103 writel_relaxed(0x01, priv->base + IR_ENABLE); in hix5hd2_ir_config() 121 writel_relaxed(val, priv->base + IR_CONFIG); in hix5hd2_ir_config() 123 writel_relaxed(0x00, priv->base + IR_INTM); in hix5hd2_ir_config() 125 writel_relaxed(0x01, priv->base + IR_START); in hix5hd2_ir_config() 172 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt() 201 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt() 203 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt() 337 writel_relaxed(0x01, priv->base + IR_ENABLE); in hix5hd2_ir_resume() 338 writel_relaxed(0x00, priv->base + IR_INTM); in hix5hd2_ir_resume() 339 writel_relaxed(0xff, priv->base + IR_INTC); in hix5hd2_ir_resume() [all …]
|
D | tango-ir.c | 117 writel_relaxed(rc5_stat, ir->rc5_base + IR_INT); in tango_ir_irq() 120 writel_relaxed(rc6_stat, ir->rc6_base + RC6_CTRL); in tango_ir_irq() 152 writel_relaxed(rc5_ctrl, ir->rc5_base + IR_CTRL); in tango_change_protocol() 153 writel_relaxed(rc6_ctrl, ir->rc6_base + RC6_CTRL); in tango_change_protocol() 223 writel_relaxed(val, ir->rc5_base + IR_NEC_CTRL); in tango_ir_probe() 228 writel_relaxed(DISABLE_NEC, ir->rc5_base + IR_CTRL); in tango_ir_probe() 229 writel_relaxed(clkdiv, ir->rc5_base + IR_RC5_CLK_DIV); in tango_ir_probe() 230 writel_relaxed(ACK_IR_INT, ir->rc5_base + IR_INT); in tango_ir_probe() 235 writel_relaxed(ACK_RC6_INT, ir->rc6_base + RC6_CTRL); in tango_ir_probe() 236 writel_relaxed((clkdiv >> 2) << 18 | clkdiv, ir->rc6_base + RC6_CLKDIV); in tango_ir_probe()
|
/linux-4.19.296/drivers/clk/hisilicon/ |
D | clk-hix5hd2.c | 179 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare() 181 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare() 186 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare() 191 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare() 196 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare() 208 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare() 224 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable() 229 writel_relaxed(val, clk->phy_reg); in clk_complex_enable() 242 writel_relaxed(val, clk->ctrl_reg); in clk_complex_disable() 247 writel_relaxed(val, clk->phy_reg); in clk_complex_disable()
|
/linux-4.19.296/drivers/clk/mxs/ |
D | clk-imx28.c | 79 writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); in mxs_saif_clkmux_select() 80 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); in mxs_saif_clkmux_select() 90 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init() 93 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); in clk_misc_init() 96 writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); in clk_misc_init() 101 writel_relaxed(val, SAIF0); in clk_misc_init() 105 writel_relaxed(val, SAIF1); in clk_misc_init() 110 writel_relaxed(val, ENET); in clk_misc_init() 116 writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); in clk_misc_init() 125 writel_relaxed(val, FRAC0); in clk_misc_init()
|