xref: /wlan-driver/qca-wifi-host-cmn/hif/src/adrastea_reg_def.h (revision 5113495b16420b49004c444715d2daae2066e7dc) !
1 /*
2  * Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef ADRASTEA_REG_DEF_H
20 #define ADRASTEA_REG_DEF_H
21 
22 /*
23  *  Start auto-generated headers from register parser
24  *
25  *  DO NOT CHANGE MANUALLY
26 */
27 
28 
29 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___S 1
30 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___S 10
31 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW (0x00241000)
32 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
33 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___POR 0x0
34 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
35 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___M 0x003FFFFF
36 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___M 0x00000001
37 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___POR 0x0
38 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___S 0
39 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2 (0x00030028)
40 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___POR 0x00000000
41 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___POR 0x0
42 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___POR 0x000
43 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW (0x00244000)
44 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___M 0x00000001
45 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___M 0x000003FF
46 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___RWC QCSR_REG_RW
47 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___POR 0x00000000
48 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___RWC QCSR_REG_RO
49 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___POR 0x0
50 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE (0x00032060)
51 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___S 0
52 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___POR 0x00000000
53 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___S 0
54 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6 (0x00030038)
55 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___POR 0x0
56 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH (0x00032064)
57 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___POR 0x000000
58 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___M 0xFFFFFFFF
59 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___S 0
60 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___POR 0x0
61 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___M 0x00FFFFFF
62 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___M 0x00000200
63 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___POR 0x0
64 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___S 1
65 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
66 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___M 0x003FFFFF
67 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___M 0xFFFFFFFF
68 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___S 0
69 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___M 0x003FFFFF
70 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___S 10
71 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___RWC QCSR_REG_RW
72 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___POR 0x0
73 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___M 0x00000010
74 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___M 0x00000080
75 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___S 0
76 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___M 0x00000010
77 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___M 0xFFFFFFFF
78 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
79 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___M 0x003FFFFF
80 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___S 17
81 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___S 0
82 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___M 0x0003FFFF
83 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___RWC QCSR_REG_RW
84 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___RWC QCSR_REG_RO
85 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___M 0x00000002
86 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___M 0x0000FFFF
87 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___M 0x00FFF000
88 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___M 0x00FFFFFF
89 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___S 0
90 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___M 0x00000200
91 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___RWC QCSR_REG_RW
92 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4 (0x00030030)
93 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___POR 0x00000000
94 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___RWC QCSR_REG_RW
95 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___M 0xFFFFFFFF
96 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___M 0x00000200
97 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___POR 0x0
98 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___M 0x00000100
99 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___POR 0x00000000
100 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___S 4
101 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___S 0
102 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___POR 0x0
103 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___RWC QCSR_REG_RO
104 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___M 0x00000001
105 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX (0x00240040)
106 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS (0x00240038)
107 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___M 0xFFFFFFFF
108 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___S 10
109 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___RWC QCSR_REG_RW
110 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___S 0
111 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___M 0x003FFFFF
112 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___POR 0x0
113 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR (0x002F1008)
114 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___RWC QCSR_REG_RO
115 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___POR 0x00000000
116 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___POR 0x00000000
117 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___S 0
118 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___S 0
119 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___M 0x00000080
120 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___S 0
121 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___M 0xFFFFFFFF
122 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___POR 0x00000000
123 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___M 0x00000010
124 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___S 0
125 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___S 0
126 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___S 0
127 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___S 10
128 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___POR 0x0
129 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___S 0
130 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___S 10
131 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___S 0
132 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___M 0x00000FFF
133 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___S 0
134 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___M 0x00000002
135 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___S 0
136 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20 (0x00030070)
137 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___POR 0x00000000
138 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___POR 0x00000000
139 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12 (0x00032030)
140 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___M 0x00000002
141 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___POR 0x000
142 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___S 18
143 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___POR 0x0
144 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___S 0
145 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___M 0xFFFFFFFF
146 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___S 0
147 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
148 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___M 0x00000FFF
149 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB (0x00032070)
150 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___M 0x00000080
151 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___S 0
152 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___S 10
153 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___POR 0x00000000
154 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___S 0
155 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___M 0xFFFFFFFF
156 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___POR 0x00000000
157 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___S 0
158 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___S 0
159 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___M 0x00000200
160 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___M 0x003FFFFF
161 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___POR 0x0
162 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___POR 0x0
163 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___S 0
164 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___POR 0x00000000
165 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___S 9
166 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___S 0
167 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___S 9
168 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___S 0
169 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___RWC QCSR_REG_RW
170 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___S 0
171 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___M 0xFFFFFFFF
172 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___M 0xFFFFFFFF
173 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___S 0
174 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___M 0x0000FFFF
175 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___POR 0x00000000
176 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___M 0x003FFFFF
177 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___POR 0x000000
178 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___RWC QCSR_REG_RO
179 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___S 0
180 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___S 0
181 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___POR 0x00000000
182 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___POR 0x00000000
183 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___M 0x00000008
184 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___M 0xFFFFFFFF
185 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___POR 0x00000000
186 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___M 0xFFFFFFFF
187 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___POR 0x00000000
188 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___POR 0x00000000
189 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___M 0xFFFFFFFF
190 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___POR 0x00000000
191 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___S 0
192 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___S 0
193 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___RWC QCSR_REG_RO
194 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13 (0x00032034)
195 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___S 0
196 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3 (0x0003002C)
197 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___M 0x003FFFFF
198 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___S 0
199 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID (0x000300E0)
200 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22 (0x00032058)
201 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___RWC QCSR_REG_RO
202 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___S 0
203 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___M 0xFFFFFFFF
204 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___M 0x00000020
205 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___M 0x003FFFFF
206 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___POR 0x0
207 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___S 0
208 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___S 0
209 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___POR 0x00000000
210 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___M 0xFFFFFFFF
211 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020
212 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___S 0
213 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___POR 0x00000000
214 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___M 0x0000FFFF
215 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0
216 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___RWC QCSR_REG_RW
217 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___S 9
218 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
219 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___M 0x003FFFFF
220 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___POR 0x0
221 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14 (0x00030058)
222 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___RWC QCSR_REG_RO
223 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___M 0x0000007F
224 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___POR 0x0
225 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___S 19
226 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___M 0xFFFFFFFF
227 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___M 0xFFFFFFFF
228 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___POR 0x00000000
229 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___RWC QCSR_REG_RW
230 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1 (0x00032004)
231 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___M 0x003FFFFF
232 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___RWC QCSR_REG_RW
233 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___S 5
234 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___M 0x0000FFFF
235 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___M 0xFFFFFFFF
236 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___S 0
237 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___M 0x003FFFFF
238 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___RWC QCSR_REG_RW
239 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___S 0
240 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___M 0x00000008
241 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___M 0x003FFFFF
242 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___M 0x00000004
243 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___S 0
244 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
245 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___M 0x00000FFF
246 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14 (0x00032038)
247 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___M 0x00000010
248 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___M 0x00000200
249 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___S 0
250 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___M 0x003FFFFF
251 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___POR 0x0
252 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___M 0x003FFFFF
253 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___M 0x00000FFF
254 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___M 0xFFFFFFFF
255 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
256 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___S 0
257 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0
258 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___RWC QCSR_REG_RO
259 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___RWC QCSR_REG_RW
260 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___S 10
261 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___M 0x00000001
262 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___M 0xFFFFFFFF
263 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___RWC QCSR_REG_RO
264 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___S 1
265 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___POR 0x00000000
266 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___S 10
267 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___RWC QCSR_REG_RO
268 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___M 0xFFFFFFFF
269 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___POR 0x00000000
270 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___M 0x00000010
271 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___M 0x003FFFFF
272 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___S 0
273 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
274 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___S 4
275 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___M 0x0000001F
276 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23 (0x0003205C)
277 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE (0x00240034)
278 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___POR 0x000000
279 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___M 0x003FFFFF
280 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___M 0x003FFFFF
281 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___S 0
282 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___RWC QCSR_REG_RO
283 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___POR 0x00000000
284 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY (0x0024D000)
285 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
286 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___POR 0x00000000
287 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15 (0x0003005C)
288 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___S 0
289 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___POR 0x0
290 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___POR 0x00000000
291 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___S 0
292 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___M 0xFFFFFFFF
293 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___S 0
294 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___S 0
295 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE (0x0024002C)
296 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
297 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___S 4
298 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___M 0x00000200
299 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___S 0
300 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0
301 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___S 0
302 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___S 7
303 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___S 0
304 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___M 0x0000001F
305 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___POR 0x0
306 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___POR 0x0
307 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___M 0x0000FFFF
308 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___M 0x00000010
309 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___POR 0x0
310 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___M 0x01FFFFFF
311 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___S 0
312 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___POR 0x000
313 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___POR 0x0
314 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___POR 0x0000
315 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___S 24
316 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___S 0
317 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___POR 0x00000000
318 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___S 0
319 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___POR 0x0
320 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___RWC QCSR_REG_RO
321 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
322 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___S 0
323 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___M 0xFFFFFFFF
324 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___S 0
325 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0 (0x00032000)
326 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___M 0x003FFFFF
327 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___M 0xFFFF0000
328 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___S 0
329 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___S 0
330 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR (0x00030014)
331 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___M 0x003FFFFF
332 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___POR 0x00000000
333 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___M 0x00000080
334 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___M 0xFFFFFFFF
335 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20 (0x00032050)
336 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___S 3
337 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___M 0x0000FFFF
338 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___S 2
339 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
340 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___M 0x00008000
341 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___RWC QCSR_REG_RO
342 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___S 0
343 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___POR 0x0000
344 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___M 0x00000200
345 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___POR 0x00000000
346 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___RWC QCSR_REG_RW
347 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___POR 0x00000000
348 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___RWC QCSR_REG_RW
349 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___M 0x00020000
350 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW (0x0024B000)
351 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET (0x002F1004)
352 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2 (0x00032008)
353 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___M 0xFFFFFFFF
354 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___S 5
355 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___POR 0x0
356 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___POR 0x00000000
357 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___M 0xFFFF0000
358 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___POR 0x00000000
359 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___S 0
360 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___POR 0x00
361 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___POR 0x00000000
362 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___M 0x00000002
363 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___POR 0x00000000
364 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___POR 0x00000000
365 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___M 0x00000001
366 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___S 2
367 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___M 0x00000060
368 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
369 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___S 6
370 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___S 0
371 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___M 0x0FFC0000
372 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___M 0xFFFFFFFF
373 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___M 0xFFFFFFFF
374 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___POR 0x0000
375 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___POR 0x00000000
376 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___POR 0x000000
377 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___POR 0x0
378 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___M 0x003FFFFF
379 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___S 6
380 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___S 8
381 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___M 0xFFFFFFFF
382 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW (0x00245000)
383 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___S 0
384 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___POR 0x0
385 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22 (0x00030078)
386 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___M 0x00000040
387 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___POR 0x00000005
388 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___POR 0x000000
389 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___RWC QCSR_REG_RO
390 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___POR 0x00000000
391 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___S 3
392 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___S 0
393 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___POR 0x000
394 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___RWC QCSR_REG_RO
395 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___S 1
396 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___POR 0x0
397 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___S 0
398 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___POR 0x00000000
399 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___POR 0x00000000
400 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___RWC QCSR_REG_RW
401 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___RWC QCSR_REG_RW
402 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___RWC QCSR_REG_RO
403 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
404 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___M 0x003FFFFF
405 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___S 0
406 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___POR 0x00000000
407 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___S 0
408 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___M 0xFFFFFFFF
409 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___POR 0x1
410 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK (0x0024004C)
411 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___M 0x00000004
412 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___RWC QCSR_REG_RW
413 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100
414 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___S 11
415 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___S 0
416 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___POR 0x0
417 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17 (0x00030064)
418 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___RWC QCSR_REG_RW
419 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___S 0
420 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___POR 0x00000000
421 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW (0x0024000C)
422 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___POR 0x0
423 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___M 0x00FFFFFF
424 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___POR 0x0
425 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW (0x0024A000)
426 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___POR 0x0
427 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___M 0x003FFFFF
428 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___POR 0x0
429 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___RWC QCSR_REG_RW
430 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___M 0xFFFFFFFF
431 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___S 4
432 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___M 0xFFFFFFFF
433 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___RWC QCSR_REG_RW
434 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
435 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
436 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___POR 0x00000000
437 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___M 0x00000003
438 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___M 0x003FFFFF
439 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___M 0xFFFFFFFF
440 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___M 0xFFFFFFFF
441 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___POR 0x00000000
442 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___M 0x00000040
443 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100
444 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___M 0xFFFFFFFF
445 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___POR 0x00000000
446 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
447 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___RWC QCSR_REG_RW
448 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS (0x00030008)
449 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___POR 0x00000000
450 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___S 3
451 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___POR 0x000000
452 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___M 0x00010000
453 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___M 0x003FFFFF
454 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___M 0x000FF800
455 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___S 8
456 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___M 0x00000010
457 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___S 0
458 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___POR 0x00000000
459 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19 (0x0003204C)
460 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___S 3
461 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___S 10
462 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___S 10
463 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5 (0x00030034)
464 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___M 0x00000020
465 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___M 0x00000FFF
466 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___S 0
467 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___RWC QCSR_REG_RW
468 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___M 0x00FFF000
469 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
470 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___M 0xFFFFFFFF
471 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___S 4
472 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___S 16
473 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___POR 0x00000000
474 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0
475 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___M 0x000FFFFF
476 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___M 0x000FF800
477 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___S 0
478 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___S 0
479 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
480 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___RWC QCSR_REG_RW
481 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___RWC QCSR_REG_RW
482 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___POR 0x0
483 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___POR 0x00000000
484 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___RWC QCSR_REG_RW
485 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___M 0x0000FFFF
486 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___S 0
487 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___M 0x00010000
488 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___POR 0x0000
489 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___RWC QCSR_REG_RO
490 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___S 0
491 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___POR 0x00000000
492 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___POR 0x00000000
493 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___S 8
494 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___M 0xFFFFFFFF
495 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___M 0x00000080
496 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___RWC QCSR_REG_RO
497 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___M 0x003FFFFF
498 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___POR 0x0000
499 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___M 0x003FFFFF
500 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___RWC QCSR_REG_RW
501 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5 (0x00032014)
502 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___S 0
503 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___POR 0x00000000
504 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___S 10
505 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___RWC QCSR_REG_RW
506 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS (0x0003000C)
507 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___POR 0x0
508 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___M 0x00000200
509 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___RWC QCSR_REG_RW
510 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___S 0
511 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___POR 0x00000000
512 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___S 0
513 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___M 0x0000001F
514 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___POR 0x00000000
515 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___S 0
516 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___POR 0x0
517 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___S 16
518 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
519 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9 (0x00032024)
520 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___M 0x00000001
521 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___S 0
522 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___POR 0x0
523 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___M 0x0000001F
524 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___RWC QCSR_REG_RO
525 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___M 0x00000001
526 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___S 0
527 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___S 11
528 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___M 0x003FFFFF
529 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___S 0
530 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___S 0
531 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___POR 0x000
532 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___S 6
533 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___M 0xFFFFFFFF
534 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
535 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___M 0x00004000
536 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___M 0x00000004
537 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___M 0xFFFFFFFF
538 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___M 0xFFFFFFFF
539 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___S 0
540 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___S 0
541 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___M 0x00020000
542 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___M 0xFFFFFFFF
543 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___RWC QCSR_REG_RW
544 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___S 0
545 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5
546 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___M 0x0000FFFF
547 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
548 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___M 0x00000008
549 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___POR 0x0
550 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___POR 0x000000
551 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___M 0x00000008
552 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___RWC QCSR_REG_RW
553 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___POR 0x00000080
554 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___M 0xFFFFFFFF
555 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___M 0x003FFFFF
556 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___POR 0x00000000
557 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___POR 0x0
558 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___S 9
559 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18 (0x00032048)
560 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___M 0x00001000
561 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___RWC QCSR_REG_RO
562 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___POR 0x000000
563 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK (0x00240050)
564 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___S 9
565 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___M 0xFFFFFFFF
566 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___POR 0x0
567 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___S 0
568 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___POR 0x0
569 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___RWC QCSR_REG_RO
570 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___POR 0x0
571 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___POR 0x0
572 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___M 0x003FFFFF
573 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___M 0x003FFFFF
574 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW (0x00243000)
575 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___S 16
576 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___M 0x003FFFFF
577 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___S 0
578 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___S 0
579 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___S 0
580 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___POR 0x00000000
581 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY (0x00030080)
582 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___M 0x00000400
583 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___POR 0x00000000
584 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW (0x00248000)
585 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___RWC QCSR_REG_RO
586 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___M 0x003FFFFF
587 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___M 0xFFFFFFFF
588 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___POR 0x000000
589 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___RWC QCSR_REG_RW
590 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___S 2
591 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___RWC QCSR_REG_RO
592 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16 (0x00032040)
593 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___POR 0x0
594 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___POR 0x000000
595 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___M 0x0000000F
596 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___POR 0x0
597 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
598 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
599 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___S 0
600 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___S 16
601 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___M 0x003FFFFF
602 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY (0x0024C000)
603 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___POR 0x00000000
604 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___M 0xFFFFFFFF
605 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___S 0
606 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___POR 0x0
607 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___POR 0x0
608 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___M 0x00000800
609 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___S 18
610 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___M 0xFFFFFFFF
611 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS (0x00032078)
612 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___POR 0x00000000
613 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___S 0
614 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___POR 0x00000000
615 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___S 0
616 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___M 0xFFFFFFFF
617 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___S 0
618 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___POR 0x00000000
619 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___S 0
620 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___RWC QCSR_REG_RO
621 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___S 0
622 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___S 0
623 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___S 2
624 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___S 0
625 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___M 0x00000008
626 #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___POR 0x00000000
627 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___POR 0x00000000
628 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___M 0xFFFFFFFF
629 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___M 0xFFFFFFFF
630 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___S 0
631 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___POR 0x00000000
632 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12 (0x00030050)
633 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___POR 0x0
634 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___M 0x00000007
635 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___M 0x003FFFFF
636 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___S 0
637 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___M 0x00000020
638 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___M 0xFFFFFFFF
639 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___POR 0x00000000
640 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___S 0
641 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___M 0x00000004
642 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___S 14
643 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___M 0x00000004
644 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___M 0xFFFFFFFF
645 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___M 0x00040000
646 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___POR 0x00000000
647 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___POR 0x000000
648 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___S 8
649 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___S 0
650 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___M 0x00000100
651 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___S 0
652 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___POR 0x0
653 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7 (0x0003003C)
654 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___S 0
655 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___S 0
656 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___S 0
657 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___POR 0x00000000
658 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___S 0
659 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___POR 0x0
660 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET (0x002F0084)
661 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___S 0
662 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___M 0x0000FFFF
663 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___POR 0x0
664 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___POR 0x0000
665 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___S 2
666 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___POR 0x000
667 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
668 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
669 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___S 0
670 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___POR 0x00000000
671 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8 (0x00030040)
672 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___RWC QCSR_REG_RO
673 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS (0x00240030)
674 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___M 0x00000010
675 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___POR 0x0
676 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___RWC QCSR_REG_RO
677 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___S 0
678 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___POR 0x000000
679 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___S 0
680 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15 (0x0003203C)
681 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___POR 0x00000000
682 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___M 0x00000002
683 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___S 0
684 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH (0x00240004)
685 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___POR 0x0
686 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___RWC QCSR_REG_RW
687 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___S 0
688 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___S 17
689 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___POR 0x00000000
690 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___POR 0x00000000
691 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___S 0
692 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___RWC QCSR_REG_RW
693 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___S 6
694 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___RWC QCSR_REG_RO
695 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200
696 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___S 4
697 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___POR 0x00000000
698 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___POR 0x0080
699 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___POR 0x0000
700 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___POR 0x00000000
701 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___S 0
702 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200
703 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___POR 0x0
704 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___S 3
705 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___S 0
706 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___POR 0x00000000
707 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___S 0
708 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
709 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___S 3
710 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
711 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___RWC QCSR_REG_RW
712 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0
713 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW (0x00240000)
714 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___POR 0x000000
715 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___POR 0x000000
716 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___M 0xFFFFFFFF
717 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13 (0x00030054)
718 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___S 15
719 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH (0x00240010)
720 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___POR 0x00000000
721 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___S 0
722 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___POR 0x00000000
723 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___S 11
724 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___S 2
725 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___RWC QCSR_REG_RW
726 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4 (0x00032010)
727 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___S 0
728 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___POR 0x00000000
729 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___S 0
730 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___M 0x00000001
731 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___POR 0x00000000
732 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___S 0
733 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___RWC QCSR_REG_RO
734 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0
735 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___S 0
736 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___S 10
737 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___RWC QCSR_REG_RW
738 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___RWC QCSR_REG_RO
739 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___POR 0x0
740 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___POR 0x0
741 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
742 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___POR 0x000000
743 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___S 7
744 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___POR 0x0
745 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___S 0
746 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___S 7
747 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___M 0x003FFFFF
748 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___RWC QCSR_REG_RW
749 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___POR 0x00000000
750 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___POR 0x000000
751 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW (0x00246000)
752 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___S 0
753 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___POR 0x0
754 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___POR 0x0
755 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___S 0
756 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___S 0
757 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0
758 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___POR 0x000
759 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___S 12
760 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___POR 0x000
761 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___M 0xFFFFFFFF
762 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___M 0x00000004
763 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___S 0
764 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
765 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
766 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___S 0
767 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23 (0x0003007C)
768 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___M 0x0000001F
769 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___S 0
770 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___S 0
771 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___M 0x00000040
772 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___POR 0x00000000
773 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___POR 0x000000
774 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___M 0x003FFFFF
775 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___POR 0x0
776 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___S 9
777 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___S 16
778 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___POR 0x00000000
779 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___S 12
780 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
781 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___RWC QCSR_REG_RO
782 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___POR 0x00
783 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___M 0x00000100
784 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0
785 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___RWC QCSR_REG_RW
786 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___POR 0x00000000
787 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___POR 0x0
788 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___S 0
789 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___POR 0x0
790 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___S 0
791 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___S 9
792 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___POR 0x00000000
793 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___POR 0x0
794 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___M 0x0000FFFF
795 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___S 0
796 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___POR 0x00000000
797 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___RWC QCSR_REG_RW
798 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___POR 0x0
799 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___S 0
800 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___POR 0x1
801 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1 (0x00240018)
802 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___S 0
803 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___RWC QCSR_REG_RW
804 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19 (0x0003006C)
805 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX (0x0024003C)
806 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___M 0xFFFFFFFF
807 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___M 0x003FFFFF
808 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___M 0x0000000F
809 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___M 0x003FFFFF
810 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5
811 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___POR 0x00000000
812 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
813 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___POR 0x0000
814 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___POR 0x0
815 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___M 0x0000000F
816 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___M 0xFFFFFFFF
817 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___M 0x00000008
818 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___POR 0x00000000
819 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___S 0
820 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___S 0
821 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___M 0x0FFFDDFF
822 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7 (0x0003201C)
823 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___M 0x00000004
824 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___S 3
825 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___M 0x0000000C
826 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___POR 0x0
827 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
828 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___POR 0x000000
829 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___M 0x00000200
830 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___POR 0x00000000
831 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___S 0
832 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___S 0
833 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___S 0
834 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___POR 0x0000
835 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___S 0
836 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___M 0x003FFFFF
837 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
838 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___S 1
839 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___POR 0x00000000
840 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___M 0x00000001
841 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___POR 0x0
842 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___POR 0x0
843 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___M 0xFFFFFFFF
844 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___S 0
845 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___S 1
846 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___POR 0x00000000
847 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___RWC QCSR_REG_RW
848 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___M 0x00000200
849 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___S 0
850 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___S 9
851 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5
852 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___RWC QCSR_REG_RW
853 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___S 0
854 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___M 0xFFFFFFFF
855 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020
856 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___S 0
857 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___S 7
858 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___POR 0x0
859 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___S 3
860 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
861 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___M 0x0000FFFF
862 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___POR 0x0
863 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___RWC QCSR_REG_WO
864 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0
865 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___M 0x00000FFF
866 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___S 16
867 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___POR 0x00000000
868 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___M 0x00000002
869 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16 (0x00030060)
870 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___RWC QCSR_REG_RW
871 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___RWC QCSR_REG_RW
872 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
873 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS (0x00030144)
874 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___POR 0x00000000
875 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___M 0xFFFFFFFF
876 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___POR 0x0000
877 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___M 0x003FFFFF
878 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___M 0x00000008
879 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___RWC QCSR_REG_RO
880 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___S 0
881 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17 (0x00032044)
882 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___RWC QCSR_REG_RW
883 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___M 0x000003FF
884 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___POR 0x00000000
885 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___M 0x00020000
886 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___POR 0x00000000
887 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___POR 0x0
888 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___M 0x00000002
889 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___POR 0x00000000
890 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___M 0xFFFF0000
891 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___S 0
892 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___POR 0x0
893 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___S 1
894 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___M 0x00000200
895 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___S 8
896 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___M 0x00000001
897 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___POR 0x0000
898 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___POR 0x00000000
899 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
900 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___M 0x000FFFFF
901 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___POR 0x00000000
902 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___S 0
903 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___POR 0x0
904 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___S 4
905 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___M 0x000FFFFF
906 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
907 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___S 0
908 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___M 0x003FFFFF
909 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___POR 0x0
910 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___S 0
911 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___RWC QCSR_REG_RO
912 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
913 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___M 0x00000008
914 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___RWC QCSR_REG_RO
915 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___S 0
916 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___M 0x00000007
917 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___POR 0x00000000
918 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___S 6
919 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___POR 0x0
920 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___POR 0x000000
921 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___S 1
922 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW (0x00242000)
923 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___S 0
924 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___M 0x003FFFFF
925 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___S 7
926 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___S 0
927 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___S 4
928 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___M 0x003FFFFF
929 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___S 0
930 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE (0x00030010)
931 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___M 0x00000002
932 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___POR 0x00000000
933 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___M 0xFFFFFFFF
934 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8 (0x00032020)
935 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___RWC QCSR_REG_RW
936 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___S 0
937 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___POR 0x00000000
938 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___M 0x00000FFF
939 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___POR 0x00000000
940 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___RWC QCSR_REG_RW
941 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___POR 0x0
942 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___RWC QCSR_REG_RW
943 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___M 0x003FFFFF
944 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M 0x00080000
945 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___S 0
946 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___S 9
947 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___POR 0x00000000
948 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___POR 0x0
949 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___POR 0x00000000
950 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___S 0
951 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___POR 0x000000
952 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___S 6
953 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0 (0x00030020)
954 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___S 5
955 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___RWC QCSR_REG_RW
956 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___RWC QCSR_REG_RW
957 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___M 0x00FFF000
958 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___POR 0x00000000
959 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___RWC QCSR_REG_RW
960 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___POR 0x0000
961 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___S 0
962 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___POR 0x00000000
963 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___M 0x01000000
964 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___M 0xFFFFFFFF
965 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___RWC QCSR_REG_RW
966 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___POR 0x0
967 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___POR 0x0
968 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___POR 0x00000000
969 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___S 0
970 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11 (0x0003004C)
971 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___POR 0x0
972 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
973 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___S 0
974 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___M 0x00000400
975 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___S 9
976 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___POR 0x0000
977 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___RWC QCSR_REG_RW
978 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB (0x0003206C)
979 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100
980 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___POR 0x00000000
981 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___POR 0x00000000
982 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___POR 0x000000
983 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___S 0
984 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___POR 0x0
985 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___M 0x0000FFFF
986 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___M 0xFFFFFFFF
987 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___M 0x00000001
988 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___M 0x0000FFFF
989 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE (0x00240014)
990 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___M 0x00000007
991 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___S 10
992 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11 (0x0003202C)
993 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___POR 0x00000000
994 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI (0x00240048)
995 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___S 0
996 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___S 3
997 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___POR 0x0
998 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW (0x00249000)
999 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___S 4
1000 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___S 8
1001 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___M 0xFFFFFFFF
1002 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
1003 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___M 0x00000004
1004 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___M 0xFFFFFFFF
1005 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___S 2
1006 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___M 0x00000001
1007 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___RWC QCSR_REG_RO
1008 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___M 0xFFFFFFFF
1009 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___S 1
1010 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___S 0
1011 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___M 0xFFFFFFFF
1012 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___POR 0x0
1013 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___S 16
1014 #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___RWC QCSR_REG_RW
1015 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___S 0
1016 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___S 0
1017 #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___M 0x00010000
1018 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___M 0x00000008
1019 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___S 0
1020 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___POR 0x000
1021 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL (0x00030000)
1022 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___POR 0x000000
1023 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI (0x00240044)
1024 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___M 0x003FFFFF
1025 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___M 0xFFFFFFFF
1026 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___POR 0x00000000
1027 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___POR 0x00000000
1028 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___S 9
1029 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___POR 0x0
1030 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___M 0xFFFFFFFF
1031 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___S 0
1032 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___M 0x00FFFFFF
1033 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___S 0
1034 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___M 0x000003FF
1035 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD (0x00240020)
1036 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___S 0
1037 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___S 0
1038 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___POR 0x000000
1039 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___S 0
1040 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___M 0x00000004
1041 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___S 9
1042 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___POR 0x0
1043 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___S 12
1044 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___POR 0x00000000
1045 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___POR 0x00000000
1046 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___POR 0x0
1047 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___S 9
1048 #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___POR 0x00000000
1049 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___POR 0x00000000
1050 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
1051 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES (0x002F1000)
1052 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
1053 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___RWC QCSR_REG_RO
1054 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___POR 0x00000000
1055 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___POR 0x00000000
1056 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___POR 0x000000
1057 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9 (0x00030044)
1058 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
1059 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___RWC QCSR_REG_RW
1060 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6 (0x00032018)
1061 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21 (0x00032054)
1062 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___M 0x0000001F
1063 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___S 12
1064 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___S 0
1065 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW (0x00247000)
1066 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18 (0x00030068)
1067 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___S 0
1068 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___M 0xFFFFFFFF
1069 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___S 9
1070 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___M 0x00000040
1071 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___M 0x00000010
1072 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___POR 0x0
1073 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___S 0
1074 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___M 0xFFFFFFFF
1075 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___S 0
1076 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___M 0x00000008
1077 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___RWC QCSR_REG_RO
1078 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___S 2
1079 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___M 0xFFFFFFFF
1080 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE (0x00240008)
1081 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___M 0xFFFFFFFF
1082 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___RWC QCSR_REG_RO
1083 #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___S 0
1084 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___S 0
1085 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___S 0
1086 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___S 3
1087 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___M 0xFFFFFFFF
1088 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___M 0x00000040
1089 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___POR 0x0
1090 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___M 0x00000080
1091 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
1092 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1 (0x00030024)
1093 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2 (0x0024001C)
1094 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___S 0
1095 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___S 0
1096 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___S 9
1097 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___POR 0x00000000
1098 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___POR 0x0
1099 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___M 0xFFFFFFFF
1100 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___POR 0x0
1101 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___S 0
1102 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___M 0x00000002
1103 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020
1104 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___POR 0x0
1105 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___POR 0x0
1106 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___POR 0x00000000
1107 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___M 0xFFFFFFFF
1108 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21 (0x00030074)
1109 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___S 0
1110 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___RWC QCSR_REG_RW
1111 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___M 0xFFFFFFFF
1112 #define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___POR 0x000000
1113 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
1114 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___POR 0x0
1115 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___M 0x00000200
1116 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___S 7
1117 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___POR 0x00000000
1118 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___M 0xFFFFFFFF
1119 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___S 0
1120 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___S 0
1121 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___S 0
1122 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___POR 0x00000000
1123 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___POR 0x0
1124 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___S 0
1125 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___POR 0x00000000
1126 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___RWC QCSR_REG_RW
1127 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___RWC QCSR_REG_RO
1128 #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB (0x00032074)
1129 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___RWC QCSR_REG_RO
1130 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___POR 0x0
1131 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___POR 0x0
1132 #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___M 0x00000001
1133 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___S 2
1134 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___S 2
1135 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___M 0xFFFF0000
1136 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10 (0x00030048)
1137 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___M 0x003FFFFF
1138 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___S 5
1139 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___M 0x0000FFFF
1140 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___POR 0x00000000
1141 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___M 0x003FFFFF
1142 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___M 0x00000002
1143 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___S 0
1144 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___POR 0x0
1145 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___M 0x00000001
1146 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___S 0
1147 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
1148 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___S 10
1149 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
1150 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___S 0
1151 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___S 3
1152 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___RWC QCSR_REG_RO
1153 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___POR 0x0
1154 #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___POR 0x00000000
1155 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___S 9
1156 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___POR 0x00000000
1157 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___POR 0x000000
1158 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___S 2
1159 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___S 0
1160 #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB (0x00032068)
1161 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___S 17
1162 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200
1163 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___S 0
1164 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___M 0x00000040
1165 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___S 0
1166 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___M 0x00000200
1167 #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY (0x00030004)
1168 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___RWC QCSR_REG_RW
1169 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___S 0
1170 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___POR 0x0
1171 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___M 0x00000004
1172 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___POR 0x0
1173 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___POR 0x00000000
1174 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10 (0x00032028)
1175 #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___M 0x00000008
1176 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3 (0x0003200C)
1177 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___POR 0x00000000
1178 #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___S 1
1179 #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___S 0
1180 
1181 
1182 /* End auto-generated headers from register parser */
1183 
1184 #define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW	0x0024C004
1185 #define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH	0x0024C008
1186 
1187 #define MISSING                                        0
1188 #define MISSING_FOR_ADRASTEA                           MISSING
1189 #ifdef QCN7605_PCIE_GOLBAL_RESET_SUPPORT
1190 #define ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS           0x3000
1191 #else
1192 #define ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS           0
1193 #endif
1194 #define ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS                     0x45000
1195 #define ADRASTEA_RTC_SOC_REG_BASE_ADDRESS                      0x113000
1196 #define ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS               0x85000
1197 #define ADRASTEA_SI_REG_BASE_ADDRESS                           0x84000
1198 #define ADRASTEA_SOC_CORE_REG_BASE_ADDRESS                     0x113000
1199 #define ADRASTEA_CE_WRAPPER_REG_CSR_BASE_ADDRESS               0xC000
1200 #define ADRASTEA_MAC_WIFICMN_REG_BASE_ADDRESS                  MISSING
1201 
1202 /* Base Addresses */
1203 #define ADRASTEA_RTC_SOC_BASE_ADDRESS                   0x00000000
1204 #define ADRASTEA_RTC_WMAC_BASE_ADDRESS                  0x00000000
1205 #define ADRASTEA_MAC_COEX_BASE_ADDRESS                  0x0000f000
1206 #define ADRASTEA_BT_COEX_BASE_ADDRESS                   0x00002000
1207 #define ADRASTEA_SOC_PCIE_BASE_ADDRESS                  0x00130000
1208 #define ADRASTEA_SOC_CORE_BASE_ADDRESS                  0x00000000
1209 #define ADRASTEA_WLAN_UART_BASE_ADDRESS                 0x00111000
1210 #define ADRASTEA_WLAN_SI_BASE_ADDRESS                   0x00010000
1211 #define ADRASTEA_WLAN_GPIO_BASE_ADDRESS                 0x00000000
1212 #define ADRASTEA_WLAN_ANALOG_INTF_BASE_ADDRESS          0x00000000
1213 #define ADRASTEA_WLAN_MAC_BASE_ADDRESS                  0x00000000
1214 #define ADRASTEA_EFUSE_BASE_ADDRESS                     0x00024000
1215 #define ADRASTEA_FPGA_REG_BASE_ADDRESS                  0x00039000
1216 #define ADRASTEA_WLAN_UART2_BASE_ADDRESS                0x00054c00
1217 
1218 #define ADRASTEA_CE_WRAPPER_BASE_ADDRESS \
1219 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY
1220 #define ADRASTEA_CE0_BASE_ADDRESS \
1221 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW
1222 #define ADRASTEA_CE1_BASE_ADDRESS \
1223 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW
1224 #define ADRASTEA_CE2_BASE_ADDRESS \
1225 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW
1226 #define ADRASTEA_CE3_BASE_ADDRESS \
1227 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW
1228 #define ADRASTEA_CE4_BASE_ADDRESS \
1229 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW
1230 #define ADRASTEA_CE5_BASE_ADDRESS \
1231 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW
1232 #define ADRASTEA_CE6_BASE_ADDRESS \
1233 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW
1234 #define ADRASTEA_CE7_BASE_ADDRESS \
1235 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW
1236 #define ADRASTEA_CE8_BASE_ADDRESS \
1237 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW
1238 #define ADRASTEA_CE9_BASE_ADDRESS \
1239 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW
1240 #define ADRASTEA_CE10_BASE_ADDRESS \
1241 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW
1242 #define ADRASTEA_CE11_BASE_ADDRESS \
1243 			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW
1244 
1245 #define ADRASTEA_A_SOC_PCIE_SOC_PCIE_REG                MISSING
1246 #define ADRASTEA_DBI_BASE_ADDRESS                       MISSING
1247 #define ADRASTEA_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS     MISSING
1248 #define ADRASTEA_WIFICMN_BASE_ADDRESS                   MISSING
1249 #define ADRASTEA_BOARD_DATA_SZ                          MISSING
1250 #define ADRASTEA_BOARD_EXT_DATA_SZ                      MISSING
1251 #define ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START		MISSING
1252 #define ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS           MISSING
1253 #define ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER            MISSING
1254 #define ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK          MISSING
1255 #define ADRASTEA_SCRATCH_3_ADDRESS                      MISSING
1256 #define ADRASTEA_TARG_DRAM_START                        0x00400000
1257 #define ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET                0x000000c0
1258 #define ADRASTEA_SOC_RESET_CONTROL_OFFSET \
1259 	(0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
1260 #define ADRASTEA_SOC_CLOCK_CONTROL_OFFSET \
1261 	(0x00000028 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
1262 #define ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK         0x00000001
1263 #define ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK         0x00000001
1264 #define ADRASTEA_WLAN_GPIO_PIN0_ADDRESS \
1265 	(0x50 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
1266 #define ADRASTEA_WLAN_GPIO_PIN1_ADDRESS \
1267 	(0x54 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
1268 #define ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK             0x00007800
1269 #define ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK             0x00007800
1270 #define ADRASTEA_SOC_CPU_CLOCK_OFFSET                   0x00000020
1271 #define ADRASTEA_SOC_LPO_CAL_OFFSET \
1272 	(0xe0 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
1273 #define ADRASTEA_WLAN_GPIO_PIN10_ADDRESS \
1274 	(0x78 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
1275 #define ADRASTEA_WLAN_GPIO_PIN11_ADDRESS \
1276 	(0x7c + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
1277 #define ADRASTEA_WLAN_GPIO_PIN12_ADDRESS \
1278 	(0x80 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
1279 #define ADRASTEA_WLAN_GPIO_PIN13_ADDRESS \
1280 	(0x84 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
1281 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB             0
1282 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK            0x00000003
1283 #define ADRASTEA_SOC_LPO_CAL_ENABLE_LSB                 20
1284 #define ADRASTEA_SOC_LPO_CAL_ENABLE_MASK                0x00100000
1285 
1286 #define ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB          0
1287 #define ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK         0x00000001
1288 #define ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK       0x00000002
1289 #define ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK       0x00000001
1290 #define ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB            18
1291 #define ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK           0x00040000
1292 #define ADRASTEA_SI_CONFIG_I2C_LSB                      16
1293 #define ADRASTEA_SI_CONFIG_I2C_MASK                     0x00010000
1294 #define ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB               7
1295 #define ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK              0x00000080
1296 #define ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB             4
1297 #define ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK            0x00000010
1298 #define ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB            5
1299 #define ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK           0x00000020
1300 #define ADRASTEA_SI_CONFIG_DIVIDER_LSB                  0
1301 #define ADRASTEA_SI_CONFIG_DIVIDER_MASK                 0x0000000f
1302 #define ADRASTEA_SI_CONFIG_OFFSET    (0x00000000 + ADRASTEA_SI_REG_BASE_ADDRESS)
1303 #define ADRASTEA_SI_TX_DATA0_OFFSET  (0x00000008 + ADRASTEA_SI_REG_BASE_ADDRESS)
1304 #define ADRASTEA_SI_TX_DATA1_OFFSET  (0x0000000c + ADRASTEA_SI_REG_BASE_ADDRESS)
1305 #define ADRASTEA_SI_RX_DATA0_OFFSET  (0x00000010 + ADRASTEA_SI_REG_BASE_ADDRESS)
1306 #define ADRASTEA_SI_RX_DATA1_OFFSET  (0x00000014 + ADRASTEA_SI_REG_BASE_ADDRESS)
1307 #define ADRASTEA_SI_CS_OFFSET        (0x00000004 + ADRASTEA_SI_REG_BASE_ADDRESS)
1308 #define ADRASTEA_SI_CS_DONE_ERR_MASK                    0x00000400
1309 #define ADRASTEA_SI_CS_DONE_INT_MASK                    0x00000200
1310 #define ADRASTEA_SI_CS_START_LSB                        8
1311 #define ADRASTEA_SI_CS_START_MASK                       0x00000100
1312 #define ADRASTEA_SI_CS_RX_CNT_LSB                       4
1313 #define ADRASTEA_SI_CS_RX_CNT_MASK                      0x000000f0
1314 #define ADRASTEA_SI_CS_TX_CNT_LSB                       0
1315 #define ADRASTEA_SI_CS_TX_CNT_MASK                      0x0000000f
1316 #define ADRASTEA_CE_COUNT                               12
1317 #define ADRASTEA_SR_WR_INDEX_OFFSET   (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX \
1318 						- ADRASTEA_CE0_BASE_ADDRESS)
1319 #define ADRASTEA_DST_WATERMARK_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK \
1320 						- ADRASTEA_CE0_BASE_ADDRESS)
1321 #define ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB           14
1322 #define ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK          0x00004000
1323 #define ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB            16
1324 #define ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK           0x0fff0000
1325 #define ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB           0
1326 #define ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK          0x0000ffff
1327 #define ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB    16
1328 #define ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK   0xffff0000
1329 #define ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB            15
1330 #define ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK           0x00008000
1331 #define ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB         2
1332 #define ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK        0x00000004
1333 #define ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB            13
1334 #define ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK           0x00002000
1335 #define ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK    0x08000000
1336 #define ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB    16
1337 #define ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK   0x00ff0000
1338 #define ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB        0
1339 #define ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK       0x00003fff
1340 
1341 #define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET    0x00000008
1342 #define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB       8
1343 #define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK      0x00000300
1344 #define ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB          13
1345 #define ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK         0x00002000
1346 #define ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK          0x00000400
1347 #define ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK          0x80000000
1348 #define ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK     0x00040000
1349 
1350 #define ADRASTEA_DST_WR_INDEX_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX\
1351 					- ADRASTEA_CE0_BASE_ADDRESS)
1352 
1353 #define ADRASTEA_SRC_WATERMARK_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK\
1354 					- ADRASTEA_CE0_BASE_ADDRESS)
1355 
1356 #define ADRASTEA_SRC_WATERMARK_LOW_MASK                      0xffff0000
1357 #define ADRASTEA_SRC_WATERMARK_HIGH_MASK                     0x0000ffff
1358 #define ADRASTEA_DST_WATERMARK_LOW_MASK                      0xffff0000
1359 #define ADRASTEA_DST_WATERMARK_HIGH_MASK                     0x0000ffff
1360 
1361 #define ADRASTEA_CURRENT_SRRI_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI\
1362 					- ADRASTEA_CE0_BASE_ADDRESS)
1363 
1364 #define ADRASTEA_CURRENT_DRRI_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI\
1365 					- ADRASTEA_CE0_BASE_ADDRESS)
1366 
1367 #define ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK        0x00000002
1368 #define ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
1369 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___M
1370 
1371 #define ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
1372 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___M
1373 
1374 #define ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK \
1375 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___M
1376 
1377 #define ADRASTEA_HOST_IS_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS \
1378 				- ADRASTEA_CE0_BASE_ADDRESS)
1379 
1380 #define ADRASTEA_MISC_IS_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS \
1381 				- ADRASTEA_CE0_BASE_ADDRESS)
1382 
1383 #define ADRASTEA_HOST_IS_COPY_COMPLETE_MASK \
1384 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___M
1385 
1386 #define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET \
1387 	(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY\
1388 	- ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
1389 
1390 /*
1391  * Base address where the CE source and destination ring read
1392  * indices are written to be viewed by host.
1393  */
1394 
1395 #define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW \
1396 	(A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW\
1397 	- ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
1398 
1399 #define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH \
1400 	(A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH - ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
1401 
1402 #define ADRASTEA_HOST_IE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE\
1403 				- ADRASTEA_CE0_BASE_ADDRESS)
1404 
1405 #define ADRASTEA_HOST_IE_COPY_COMPLETE_MASK \
1406 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___M
1407 
1408 #define ADRASTEA_SR_BA_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW\
1409 				- ADRASTEA_CE0_BASE_ADDRESS)
1410 
1411 #define ADRASTEA_SR_BA_HIGH_OFFSET \
1412 		(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH \
1413 		 - ADRASTEA_CE0_BASE_ADDRESS)
1414 
1415 #define ADRASTEA_SR_SIZE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE \
1416 					- ADRASTEA_CE0_BASE_ADDRESS)
1417 
1418 #define ADRASTEA_CE_CTRL1_OFFSET   (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1 \
1419 					- ADRASTEA_CE0_BASE_ADDRESS)
1420 
1421 #define ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK \
1422 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___M
1423 
1424 #define ADRASTEA_DR_BA_OFFSET       (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW\
1425 					- ADRASTEA_CE0_BASE_ADDRESS)
1426 
1427 #define ADRASTEA_DR_BA_HIGH_OFFSET  \
1428 		(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH\
1429 		 - ADRASTEA_CE0_BASE_ADDRESS)
1430 
1431 #define ADRASTEA_DR_SIZE_OFFSET     (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE\
1432 					- ADRASTEA_CE0_BASE_ADDRESS)
1433 
1434 #define ADRASTEA_CE_CMD_REGISTER_OFFSET     (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD\
1435 						- ADRASTEA_CE0_BASE_ADDRESS)
1436 
1437 #define ADRASTEA_MISC_IE_OFFSET \
1438 	(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE - ADRASTEA_CE0_BASE_ADDRESS)
1439 
1440 #define ADRASTEA_MISC_IS_AXI_ERR_MASK 0x00000100
1441 
1442 #define ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK                   0x00000200
1443 
1444 #define ADRASTEA_MISC_IS_AXI_TIMEOUT_ERR \
1445 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___M
1446 
1447 #define ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK \
1448 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___M
1449 
1450 #define ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK\
1451 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___M
1452 
1453 #define ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK \
1454 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___M
1455 
1456 #define ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK \
1457 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___M
1458 
1459 #define ADRASTEA_SRC_WATERMARK_LOW_LSB \
1460 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___S
1461 
1462 #define ADRASTEA_SRC_WATERMARK_HIGH_LSB \
1463 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___S
1464 
1465 #define ADRASTEA_DST_WATERMARK_LOW_LSB \
1466 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___S
1467 
1468 #define ADRASTEA_DST_WATERMARK_HIGH_LSB \
1469 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___S
1470 
1471 #define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
1472 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___M
1473 
1474 #define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
1475 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___S
1476 
1477 #define ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB \
1478 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___S
1479 
1480 #define ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
1481 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___M
1482 
1483 #define ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
1484 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___M
1485 
1486 #define ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
1487 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___S
1488 
1489 #define ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
1490 	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___S
1491 
1492 #define ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK  0x0000004
1493 #define ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB   2
1494 #define ADRASTEA_SOC_GLOBAL_RESET_ADDRESS \
1495 	(0x0008 + ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS)
1496 #define ADRASTEA_RTC_STATE_ADDRESS \
1497 	(0x0000 + ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS)
1498 #define ADRASTEA_RTC_STATE_COLD_RESET_MASK                   0x400
1499 
1500 #define ADRASTEA_PCIE_SOC_WAKE_RESET                         0x00000000
1501 #define ADRASTEA_PCIE_SOC_WAKE_ADDRESS                       (ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE)
1502 #define ADRASTEA_PCIE_SOC_WAKE_V_MASK                        0x00000001
1503 
1504 #define ADRASTEA_RTC_STATE_V_MASK                            0x00000007
1505 #define ADRASTEA_RTC_STATE_V_LSB                             0
1506 #define ADRASTEA_RTC_STATE_V_ON                              5
1507 #define ADRASTEA_PCIE_LOCAL_BASE_ADDRESS                     0x0
1508 #define ADRASTEA_FW_IND_EVENT_PENDING                        1
1509 #define ADRASTEA_FW_IND_INITIALIZED                          2
1510 #define ADRASTEA_FW_IND_HELPER                               4
1511 
1512 #define ADRASTEA_PCIE_INTR_FIRMWARE_MASK                     0x00000000
1513 #define ADRASTEA_PCIE_INTR_CE0_MASK                          0x00000100
1514 #define ADRASTEA_PCIE_INTR_CE_MASK_ALL                       0x00001ffe
1515 
1516 #define ADRASTEA_CPU_INTR_ADDRESS                            0xffffffff
1517 #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS               0xffffffff
1518 #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK           0xffffffff
1519 #define ADRASTEA_SOC_LF_TIMER_STATUS0_ADDRESS                0xffffffff
1520 #define ADRASTEA_SOC_RESET_CONTROL_ADDRESS \
1521 	(0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
1522 #define ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK            0x0100
1523 #define ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
1524 #define ADRASTEA_CORE_CTRL_ADDRESS        (0x0000 + ADRASTEA_SOC_CORE_REG_BASE_ADDRESS)
1525 #define ADRASTEA_CORE_CTRL_CPU_INTR_MASK                  0x00002000
1526 #define ADRASTEA_LOCAL_SCRATCH_OFFSET                     0x00000018
1527 #define ADRASTEA_CLOCK_GPIO_OFFSET                        0xffffffff
1528 #define ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
1529 #define ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
1530 #define ADRASTEA_SOC_CHIP_ID_ADDRESS                      0x000000f0
1531 #define ADRASTEA_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
1532 #define ADRASTEA_SOC_CHIP_ID_VERSION_LSB                  18
1533 #define ADRASTEA_SOC_CHIP_ID_REVISION_MASK                0x00000f00
1534 #define ADRASTEA_SOC_CHIP_ID_REVISION_LSB                 8
1535 #define ADRASTEA_SOC_POWER_REG_OFFSET                     0x0000010c
1536 
1537 /* Copy Engine Debug */
1538 #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
1539 #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
1540 #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
1541 #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
1542 #define ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
1543 #define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
1544 #define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
1545 #define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
1546 #define ADRASTEA_WLAN_DEBUG_OUT_OFFSET                    0x00000110
1547 #define ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB                  19
1548 #define ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB                  0
1549 #define ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
1550 #define ADRASTEA_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
1551 #define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
1552 #define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
1553 #define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
1554 #define ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB                   4
1555 #define ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB                   0
1556 #define ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
1557 #define ADRASTEA_CE_WRAPPER_DEBUG_OFFSET                  0x0008
1558 #define ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB                 4
1559 #define ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB                 0
1560 #define ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK                0x0000001f
1561 #define ADRASTEA_CE_DEBUG_OFFSET                          0x0054
1562 #define ADRASTEA_CE_DEBUG_SEL_MSB                         5
1563 #define ADRASTEA_CE_DEBUG_SEL_LSB                         0
1564 #define ADRASTEA_CE_DEBUG_SEL_MASK                        0x0000003f
1565 /* End */
1566 
1567 /* PLL start */
1568 #define ADRASTEA_EFUSE_OFFSET                             0x0000032c
1569 #define ADRASTEA_EFUSE_XTAL_SEL_MSB                       10
1570 #define ADRASTEA_EFUSE_XTAL_SEL_LSB                       8
1571 #define ADRASTEA_EFUSE_XTAL_SEL_MASK                      0x00000700
1572 #define ADRASTEA_BB_PLL_CONFIG_OFFSET                     0x000002f4
1573 #define ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB                 20
1574 #define ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB                 18
1575 #define ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
1576 #define ADRASTEA_BB_PLL_CONFIG_FRAC_MSB                   17
1577 #define ADRASTEA_BB_PLL_CONFIG_FRAC_LSB                   0
1578 #define ADRASTEA_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
1579 #define ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB                 10
1580 #define ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB                 0
1581 #define ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
1582 #define ADRASTEA_WLAN_PLL_SETTLE_OFFSET                   0x0018
1583 #define ADRASTEA_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
1584 #define ADRASTEA_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
1585 #define ADRASTEA_WLAN_PLL_SETTLE_RESET                    0x00000400
1586 #define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB               18
1587 #define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB               18
1588 #define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
1589 #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB              16
1590 #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB              16
1591 #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
1592 #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
1593 #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
1594 #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
1595 #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
1596 #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
1597 #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB              13
1598 #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB              10
1599 #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
1600 #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
1601 #define ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB                 9
1602 #define ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB                 0
1603 #define ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
1604 #define ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET               0x11
1605 #define ADRASTEA_WLAN_PLL_CONTROL_OFFSET                  0x0014
1606 #define ADRASTEA_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
1607 #define ADRASTEA_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
1608 #define ADRASTEA_WLAN_PLL_CONTROL_RESET                   0x00010011
1609 #define ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
1610 #define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB                2
1611 #define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB                0
1612 #define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
1613 #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
1614 #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
1615 #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
1616 #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
1617 #define ADRASTEA_RTC_SYNC_STATUS_OFFSET                   0x0244
1618 #define ADRASTEA_SOC_CPU_CLOCK_OFFSET                     0x00000020
1619 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB               1
1620 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB               0
1621 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
1622 /* PLL end */
1623 
1624 #define ADRASTEA_PCIE_INTR_CE_MASK(n) (ADRASTEA_PCIE_INTR_CE0_MASK << (n))
1625 #define ADRASTEA_DRAM_BASE_ADDRESS     ADRASTEA_TARG_DRAM_START
1626 #define ADRASTEA_FW_INDICATOR_ADDRESS \
1627 	(ADRASTEA_WIFICMN_BASE_ADDRESS + ADRASTEA_SCRATCH_3_ADDRESS)
1628 #define ADRASTEA_SYSTEM_SLEEP_OFFSET       ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET
1629 #define ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET  (0x002c + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS)
1630 #define ADRASTEA_WLAN_RESET_CONTROL_OFFSET (0x0000 + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS)
1631 #define ADRASTEA_CLOCK_CONTROL_OFFSET      ADRASTEA_SOC_CLOCK_CONTROL_OFFSET
1632 #define ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK \
1633 	ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK
1634 #define ADRASTEA_RESET_CONTROL_MBOX_RST_MASK 0x00000004
1635 #define ADRASTEA_RESET_CONTROL_SI0_RST_MASK \
1636 	ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK
1637 #define ADRASTEA_GPIO_BASE_ADDRESS         ADRASTEA_WLAN_GPIO_BASE_ADDRESS
1638 #define ADRASTEA_GPIO_PIN0_OFFSET          ADRASTEA_WLAN_GPIO_PIN0_ADDRESS
1639 #define ADRASTEA_GPIO_PIN1_OFFSET          ADRASTEA_WLAN_GPIO_PIN1_ADDRESS
1640 #define ADRASTEA_GPIO_PIN0_CONFIG_MASK     ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK
1641 #define ADRASTEA_GPIO_PIN1_CONFIG_MASK     ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK
1642 #define ADRASTEA_SI_BASE_ADDRESS           0x00000000
1643 #define ADRASTEA_CPU_CLOCK_OFFSET          (0x20 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
1644 #define ADRASTEA_LPO_CAL_OFFSET            ADRASTEA_SOC_LPO_CAL_OFFSET
1645 #define ADRASTEA_GPIO_PIN10_OFFSET         ADRASTEA_WLAN_GPIO_PIN10_ADDRESS
1646 #define ADRASTEA_GPIO_PIN11_OFFSET         ADRASTEA_WLAN_GPIO_PIN11_ADDRESS
1647 #define ADRASTEA_GPIO_PIN12_OFFSET         ADRASTEA_WLAN_GPIO_PIN12_ADDRESS
1648 #define ADRASTEA_GPIO_PIN13_OFFSET         ADRASTEA_WLAN_GPIO_PIN13_ADDRESS
1649 #define ADRASTEA_CPU_CLOCK_STANDARD_LSB    0
1650 #define ADRASTEA_CPU_CLOCK_STANDARD_MASK   0x1
1651 #define ADRASTEA_LPO_CAL_ENABLE_LSB        ADRASTEA_SOC_LPO_CAL_ENABLE_LSB
1652 #define ADRASTEA_LPO_CAL_ENABLE_MASK       ADRASTEA_SOC_LPO_CAL_ENABLE_MASK
1653 #define ADRASTEA_ANALOG_INTF_BASE_ADDRESS  ADRASTEA_WLAN_ANALOG_INTF_BASE_ADDRESS
1654 #define ADRASTEA_MBOX_BASE_ADDRESS         0x00008000
1655 #define ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB              MISSING
1656 #define ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK            MISSING
1657 #define ADRASTEA_INT_STATUS_ENABLE_CPU_LSB               MISSING
1658 #define ADRASTEA_INT_STATUS_ENABLE_CPU_MASK              MISSING
1659 #define ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB           MISSING
1660 #define ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK          MISSING
1661 #define ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
1662 #define ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
1663 #define ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
1664 #define ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
1665 #define ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
1666 #define ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
1667 #define ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
1668 #define ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
1669 #define ADRASTEA_INT_STATUS_ENABLE_ADDRESS               MISSING
1670 #define ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
1671 #define ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
1672 #define ADRASTEA_HOST_INT_STATUS_ADDRESS                 MISSING
1673 #define ADRASTEA_CPU_INT_STATUS_ADDRESS                  MISSING
1674 #define ADRASTEA_ERROR_INT_STATUS_ADDRESS                MISSING
1675 #define ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK            MISSING
1676 #define ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB             MISSING
1677 #define ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
1678 #define ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
1679 #define ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
1680 #define ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
1681 #define ADRASTEA_COUNT_DEC_ADDRESS                       MISSING
1682 #define ADRASTEA_HOST_INT_STATUS_CPU_MASK                MISSING
1683 #define ADRASTEA_HOST_INT_STATUS_CPU_LSB                 MISSING
1684 #define ADRASTEA_HOST_INT_STATUS_ERROR_MASK              MISSING
1685 #define ADRASTEA_HOST_INT_STATUS_ERROR_LSB               MISSING
1686 #define ADRASTEA_HOST_INT_STATUS_COUNTER_MASK            MISSING
1687 #define ADRASTEA_HOST_INT_STATUS_COUNTER_LSB             MISSING
1688 #define ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS              MISSING
1689 #define ADRASTEA_WINDOW_DATA_ADDRESS                     MISSING
1690 #define ADRASTEA_WINDOW_READ_ADDR_ADDRESS                MISSING
1691 #define ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS               MISSING
1692 
1693 /* Shadow Registers - Start */
1694 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0 \
1695 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0
1696 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1 \
1697 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1
1698 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2 \
1699 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2
1700 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3 \
1701 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3
1702 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4 \
1703 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4
1704 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5 \
1705 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5
1706 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6 \
1707 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6
1708 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7 \
1709 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7
1710 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8 \
1711 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8
1712 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9 \
1713 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9
1714 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10 \
1715 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10
1716 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11 \
1717 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11
1718 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12 \
1719 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12
1720 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13 \
1721 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13
1722 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14 \
1723 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14
1724 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15 \
1725 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15
1726 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16 \
1727 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16
1728 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17 \
1729 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17
1730 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18 \
1731 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18
1732 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19 \
1733 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19
1734 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20 \
1735 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20
1736 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21 \
1737 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21
1738 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22 \
1739 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22
1740 #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23 \
1741 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23
1742 
1743 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0 \
1744 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0
1745 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1 \
1746 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1
1747 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2 \
1748 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2
1749 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3 \
1750 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3
1751 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4 \
1752 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4
1753 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5 \
1754 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5
1755 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6 \
1756 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6
1757 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7 \
1758 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7
1759 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8 \
1760 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8
1761 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9 \
1762 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9
1763 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10 \
1764 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10
1765 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11 \
1766 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11
1767 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12 \
1768 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12
1769 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13 \
1770 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13
1771 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14 \
1772 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14
1773 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15 \
1774 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15
1775 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16 \
1776 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16
1777 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17 \
1778 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17
1779 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18 \
1780 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18
1781 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19 \
1782 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19
1783 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20 \
1784 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20
1785 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21 \
1786 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21
1787 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22 \
1788 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22
1789 #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23 \
1790 					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23
1791 
1792 /* Q6 iHelium emulation registers */
1793 #define ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1	0x00113018
1794 #define ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER		0x00113184
1795 #define ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1		0x00113020
1796 #define ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1	0x00113010
1797 #define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0		0x00130040
1798 #define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1		0x00130044
1799 
1800 #define ADRASTEA_HOST_ENABLE_REGISTER    0x00188000
1801 #define ADRASTEA_Q6_ENABLE_REGISTER_0    0x00188004
1802 #define ADRASTEA_Q6_ENABLE_REGISTER_1    0x00188008
1803 #define ADRASTEA_HOST_CAUSE_REGISTER     0x0018800c
1804 #define ADRASTEA_Q6_CAUSE_REGISTER_0     0x00188010
1805 #define ADRASTEA_Q6_CAUSE_REGISTER_1     0x00188014
1806 #define ADRASTEA_HOST_CLEAR_REGISTER     0x00188018
1807 #define ADRASTEA_Q6_CLEAR_REGISTER_0     0x0018801c
1808 #define ADRASTEA_Q6_CLEAR_REGISTER_1     0x00188020
1809 
1810 #define ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA	0x08
1811 #define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2			0x0013005C
1812 #define ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK        0x0
1813 /* end: Q6 iHelium emulation registers */
1814 
1815 #define ADRASTEA_BYPASS_QMI_TEMP_REGISTER    0x00032064
1816 #define GENOA_OFFSET			     0x800000
1817 
1818 struct targetdef_s adrastea_targetdef = {
1819 	.d_RTC_SOC_BASE_ADDRESS = ADRASTEA_RTC_SOC_BASE_ADDRESS,
1820 	.d_RTC_WMAC_BASE_ADDRESS = ADRASTEA_RTC_WMAC_BASE_ADDRESS,
1821 	.d_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
1822 	.d_WLAN_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
1823 	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
1824 	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
1825 	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
1826 	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
1827 	.d_CLOCK_CONTROL_OFFSET = ADRASTEA_CLOCK_CONTROL_OFFSET,
1828 	.d_CLOCK_CONTROL_SI0_CLK_MASK = ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK,
1829 	.d_RESET_CONTROL_OFFSET = ADRASTEA_SOC_RESET_CONTROL_OFFSET,
1830 	.d_RESET_CONTROL_MBOX_RST_MASK = ADRASTEA_RESET_CONTROL_MBOX_RST_MASK,
1831 	.d_RESET_CONTROL_SI0_RST_MASK = ADRASTEA_RESET_CONTROL_SI0_RST_MASK,
1832 	.d_WLAN_RESET_CONTROL_OFFSET = ADRASTEA_WLAN_RESET_CONTROL_OFFSET,
1833 	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
1834 	ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK,
1835 	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
1836 	ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK,
1837 	.d_GPIO_BASE_ADDRESS = ADRASTEA_GPIO_BASE_ADDRESS,
1838 	.d_GPIO_PIN0_OFFSET = ADRASTEA_GPIO_PIN0_OFFSET,
1839 	.d_GPIO_PIN1_OFFSET = ADRASTEA_GPIO_PIN1_OFFSET,
1840 	.d_GPIO_PIN0_CONFIG_MASK = ADRASTEA_GPIO_PIN0_CONFIG_MASK,
1841 	.d_GPIO_PIN1_CONFIG_MASK = ADRASTEA_GPIO_PIN1_CONFIG_MASK,
1842 	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB,
1843 	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK,
1844 	.d_SI_CONFIG_I2C_LSB = ADRASTEA_SI_CONFIG_I2C_LSB,
1845 	.d_SI_CONFIG_I2C_MASK = ADRASTEA_SI_CONFIG_I2C_MASK,
1846 	.d_SI_CONFIG_POS_SAMPLE_LSB = ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB,
1847 	.d_SI_CONFIG_POS_SAMPLE_MASK = ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK,
1848 	.d_SI_CONFIG_INACTIVE_CLK_LSB = ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB,
1849 	.d_SI_CONFIG_INACTIVE_CLK_MASK = ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK,
1850 	.d_SI_CONFIG_INACTIVE_DATA_LSB = ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB,
1851 	.d_SI_CONFIG_INACTIVE_DATA_MASK = ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK,
1852 	.d_SI_CONFIG_DIVIDER_LSB = ADRASTEA_SI_CONFIG_DIVIDER_LSB,
1853 	.d_SI_CONFIG_DIVIDER_MASK = ADRASTEA_SI_CONFIG_DIVIDER_MASK,
1854 	.d_SI_BASE_ADDRESS = ADRASTEA_SI_BASE_ADDRESS,
1855 	.d_SI_CONFIG_OFFSET = ADRASTEA_SI_CONFIG_OFFSET,
1856 	.d_SI_TX_DATA0_OFFSET = ADRASTEA_SI_TX_DATA0_OFFSET,
1857 	.d_SI_TX_DATA1_OFFSET = ADRASTEA_SI_TX_DATA1_OFFSET,
1858 	.d_SI_RX_DATA0_OFFSET = ADRASTEA_SI_RX_DATA0_OFFSET,
1859 	.d_SI_RX_DATA1_OFFSET = ADRASTEA_SI_RX_DATA1_OFFSET,
1860 	.d_SI_CS_OFFSET = ADRASTEA_SI_CS_OFFSET,
1861 	.d_SI_CS_DONE_ERR_MASK = ADRASTEA_SI_CS_DONE_ERR_MASK,
1862 	.d_SI_CS_DONE_INT_MASK = ADRASTEA_SI_CS_DONE_INT_MASK,
1863 	.d_SI_CS_START_LSB = ADRASTEA_SI_CS_START_LSB,
1864 	.d_SI_CS_START_MASK = ADRASTEA_SI_CS_START_MASK,
1865 	.d_SI_CS_RX_CNT_LSB = ADRASTEA_SI_CS_RX_CNT_LSB,
1866 	.d_SI_CS_RX_CNT_MASK = ADRASTEA_SI_CS_RX_CNT_MASK,
1867 	.d_SI_CS_TX_CNT_LSB = ADRASTEA_SI_CS_TX_CNT_LSB,
1868 	.d_SI_CS_TX_CNT_MASK = ADRASTEA_SI_CS_TX_CNT_MASK,
1869 	.d_BOARD_DATA_SZ = ADRASTEA_BOARD_DATA_SZ,
1870 	.d_BOARD_EXT_DATA_SZ = ADRASTEA_BOARD_EXT_DATA_SZ,
1871 	.d_MBOX_BASE_ADDRESS = ADRASTEA_MBOX_BASE_ADDRESS,
1872 	.d_LOCAL_SCRATCH_OFFSET = ADRASTEA_LOCAL_SCRATCH_OFFSET,
1873 	.d_CPU_CLOCK_OFFSET = ADRASTEA_CPU_CLOCK_OFFSET,
1874 	.d_LPO_CAL_OFFSET = ADRASTEA_LPO_CAL_OFFSET,
1875 	.d_GPIO_PIN10_OFFSET = ADRASTEA_GPIO_PIN10_OFFSET,
1876 	.d_GPIO_PIN11_OFFSET = ADRASTEA_GPIO_PIN11_OFFSET,
1877 	.d_GPIO_PIN12_OFFSET = ADRASTEA_GPIO_PIN12_OFFSET,
1878 	.d_GPIO_PIN13_OFFSET = ADRASTEA_GPIO_PIN13_OFFSET,
1879 	.d_CLOCK_GPIO_OFFSET = ADRASTEA_CLOCK_GPIO_OFFSET,
1880 	.d_CPU_CLOCK_STANDARD_LSB = ADRASTEA_CPU_CLOCK_STANDARD_LSB,
1881 	.d_CPU_CLOCK_STANDARD_MASK = ADRASTEA_CPU_CLOCK_STANDARD_MASK,
1882 	.d_LPO_CAL_ENABLE_LSB = ADRASTEA_LPO_CAL_ENABLE_LSB,
1883 	.d_LPO_CAL_ENABLE_MASK = ADRASTEA_LPO_CAL_ENABLE_MASK,
1884 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
1885 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
1886 		ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
1887 	.d_ANALOG_INTF_BASE_ADDRESS = ADRASTEA_ANALOG_INTF_BASE_ADDRESS,
1888 	.d_WLAN_MAC_BASE_ADDRESS = ADRASTEA_WLAN_MAC_BASE_ADDRESS,
1889 	.d_FW_INDICATOR_ADDRESS = ADRASTEA_FW_INDICATOR_ADDRESS,
1890 	.d_DRAM_BASE_ADDRESS = ADRASTEA_DRAM_BASE_ADDRESS,
1891 	.d_SOC_CORE_BASE_ADDRESS = ADRASTEA_SOC_CORE_BASE_ADDRESS,
1892 	.d_CORE_CTRL_ADDRESS = ADRASTEA_CORE_CTRL_ADDRESS,
1893 	.d_CE_COUNT = ADRASTEA_CE_COUNT,
1894 	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
1895 	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
1896 	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
1897 	.d_PCIE_INTR_ENABLE_ADDRESS = ADRASTEA_HOST_ENABLE_REGISTER,
1898 	.d_PCIE_INTR_CLR_ADDRESS = ADRASTEA_HOST_CLEAR_REGISTER,
1899 	.d_PCIE_INTR_FIRMWARE_MASK = ADRASTEA_PCIE_INTR_FIRMWARE_MASK,
1900 	.d_PCIE_INTR_CE_MASK_ALL = ADRASTEA_PCIE_INTR_CE_MASK_ALL,
1901 	.d_CORE_CTRL_CPU_INTR_MASK = ADRASTEA_CORE_CTRL_CPU_INTR_MASK,
1902 	.d_SR_WR_INDEX_ADDRESS = ADRASTEA_SR_WR_INDEX_OFFSET,
1903 	.d_DST_WATERMARK_ADDRESS = ADRASTEA_DST_WATERMARK_OFFSET,
1904 	/* htt_rx.c */
1905 	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
1906 	ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK,
1907 	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB,
1908 	.d_RX_MPDU_START_0_SEQ_NUM_MASK = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK,
1909 	.d_RX_MPDU_START_0_SEQ_NUM_LSB = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB,
1910 	.d_RX_MPDU_START_2_PN_47_32_LSB = ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB,
1911 	.d_RX_MPDU_START_2_PN_47_32_MASK =
1912 		ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK,
1913 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
1914 		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
1915 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
1916 		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
1917 	.d_RX_MSDU_END_4_LAST_MSDU_MASK = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK,
1918 	.d_RX_MSDU_END_4_LAST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB,
1919 	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
1920 		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK,
1921 	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
1922 		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB,
1923 	.d_RX_ATTENTION_0_FRAGMENT_MASK = ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK,
1924 	.d_RX_ATTENTION_0_FRAGMENT_LSB = ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB,
1925 	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
1926 		ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
1927 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
1928 		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
1929 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
1930 		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
1931 	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
1932 		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK,
1933 	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
1934 		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB,
1935 	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
1936 		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
1937 	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
1938 		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK,
1939 	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
1940 		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB,
1941 	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
1942 		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK,
1943 	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
1944 		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB,
1945 	.d_RX_ATTENTION_0_MORE_DATA_MASK =
1946 		ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK,
1947 	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
1948 		ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK,
1949 	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
1950 		ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
1951 
1952 	/* PLL start */
1953 	.d_EFUSE_OFFSET = ADRASTEA_EFUSE_OFFSET,
1954 	.d_EFUSE_XTAL_SEL_MSB = ADRASTEA_EFUSE_XTAL_SEL_MSB,
1955 	.d_EFUSE_XTAL_SEL_LSB = ADRASTEA_EFUSE_XTAL_SEL_LSB,
1956 	.d_EFUSE_XTAL_SEL_MASK = ADRASTEA_EFUSE_XTAL_SEL_MASK,
1957 	.d_BB_PLL_CONFIG_OFFSET = ADRASTEA_BB_PLL_CONFIG_OFFSET,
1958 	.d_BB_PLL_CONFIG_OUTDIV_MSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB,
1959 	.d_BB_PLL_CONFIG_OUTDIV_LSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB,
1960 	.d_BB_PLL_CONFIG_OUTDIV_MASK = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK,
1961 	.d_BB_PLL_CONFIG_FRAC_MSB = ADRASTEA_BB_PLL_CONFIG_FRAC_MSB,
1962 	.d_BB_PLL_CONFIG_FRAC_LSB = ADRASTEA_BB_PLL_CONFIG_FRAC_LSB,
1963 	.d_BB_PLL_CONFIG_FRAC_MASK = ADRASTEA_BB_PLL_CONFIG_FRAC_MASK,
1964 	.d_WLAN_PLL_SETTLE_TIME_MSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB,
1965 	.d_WLAN_PLL_SETTLE_TIME_LSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB,
1966 	.d_WLAN_PLL_SETTLE_TIME_MASK = ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK,
1967 	.d_WLAN_PLL_SETTLE_OFFSET = ADRASTEA_WLAN_PLL_SETTLE_OFFSET,
1968 	.d_WLAN_PLL_SETTLE_SW_MASK = ADRASTEA_WLAN_PLL_SETTLE_SW_MASK,
1969 	.d_WLAN_PLL_SETTLE_RSTMASK = ADRASTEA_WLAN_PLL_SETTLE_RSTMASK,
1970 	.d_WLAN_PLL_SETTLE_RESET = ADRASTEA_WLAN_PLL_SETTLE_RESET,
1971 	.d_WLAN_PLL_CONTROL_NOPWD_MSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB,
1972 	.d_WLAN_PLL_CONTROL_NOPWD_LSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB,
1973 	.d_WLAN_PLL_CONTROL_NOPWD_MASK = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK,
1974 	.d_WLAN_PLL_CONTROL_BYPASS_MSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB,
1975 	.d_WLAN_PLL_CONTROL_BYPASS_LSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB,
1976 	.d_WLAN_PLL_CONTROL_BYPASS_MASK = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK,
1977 	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
1978 		ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET,
1979 	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB,
1980 	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB,
1981 	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
1982 		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK,
1983 	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
1984 		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET,
1985 	.d_WLAN_PLL_CONTROL_REFDIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB,
1986 	.d_WLAN_PLL_CONTROL_REFDIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB,
1987 	.d_WLAN_PLL_CONTROL_REFDIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK,
1988 	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
1989 		ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET,
1990 	.d_WLAN_PLL_CONTROL_DIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB,
1991 	.d_WLAN_PLL_CONTROL_DIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB,
1992 	.d_WLAN_PLL_CONTROL_DIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK,
1993 	.d_WLAN_PLL_CONTROL_DIV_RESET = ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET,
1994 	.d_WLAN_PLL_CONTROL_OFFSET = ADRASTEA_WLAN_PLL_CONTROL_OFFSET,
1995 	.d_WLAN_PLL_CONTROL_SW_MASK = ADRASTEA_WLAN_PLL_CONTROL_SW_MASK,
1996 	.d_WLAN_PLL_CONTROL_RSTMASK = ADRASTEA_WLAN_PLL_CONTROL_RSTMASK,
1997 	.d_WLAN_PLL_CONTROL_RESET = ADRASTEA_WLAN_PLL_CONTROL_RESET,
1998 	.d_SOC_CORE_CLK_CTRL_OFFSET = ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET,
1999 	.d_SOC_CORE_CLK_CTRL_DIV_MSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB,
2000 	.d_SOC_CORE_CLK_CTRL_DIV_LSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB,
2001 	.d_SOC_CORE_CLK_CTRL_DIV_MASK = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK,
2002 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
2003 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
2004 	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
2005 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
2006 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
2007 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
2008 	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
2009 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
2010 	.d_RTC_SYNC_STATUS_OFFSET = ADRASTEA_RTC_SYNC_STATUS_OFFSET,
2011 	.d_SOC_CPU_CLOCK_OFFSET = ADRASTEA_SOC_CPU_CLOCK_OFFSET,
2012 	.d_SOC_CPU_CLOCK_STANDARD_MSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB,
2013 	.d_SOC_CPU_CLOCK_STANDARD_LSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB,
2014 	.d_SOC_CPU_CLOCK_STANDARD_MASK = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK,
2015 	/* PLL end */
2016 	.d_SOC_POWER_REG_OFFSET = ADRASTEA_SOC_POWER_REG_OFFSET,
2017 	.d_PCIE_INTR_CAUSE_ADDRESS = ADRASTEA_HOST_CAUSE_REGISTER,
2018 	.d_SOC_RESET_CONTROL_ADDRESS = ADRASTEA_SOC_RESET_CONTROL_ADDRESS,
2019 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
2020 		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
2021 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
2022 		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
2023 	.d_SOC_RESET_CONTROL_CE_RST_MASK =
2024 		ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK,
2025 	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
2026 		ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
2027 	.d_CPU_INTR_ADDRESS = ADRASTEA_CPU_INTR_ADDRESS,
2028 	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
2029 		ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS,
2030 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
2031 		ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
2032 	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
2033 		ADRASTEA_SOC_LF_TIMER_STATUS0_ADDRESS,
2034 	/* chip id start */
2035 	.d_SOC_CHIP_ID_ADDRESS = ADRASTEA_SOC_CHIP_ID_ADDRESS,
2036 	.d_SOC_CHIP_ID_VERSION_MASK = ADRASTEA_SOC_CHIP_ID_VERSION_MASK,
2037 	.d_SOC_CHIP_ID_VERSION_LSB = ADRASTEA_SOC_CHIP_ID_VERSION_LSB,
2038 	.d_SOC_CHIP_ID_REVISION_MASK = ADRASTEA_SOC_CHIP_ID_REVISION_MASK,
2039 	.d_SOC_CHIP_ID_REVISION_LSB = ADRASTEA_SOC_CHIP_ID_REVISION_LSB,
2040 	/* chip id end */
2041 	.d_A_SOC_CORE_SCRATCH_0_ADDRESS = ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS,
2042 	.d_A_SOC_CORE_SPARE_0_REGISTER = ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER,
2043 	.d_PCIE_INTR_FIRMWARE_ROUTE_MASK =
2044 		ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK,
2045 	.d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 =
2046 		ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1,
2047 	.d_A_SOC_CORE_SPARE_1_REGISTER =
2048 		ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER,
2049 	.d_A_SOC_CORE_PCIE_INTR_CLR_GRP1 =
2050 		ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1,
2051 	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 =
2052 		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1,
2053 	.d_A_SOC_PCIE_PCIE_SCRATCH_0 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0,
2054 	.d_A_SOC_PCIE_PCIE_SCRATCH_1 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1,
2055 	.d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA =
2056 		ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA,
2057 	.d_A_SOC_PCIE_PCIE_SCRATCH_2 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2,
2058 	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK =
2059 		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK,
2060 	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET,
2061 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
2062 	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
2063 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
2064 		ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
2065 	.d_WLAN_DEBUG_CONTROL_OFFSET = ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET,
2066 	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
2067 		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB,
2068 	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
2069 		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB,
2070 	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
2071 		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK,
2072 	.d_WLAN_DEBUG_OUT_OFFSET = ADRASTEA_WLAN_DEBUG_OUT_OFFSET,
2073 	.d_WLAN_DEBUG_OUT_DATA_MSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB,
2074 	.d_WLAN_DEBUG_OUT_DATA_LSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB,
2075 	.d_WLAN_DEBUG_OUT_DATA_MASK = ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK,
2076 	.d_AMBA_DEBUG_BUS_OFFSET = ADRASTEA_AMBA_DEBUG_BUS_OFFSET,
2077 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
2078 		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
2079 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
2080 		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
2081 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
2082 		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
2083 	.d_AMBA_DEBUG_BUS_SEL_MSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB,
2084 	.d_AMBA_DEBUG_BUS_SEL_LSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB,
2085 	.d_AMBA_DEBUG_BUS_SEL_MASK = ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK,
2086 
2087 #ifdef QCA_WIFI_3_0_ADRASTEA
2088 	.d_Q6_ENABLE_REGISTER_0 = ADRASTEA_Q6_ENABLE_REGISTER_0,
2089 	.d_Q6_ENABLE_REGISTER_1 = ADRASTEA_Q6_ENABLE_REGISTER_1,
2090 	.d_Q6_CAUSE_REGISTER_0 = ADRASTEA_Q6_CAUSE_REGISTER_0,
2091 	.d_Q6_CAUSE_REGISTER_1 = ADRASTEA_Q6_CAUSE_REGISTER_1,
2092 	.d_Q6_CLEAR_REGISTER_0 = ADRASTEA_Q6_CLEAR_REGISTER_0,
2093 	.d_Q6_CLEAR_REGISTER_1 = ADRASTEA_Q6_CLEAR_REGISTER_1,
2094 #endif
2095 
2096 #ifdef CONFIG_BYPASS_QMI
2097 	.d_BYPASS_QMI_TEMP_REGISTER = ADRASTEA_BYPASS_QMI_TEMP_REGISTER,
2098 #endif
2099 };
2100 
2101 struct hostdef_s adrastea_hostdef = {
2102 	.d_INT_STATUS_ENABLE_ERROR_LSB = ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB,
2103 	.d_INT_STATUS_ENABLE_ERROR_MASK = ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK,
2104 	.d_INT_STATUS_ENABLE_CPU_LSB = ADRASTEA_INT_STATUS_ENABLE_CPU_LSB,
2105 	.d_INT_STATUS_ENABLE_CPU_MASK = ADRASTEA_INT_STATUS_ENABLE_CPU_MASK,
2106 	.d_INT_STATUS_ENABLE_COUNTER_LSB =
2107 		ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB,
2108 	.d_INT_STATUS_ENABLE_COUNTER_MASK =
2109 		ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK,
2110 	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
2111 		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB,
2112 	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
2113 		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK,
2114 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
2115 		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
2116 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
2117 		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
2118 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
2119 		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
2120 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
2121 		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
2122 	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
2123 		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
2124 	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
2125 		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
2126 	.d_INT_STATUS_ENABLE_ADDRESS = ADRASTEA_INT_STATUS_ENABLE_ADDRESS,
2127 	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
2128 		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB,
2129 	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
2130 		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK,
2131 	.d_HOST_INT_STATUS_ADDRESS = ADRASTEA_HOST_INT_STATUS_ADDRESS,
2132 	.d_CPU_INT_STATUS_ADDRESS = ADRASTEA_CPU_INT_STATUS_ADDRESS,
2133 	.d_ERROR_INT_STATUS_ADDRESS = ADRASTEA_ERROR_INT_STATUS_ADDRESS,
2134 	.d_ERROR_INT_STATUS_WAKEUP_MASK = ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK,
2135 	.d_ERROR_INT_STATUS_WAKEUP_LSB = ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB,
2136 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
2137 		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
2138 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
2139 		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
2140 	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
2141 		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
2142 	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
2143 		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
2144 	.d_COUNT_DEC_ADDRESS = ADRASTEA_COUNT_DEC_ADDRESS,
2145 	.d_HOST_INT_STATUS_CPU_MASK = ADRASTEA_HOST_INT_STATUS_CPU_MASK,
2146 	.d_HOST_INT_STATUS_CPU_LSB = ADRASTEA_HOST_INT_STATUS_CPU_LSB,
2147 	.d_HOST_INT_STATUS_ERROR_MASK = ADRASTEA_HOST_INT_STATUS_ERROR_MASK,
2148 	.d_HOST_INT_STATUS_ERROR_LSB = ADRASTEA_HOST_INT_STATUS_ERROR_LSB,
2149 	.d_HOST_INT_STATUS_COUNTER_MASK = ADRASTEA_HOST_INT_STATUS_COUNTER_MASK,
2150 	.d_HOST_INT_STATUS_COUNTER_LSB = ADRASTEA_HOST_INT_STATUS_COUNTER_LSB,
2151 	.d_RX_LOOKAHEAD_VALID_ADDRESS = ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS,
2152 	.d_WINDOW_DATA_ADDRESS = ADRASTEA_WINDOW_DATA_ADDRESS,
2153 	.d_WINDOW_READ_ADDR_ADDRESS = ADRASTEA_WINDOW_READ_ADDR_ADDRESS,
2154 	.d_WINDOW_WRITE_ADDR_ADDRESS = ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS,
2155 	.d_SOC_GLOBAL_RESET_ADDRESS = ADRASTEA_SOC_GLOBAL_RESET_ADDRESS,
2156 	.d_RTC_STATE_ADDRESS = ADRASTEA_RTC_STATE_ADDRESS,
2157 	.d_RTC_STATE_COLD_RESET_MASK = ADRASTEA_RTC_STATE_COLD_RESET_MASK,
2158 	.d_PCIE_LOCAL_BASE_ADDRESS = ADRASTEA_PCIE_LOCAL_BASE_ADDRESS,
2159 	.d_PCIE_SOC_WAKE_RESET = ADRASTEA_PCIE_SOC_WAKE_RESET,
2160 	.d_PCIE_SOC_WAKE_ADDRESS = ADRASTEA_PCIE_SOC_WAKE_ADDRESS,
2161 	.d_PCIE_SOC_WAKE_V_MASK = ADRASTEA_PCIE_SOC_WAKE_V_MASK,
2162 	.d_RTC_STATE_V_MASK = ADRASTEA_RTC_STATE_V_MASK,
2163 	.d_RTC_STATE_V_LSB = ADRASTEA_RTC_STATE_V_LSB,
2164 	.d_FW_IND_EVENT_PENDING = ADRASTEA_FW_IND_EVENT_PENDING,
2165 	.d_FW_IND_INITIALIZED = ADRASTEA_FW_IND_INITIALIZED,
2166 	.d_FW_IND_HELPER = ADRASTEA_FW_IND_HELPER,
2167 	.d_RTC_STATE_V_ON = ADRASTEA_RTC_STATE_V_ON,
2168 #if defined(SDIO_3_0)
2169 	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
2170 		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_MASK,
2171 	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
2172 		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_LSB,
2173 #endif
2174 	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
2175 	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
2176 	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
2177 	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
2178 	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
2179 	.d_HOST_CE_COUNT = ADRASTEA_CE_COUNT,
2180 	.d_ENABLE_MSI = 0,
2181 	.d_MUX_ID_MASK = 0xf000,
2182 	.d_TRANSACTION_ID_MASK = 0x0fff,
2183 	.d_DESC_DATA_FLAG_MASK = 0x1FFFE3E0,
2184 	.d_A_SOC_PCIE_PCIE_BAR0_START = ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START,
2185 };
2186 
2187 
2188 struct ce_reg_def adrastea_ce_targetdef = {
2189 	/* copy_engine.c  */
2190 	.d_DST_WR_INDEX_ADDRESS = ADRASTEA_DST_WR_INDEX_OFFSET,
2191 	.d_SRC_WATERMARK_ADDRESS = ADRASTEA_SRC_WATERMARK_OFFSET,
2192 	.d_SRC_WATERMARK_LOW_MASK = ADRASTEA_SRC_WATERMARK_LOW_MASK,
2193 	.d_SRC_WATERMARK_HIGH_MASK = ADRASTEA_SRC_WATERMARK_HIGH_MASK,
2194 	.d_DST_WATERMARK_LOW_MASK = ADRASTEA_DST_WATERMARK_LOW_MASK,
2195 	.d_DST_WATERMARK_HIGH_MASK = ADRASTEA_DST_WATERMARK_HIGH_MASK,
2196 	.d_CURRENT_SRRI_ADDRESS = ADRASTEA_CURRENT_SRRI_OFFSET,
2197 	.d_CURRENT_DRRI_ADDRESS = ADRASTEA_CURRENT_DRRI_OFFSET,
2198 	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
2199 		ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
2200 	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
2201 		ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
2202 	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
2203 		ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
2204 	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
2205 		ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
2206 	.d_HOST_IS_ADDRESS = ADRASTEA_HOST_IS_OFFSET,
2207 	.d_MISC_IS_ADDRESS = ADRASTEA_MISC_IS_OFFSET,
2208 	.d_HOST_IS_COPY_COMPLETE_MASK = ADRASTEA_HOST_IS_COPY_COMPLETE_MASK,
2209 	.d_CE_WRAPPER_BASE_ADDRESS = ADRASTEA_CE_WRAPPER_BASE_ADDRESS,
2210 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
2211 		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET,
2212 	.d_CE_DDR_ADDRESS_FOR_RRI_LOW =
2213 		ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW,
2214 	.d_CE_DDR_ADDRESS_FOR_RRI_HIGH =
2215 		ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH,
2216 	.d_HOST_IE_ADDRESS = ADRASTEA_HOST_IE_OFFSET,
2217 	.d_HOST_IE_COPY_COMPLETE_MASK = ADRASTEA_HOST_IE_COPY_COMPLETE_MASK,
2218 	.d_SR_BA_ADDRESS = ADRASTEA_SR_BA_OFFSET,
2219 	.d_SR_BA_ADDRESS_HIGH = ADRASTEA_SR_BA_HIGH_OFFSET,
2220 	.d_SR_SIZE_ADDRESS = ADRASTEA_SR_SIZE_OFFSET,
2221 	.d_CE_CTRL1_ADDRESS = ADRASTEA_CE_CTRL1_OFFSET,
2222 	.d_CE_CTRL1_DMAX_LENGTH_MASK = ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK,
2223 	.d_DR_BA_ADDRESS = ADRASTEA_DR_BA_OFFSET,
2224 	.d_DR_BA_ADDRESS_HIGH = ADRASTEA_DR_BA_HIGH_OFFSET,
2225 	.d_DR_SIZE_ADDRESS = ADRASTEA_DR_SIZE_OFFSET,
2226 	.d_CE_CMD_REGISTER = ADRASTEA_CE_CMD_REGISTER_OFFSET,
2227 	.d_CE_MSI_ADDRESS = MISSING_FOR_ADRASTEA,
2228 	.d_CE_MSI_ADDRESS_HIGH = MISSING_FOR_ADRASTEA,
2229 	.d_CE_MSI_DATA = MISSING_FOR_ADRASTEA,
2230 	.d_CE_MSI_ENABLE_BIT = MISSING_FOR_ADRASTEA,
2231 	.d_MISC_IE_ADDRESS = ADRASTEA_MISC_IE_OFFSET,
2232 	.d_MISC_IS_AXI_ERR_MASK = ADRASTEA_MISC_IS_AXI_ERR_MASK,
2233 	.d_MISC_IS_DST_ADDR_ERR_MASK = ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK,
2234 	.d_MISC_IS_SRC_LEN_ERR_MASK = ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK,
2235 	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK,
2236 	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
2237 		ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK,
2238 	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
2239 		ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK,
2240 	.d_SRC_WATERMARK_LOW_LSB = ADRASTEA_SRC_WATERMARK_LOW_LSB,
2241 	.d_SRC_WATERMARK_HIGH_LSB = ADRASTEA_SRC_WATERMARK_HIGH_LSB,
2242 	.d_DST_WATERMARK_LOW_LSB = ADRASTEA_DST_WATERMARK_LOW_LSB,
2243 	.d_DST_WATERMARK_HIGH_LSB = ADRASTEA_DST_WATERMARK_HIGH_LSB,
2244 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
2245 		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
2246 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
2247 		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
2248 	.d_CE_CTRL1_DMAX_LENGTH_LSB = ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB,
2249 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
2250 		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
2251 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
2252 		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
2253 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
2254 		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
2255 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
2256 		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
2257 	.d_CE_CTRL1_IDX_UPD_EN_MASK =
2258 		ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M,
2259 	.d_CE_WRAPPER_DEBUG_OFFSET = ADRASTEA_CE_WRAPPER_DEBUG_OFFSET,
2260 	.d_CE_WRAPPER_DEBUG_SEL_MSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB,
2261 	.d_CE_WRAPPER_DEBUG_SEL_LSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB,
2262 	.d_CE_WRAPPER_DEBUG_SEL_MASK = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK,
2263 	.d_CE_DEBUG_OFFSET = ADRASTEA_CE_DEBUG_OFFSET,
2264 	.d_CE_DEBUG_SEL_MSB = ADRASTEA_CE_DEBUG_SEL_MSB,
2265 	.d_CE_DEBUG_SEL_LSB = ADRASTEA_CE_DEBUG_SEL_LSB,
2266 	.d_CE_DEBUG_SEL_MASK = ADRASTEA_CE_DEBUG_SEL_MASK,
2267 	.d_CE0_BASE_ADDRESS = ADRASTEA_CE0_BASE_ADDRESS,
2268 	.d_CE1_BASE_ADDRESS = ADRASTEA_CE1_BASE_ADDRESS,
2269 	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES =
2270 		MISSING_FOR_ADRASTEA,
2271 	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS =
2272 		MISSING_FOR_ADRASTEA,
2273 };
2274 
2275 
2276 struct host_shadow_regs_s adrastea_host_shadow_regs = {
2277 	.d_A_LOCAL_SHADOW_REG_VALUE_0  =
2278 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0,
2279 	.d_A_LOCAL_SHADOW_REG_VALUE_1  =
2280 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1,
2281 	.d_A_LOCAL_SHADOW_REG_VALUE_2  =
2282 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2,
2283 	.d_A_LOCAL_SHADOW_REG_VALUE_3  =
2284 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3,
2285 	.d_A_LOCAL_SHADOW_REG_VALUE_4  =
2286 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4,
2287 	.d_A_LOCAL_SHADOW_REG_VALUE_5  =
2288 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5,
2289 	.d_A_LOCAL_SHADOW_REG_VALUE_6  =
2290 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6,
2291 	.d_A_LOCAL_SHADOW_REG_VALUE_7  =
2292 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7,
2293 	.d_A_LOCAL_SHADOW_REG_VALUE_8  =
2294 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8,
2295 	.d_A_LOCAL_SHADOW_REG_VALUE_9  =
2296 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9,
2297 	.d_A_LOCAL_SHADOW_REG_VALUE_10 =
2298 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10,
2299 	.d_A_LOCAL_SHADOW_REG_VALUE_11 =
2300 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11,
2301 	.d_A_LOCAL_SHADOW_REG_VALUE_12 =
2302 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12,
2303 	.d_A_LOCAL_SHADOW_REG_VALUE_13 =
2304 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13,
2305 	.d_A_LOCAL_SHADOW_REG_VALUE_14 =
2306 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14,
2307 	.d_A_LOCAL_SHADOW_REG_VALUE_15 =
2308 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15,
2309 	.d_A_LOCAL_SHADOW_REG_VALUE_16 =
2310 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16,
2311 	.d_A_LOCAL_SHADOW_REG_VALUE_17 =
2312 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17,
2313 	.d_A_LOCAL_SHADOW_REG_VALUE_18 =
2314 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18,
2315 	.d_A_LOCAL_SHADOW_REG_VALUE_19 =
2316 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19,
2317 	.d_A_LOCAL_SHADOW_REG_VALUE_20 =
2318 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20,
2319 	.d_A_LOCAL_SHADOW_REG_VALUE_21 =
2320 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21,
2321 	.d_A_LOCAL_SHADOW_REG_VALUE_22 =
2322 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22,
2323 	.d_A_LOCAL_SHADOW_REG_VALUE_23 =
2324 		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23,
2325 	.d_A_LOCAL_SHADOW_REG_ADDRESS_0  =
2326 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0,
2327 	.d_A_LOCAL_SHADOW_REG_ADDRESS_1  =
2328 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1,
2329 	.d_A_LOCAL_SHADOW_REG_ADDRESS_2  =
2330 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2,
2331 	.d_A_LOCAL_SHADOW_REG_ADDRESS_3  =
2332 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3,
2333 	.d_A_LOCAL_SHADOW_REG_ADDRESS_4  =
2334 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4,
2335 	.d_A_LOCAL_SHADOW_REG_ADDRESS_5  =
2336 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5,
2337 	.d_A_LOCAL_SHADOW_REG_ADDRESS_6  =
2338 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6,
2339 	.d_A_LOCAL_SHADOW_REG_ADDRESS_7  =
2340 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7,
2341 	.d_A_LOCAL_SHADOW_REG_ADDRESS_8  =
2342 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8,
2343 	.d_A_LOCAL_SHADOW_REG_ADDRESS_9  =
2344 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9,
2345 	.d_A_LOCAL_SHADOW_REG_ADDRESS_10 =
2346 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10,
2347 	.d_A_LOCAL_SHADOW_REG_ADDRESS_11 =
2348 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11,
2349 	.d_A_LOCAL_SHADOW_REG_ADDRESS_12 =
2350 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12,
2351 	.d_A_LOCAL_SHADOW_REG_ADDRESS_13 =
2352 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13,
2353 	.d_A_LOCAL_SHADOW_REG_ADDRESS_14 =
2354 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14,
2355 	.d_A_LOCAL_SHADOW_REG_ADDRESS_15 =
2356 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15,
2357 	.d_A_LOCAL_SHADOW_REG_ADDRESS_16 =
2358 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16,
2359 	.d_A_LOCAL_SHADOW_REG_ADDRESS_17 =
2360 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17,
2361 	.d_A_LOCAL_SHADOW_REG_ADDRESS_18 =
2362 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18,
2363 	.d_A_LOCAL_SHADOW_REG_ADDRESS_19 =
2364 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19,
2365 	.d_A_LOCAL_SHADOW_REG_ADDRESS_20 =
2366 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20,
2367 	.d_A_LOCAL_SHADOW_REG_ADDRESS_21 =
2368 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21,
2369 	.d_A_LOCAL_SHADOW_REG_ADDRESS_22 =
2370 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22,
2371 	.d_A_LOCAL_SHADOW_REG_ADDRESS_23 =
2372 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23
2373 };
2374 
2375 struct targetdef_s genoa_targetdef = {
2376 	.d_RTC_SOC_BASE_ADDRESS = ADRASTEA_RTC_SOC_BASE_ADDRESS,
2377 	.d_RTC_WMAC_BASE_ADDRESS = ADRASTEA_RTC_WMAC_BASE_ADDRESS,
2378 	.d_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
2379 	.d_WLAN_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
2380 	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
2381 	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
2382 	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
2383 	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
2384 	.d_CLOCK_CONTROL_OFFSET = ADRASTEA_CLOCK_CONTROL_OFFSET,
2385 	.d_CLOCK_CONTROL_SI0_CLK_MASK = ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK,
2386 	.d_RESET_CONTROL_OFFSET = ADRASTEA_SOC_RESET_CONTROL_OFFSET,
2387 	.d_RESET_CONTROL_MBOX_RST_MASK = ADRASTEA_RESET_CONTROL_MBOX_RST_MASK,
2388 	.d_RESET_CONTROL_SI0_RST_MASK = ADRASTEA_RESET_CONTROL_SI0_RST_MASK,
2389 	.d_WLAN_RESET_CONTROL_OFFSET = ADRASTEA_WLAN_RESET_CONTROL_OFFSET,
2390 	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
2391 	ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK,
2392 	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
2393 	ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK,
2394 	.d_GPIO_BASE_ADDRESS = ADRASTEA_GPIO_BASE_ADDRESS,
2395 	.d_GPIO_PIN0_OFFSET = ADRASTEA_GPIO_PIN0_OFFSET,
2396 	.d_GPIO_PIN1_OFFSET = ADRASTEA_GPIO_PIN1_OFFSET,
2397 	.d_GPIO_PIN0_CONFIG_MASK = ADRASTEA_GPIO_PIN0_CONFIG_MASK,
2398 	.d_GPIO_PIN1_CONFIG_MASK = ADRASTEA_GPIO_PIN1_CONFIG_MASK,
2399 	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB,
2400 	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK,
2401 	.d_SI_CONFIG_I2C_LSB = ADRASTEA_SI_CONFIG_I2C_LSB,
2402 	.d_SI_CONFIG_I2C_MASK = ADRASTEA_SI_CONFIG_I2C_MASK,
2403 	.d_SI_CONFIG_POS_SAMPLE_LSB = ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB,
2404 	.d_SI_CONFIG_POS_SAMPLE_MASK = ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK,
2405 	.d_SI_CONFIG_INACTIVE_CLK_LSB = ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB,
2406 	.d_SI_CONFIG_INACTIVE_CLK_MASK = ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK,
2407 	.d_SI_CONFIG_INACTIVE_DATA_LSB = ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB,
2408 	.d_SI_CONFIG_INACTIVE_DATA_MASK = ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK,
2409 	.d_SI_CONFIG_DIVIDER_LSB = ADRASTEA_SI_CONFIG_DIVIDER_LSB,
2410 	.d_SI_CONFIG_DIVIDER_MASK = ADRASTEA_SI_CONFIG_DIVIDER_MASK,
2411 	.d_SI_BASE_ADDRESS = ADRASTEA_SI_BASE_ADDRESS,
2412 	.d_SI_CONFIG_OFFSET = ADRASTEA_SI_CONFIG_OFFSET,
2413 	.d_SI_TX_DATA0_OFFSET = ADRASTEA_SI_TX_DATA0_OFFSET,
2414 	.d_SI_TX_DATA1_OFFSET = ADRASTEA_SI_TX_DATA1_OFFSET,
2415 	.d_SI_RX_DATA0_OFFSET = ADRASTEA_SI_RX_DATA0_OFFSET,
2416 	.d_SI_RX_DATA1_OFFSET = ADRASTEA_SI_RX_DATA1_OFFSET,
2417 	.d_SI_CS_OFFSET = ADRASTEA_SI_CS_OFFSET,
2418 	.d_SI_CS_DONE_ERR_MASK = ADRASTEA_SI_CS_DONE_ERR_MASK,
2419 	.d_SI_CS_DONE_INT_MASK = ADRASTEA_SI_CS_DONE_INT_MASK,
2420 	.d_SI_CS_START_LSB = ADRASTEA_SI_CS_START_LSB,
2421 	.d_SI_CS_START_MASK = ADRASTEA_SI_CS_START_MASK,
2422 	.d_SI_CS_RX_CNT_LSB = ADRASTEA_SI_CS_RX_CNT_LSB,
2423 	.d_SI_CS_RX_CNT_MASK = ADRASTEA_SI_CS_RX_CNT_MASK,
2424 	.d_SI_CS_TX_CNT_LSB = ADRASTEA_SI_CS_TX_CNT_LSB,
2425 	.d_SI_CS_TX_CNT_MASK = ADRASTEA_SI_CS_TX_CNT_MASK,
2426 	.d_BOARD_DATA_SZ = ADRASTEA_BOARD_DATA_SZ,
2427 	.d_BOARD_EXT_DATA_SZ = ADRASTEA_BOARD_EXT_DATA_SZ,
2428 	.d_MBOX_BASE_ADDRESS = ADRASTEA_MBOX_BASE_ADDRESS,
2429 	.d_LOCAL_SCRATCH_OFFSET = ADRASTEA_LOCAL_SCRATCH_OFFSET,
2430 	.d_CPU_CLOCK_OFFSET = ADRASTEA_CPU_CLOCK_OFFSET,
2431 	.d_LPO_CAL_OFFSET = ADRASTEA_LPO_CAL_OFFSET,
2432 	.d_GPIO_PIN10_OFFSET = ADRASTEA_GPIO_PIN10_OFFSET,
2433 	.d_GPIO_PIN11_OFFSET = ADRASTEA_GPIO_PIN11_OFFSET,
2434 	.d_GPIO_PIN12_OFFSET = ADRASTEA_GPIO_PIN12_OFFSET,
2435 	.d_GPIO_PIN13_OFFSET = ADRASTEA_GPIO_PIN13_OFFSET,
2436 	.d_CLOCK_GPIO_OFFSET = ADRASTEA_CLOCK_GPIO_OFFSET,
2437 	.d_CPU_CLOCK_STANDARD_LSB = ADRASTEA_CPU_CLOCK_STANDARD_LSB,
2438 	.d_CPU_CLOCK_STANDARD_MASK = ADRASTEA_CPU_CLOCK_STANDARD_MASK,
2439 	.d_LPO_CAL_ENABLE_LSB = ADRASTEA_LPO_CAL_ENABLE_LSB,
2440 	.d_LPO_CAL_ENABLE_MASK = ADRASTEA_LPO_CAL_ENABLE_MASK,
2441 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
2442 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
2443 		ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
2444 	.d_ANALOG_INTF_BASE_ADDRESS = ADRASTEA_ANALOG_INTF_BASE_ADDRESS,
2445 	.d_WLAN_MAC_BASE_ADDRESS = ADRASTEA_WLAN_MAC_BASE_ADDRESS,
2446 	.d_FW_INDICATOR_ADDRESS = ADRASTEA_FW_INDICATOR_ADDRESS,
2447 	.d_DRAM_BASE_ADDRESS = ADRASTEA_DRAM_BASE_ADDRESS,
2448 	.d_SOC_CORE_BASE_ADDRESS = ADRASTEA_SOC_CORE_BASE_ADDRESS,
2449 	.d_CORE_CTRL_ADDRESS = ADRASTEA_CORE_CTRL_ADDRESS,
2450 	.d_CE_COUNT = ADRASTEA_CE_COUNT,
2451 	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
2452 	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
2453 	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
2454 	.d_PCIE_INTR_ENABLE_ADDRESS = ADRASTEA_HOST_ENABLE_REGISTER,
2455 	.d_PCIE_INTR_CLR_ADDRESS = ADRASTEA_HOST_CLEAR_REGISTER,
2456 	.d_PCIE_INTR_FIRMWARE_MASK = ADRASTEA_PCIE_INTR_FIRMWARE_MASK,
2457 	.d_PCIE_INTR_CE_MASK_ALL = ADRASTEA_PCIE_INTR_CE_MASK_ALL,
2458 	.d_CORE_CTRL_CPU_INTR_MASK = ADRASTEA_CORE_CTRL_CPU_INTR_MASK,
2459 	.d_SR_WR_INDEX_ADDRESS = ADRASTEA_SR_WR_INDEX_OFFSET,
2460 	.d_DST_WATERMARK_ADDRESS = ADRASTEA_DST_WATERMARK_OFFSET,
2461 	/* htt_rx.c */
2462 	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
2463 	ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK,
2464 	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB,
2465 	.d_RX_MPDU_START_0_SEQ_NUM_MASK = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK,
2466 	.d_RX_MPDU_START_0_SEQ_NUM_LSB = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB,
2467 	.d_RX_MPDU_START_2_PN_47_32_LSB = ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB,
2468 	.d_RX_MPDU_START_2_PN_47_32_MASK =
2469 		ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK,
2470 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
2471 		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
2472 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
2473 		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
2474 	.d_RX_MSDU_END_4_LAST_MSDU_MASK = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK,
2475 	.d_RX_MSDU_END_4_LAST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB,
2476 	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
2477 		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK,
2478 	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
2479 		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB,
2480 	.d_RX_ATTENTION_0_FRAGMENT_MASK = ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK,
2481 	.d_RX_ATTENTION_0_FRAGMENT_LSB = ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB,
2482 	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
2483 		ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
2484 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
2485 		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
2486 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
2487 		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
2488 	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
2489 		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK,
2490 	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
2491 		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB,
2492 	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
2493 		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
2494 	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
2495 		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK,
2496 	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
2497 		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB,
2498 	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
2499 		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK,
2500 	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
2501 		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB,
2502 	.d_RX_ATTENTION_0_MORE_DATA_MASK =
2503 		ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK,
2504 	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
2505 		ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK,
2506 	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
2507 		ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
2508 
2509 	/* PLL start */
2510 	.d_EFUSE_OFFSET = ADRASTEA_EFUSE_OFFSET,
2511 	.d_EFUSE_XTAL_SEL_MSB = ADRASTEA_EFUSE_XTAL_SEL_MSB,
2512 	.d_EFUSE_XTAL_SEL_LSB = ADRASTEA_EFUSE_XTAL_SEL_LSB,
2513 	.d_EFUSE_XTAL_SEL_MASK = ADRASTEA_EFUSE_XTAL_SEL_MASK,
2514 	.d_BB_PLL_CONFIG_OFFSET = ADRASTEA_BB_PLL_CONFIG_OFFSET,
2515 	.d_BB_PLL_CONFIG_OUTDIV_MSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB,
2516 	.d_BB_PLL_CONFIG_OUTDIV_LSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB,
2517 	.d_BB_PLL_CONFIG_OUTDIV_MASK = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK,
2518 	.d_BB_PLL_CONFIG_FRAC_MSB = ADRASTEA_BB_PLL_CONFIG_FRAC_MSB,
2519 	.d_BB_PLL_CONFIG_FRAC_LSB = ADRASTEA_BB_PLL_CONFIG_FRAC_LSB,
2520 	.d_BB_PLL_CONFIG_FRAC_MASK = ADRASTEA_BB_PLL_CONFIG_FRAC_MASK,
2521 	.d_WLAN_PLL_SETTLE_TIME_MSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB,
2522 	.d_WLAN_PLL_SETTLE_TIME_LSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB,
2523 	.d_WLAN_PLL_SETTLE_TIME_MASK = ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK,
2524 	.d_WLAN_PLL_SETTLE_OFFSET = ADRASTEA_WLAN_PLL_SETTLE_OFFSET,
2525 	.d_WLAN_PLL_SETTLE_SW_MASK = ADRASTEA_WLAN_PLL_SETTLE_SW_MASK,
2526 	.d_WLAN_PLL_SETTLE_RSTMASK = ADRASTEA_WLAN_PLL_SETTLE_RSTMASK,
2527 	.d_WLAN_PLL_SETTLE_RESET = ADRASTEA_WLAN_PLL_SETTLE_RESET,
2528 	.d_WLAN_PLL_CONTROL_NOPWD_MSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB,
2529 	.d_WLAN_PLL_CONTROL_NOPWD_LSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB,
2530 	.d_WLAN_PLL_CONTROL_NOPWD_MASK = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK,
2531 	.d_WLAN_PLL_CONTROL_BYPASS_MSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB,
2532 	.d_WLAN_PLL_CONTROL_BYPASS_LSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB,
2533 	.d_WLAN_PLL_CONTROL_BYPASS_MASK = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK,
2534 	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
2535 		ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET,
2536 	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB,
2537 	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB,
2538 	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
2539 		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK,
2540 	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
2541 		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET,
2542 	.d_WLAN_PLL_CONTROL_REFDIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB,
2543 	.d_WLAN_PLL_CONTROL_REFDIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB,
2544 	.d_WLAN_PLL_CONTROL_REFDIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK,
2545 	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
2546 		ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET,
2547 	.d_WLAN_PLL_CONTROL_DIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB,
2548 	.d_WLAN_PLL_CONTROL_DIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB,
2549 	.d_WLAN_PLL_CONTROL_DIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK,
2550 	.d_WLAN_PLL_CONTROL_DIV_RESET = ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET,
2551 	.d_WLAN_PLL_CONTROL_OFFSET = ADRASTEA_WLAN_PLL_CONTROL_OFFSET,
2552 	.d_WLAN_PLL_CONTROL_SW_MASK = ADRASTEA_WLAN_PLL_CONTROL_SW_MASK,
2553 	.d_WLAN_PLL_CONTROL_RSTMASK = ADRASTEA_WLAN_PLL_CONTROL_RSTMASK,
2554 	.d_WLAN_PLL_CONTROL_RESET = ADRASTEA_WLAN_PLL_CONTROL_RESET,
2555 	.d_SOC_CORE_CLK_CTRL_OFFSET = ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET,
2556 	.d_SOC_CORE_CLK_CTRL_DIV_MSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB,
2557 	.d_SOC_CORE_CLK_CTRL_DIV_LSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB,
2558 	.d_SOC_CORE_CLK_CTRL_DIV_MASK = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK,
2559 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
2560 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
2561 	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
2562 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
2563 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
2564 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
2565 	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
2566 		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
2567 	.d_RTC_SYNC_STATUS_OFFSET = ADRASTEA_RTC_SYNC_STATUS_OFFSET,
2568 	.d_SOC_CPU_CLOCK_OFFSET = ADRASTEA_SOC_CPU_CLOCK_OFFSET,
2569 	.d_SOC_CPU_CLOCK_STANDARD_MSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB,
2570 	.d_SOC_CPU_CLOCK_STANDARD_LSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB,
2571 	.d_SOC_CPU_CLOCK_STANDARD_MASK = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK,
2572 	/* PLL end */
2573 	.d_SOC_POWER_REG_OFFSET = ADRASTEA_SOC_POWER_REG_OFFSET,
2574 	.d_PCIE_INTR_CAUSE_ADDRESS = ADRASTEA_HOST_CAUSE_REGISTER,
2575 	.d_SOC_RESET_CONTROL_ADDRESS = ADRASTEA_SOC_RESET_CONTROL_ADDRESS,
2576 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
2577 		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
2578 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
2579 		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
2580 	.d_SOC_RESET_CONTROL_CE_RST_MASK =
2581 		ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK,
2582 	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
2583 		ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
2584 	.d_CPU_INTR_ADDRESS = ADRASTEA_CPU_INTR_ADDRESS,
2585 	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
2586 		ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS,
2587 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
2588 		ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
2589 	/* chip id start */
2590 	.d_SOC_CHIP_ID_ADDRESS = ADRASTEA_SOC_CHIP_ID_ADDRESS,
2591 	.d_SOC_CHIP_ID_VERSION_MASK = ADRASTEA_SOC_CHIP_ID_VERSION_MASK,
2592 	.d_SOC_CHIP_ID_VERSION_LSB = ADRASTEA_SOC_CHIP_ID_VERSION_LSB,
2593 	.d_SOC_CHIP_ID_REVISION_MASK = ADRASTEA_SOC_CHIP_ID_REVISION_MASK,
2594 	.d_SOC_CHIP_ID_REVISION_LSB = ADRASTEA_SOC_CHIP_ID_REVISION_LSB,
2595 	/* chip id end */
2596 	.d_A_SOC_CORE_SCRATCH_0_ADDRESS = ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS,
2597 	.d_A_SOC_CORE_SPARE_0_REGISTER = ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER,
2598 	.d_PCIE_INTR_FIRMWARE_ROUTE_MASK =
2599 		ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK,
2600 	.d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 =
2601 		ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1,
2602 	.d_A_SOC_CORE_SPARE_1_REGISTER =
2603 		ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER,
2604 	.d_A_SOC_CORE_PCIE_INTR_CLR_GRP1 =
2605 		ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1,
2606 	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 =
2607 		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1,
2608 	.d_A_SOC_PCIE_PCIE_SCRATCH_0 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0,
2609 	.d_A_SOC_PCIE_PCIE_SCRATCH_1 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1,
2610 	.d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA =
2611 		ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA,
2612 	.d_A_SOC_PCIE_PCIE_SCRATCH_2 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2,
2613 	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK =
2614 		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK,
2615 	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET,
2616 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
2617 	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
2618 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
2619 		ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
2620 	.d_WLAN_DEBUG_CONTROL_OFFSET = ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET,
2621 	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
2622 		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB,
2623 	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
2624 		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB,
2625 	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
2626 		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK,
2627 	.d_WLAN_DEBUG_OUT_OFFSET = ADRASTEA_WLAN_DEBUG_OUT_OFFSET,
2628 	.d_WLAN_DEBUG_OUT_DATA_MSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB,
2629 	.d_WLAN_DEBUG_OUT_DATA_LSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB,
2630 	.d_WLAN_DEBUG_OUT_DATA_MASK = ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK,
2631 	.d_AMBA_DEBUG_BUS_OFFSET = ADRASTEA_AMBA_DEBUG_BUS_OFFSET,
2632 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
2633 		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
2634 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
2635 		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
2636 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
2637 		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
2638 	.d_AMBA_DEBUG_BUS_SEL_MSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB,
2639 	.d_AMBA_DEBUG_BUS_SEL_LSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB,
2640 	.d_AMBA_DEBUG_BUS_SEL_MASK = ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK,
2641 
2642 #ifdef QCA_WIFI_3_0_ADRASTEA
2643 	.d_Q6_ENABLE_REGISTER_0 = ADRASTEA_Q6_ENABLE_REGISTER_0,
2644 	.d_Q6_ENABLE_REGISTER_1 = ADRASTEA_Q6_ENABLE_REGISTER_1,
2645 	.d_Q6_CAUSE_REGISTER_0 = ADRASTEA_Q6_CAUSE_REGISTER_0,
2646 	.d_Q6_CAUSE_REGISTER_1 = ADRASTEA_Q6_CAUSE_REGISTER_1,
2647 	.d_Q6_CLEAR_REGISTER_0 = ADRASTEA_Q6_CLEAR_REGISTER_0,
2648 	.d_Q6_CLEAR_REGISTER_1 = ADRASTEA_Q6_CLEAR_REGISTER_1,
2649 #endif
2650 
2651 #ifdef CONFIG_BYPASS_QMI
2652 	.d_BYPASS_QMI_TEMP_REGISTER = GENOA_OFFSET +
2653 				      ADRASTEA_BYPASS_QMI_TEMP_REGISTER,
2654 #endif
2655 };
2656 
2657 struct hostdef_s genoa_hostdef = {
2658 	.d_INT_STATUS_ENABLE_ERROR_LSB = ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB,
2659 	.d_INT_STATUS_ENABLE_ERROR_MASK = ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK,
2660 	.d_INT_STATUS_ENABLE_CPU_LSB = ADRASTEA_INT_STATUS_ENABLE_CPU_LSB,
2661 	.d_INT_STATUS_ENABLE_CPU_MASK = ADRASTEA_INT_STATUS_ENABLE_CPU_MASK,
2662 	.d_INT_STATUS_ENABLE_COUNTER_LSB =
2663 		ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB,
2664 	.d_INT_STATUS_ENABLE_COUNTER_MASK =
2665 		ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK,
2666 	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
2667 		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB,
2668 	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
2669 		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK,
2670 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
2671 		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
2672 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
2673 		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
2674 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
2675 		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
2676 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
2677 		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
2678 	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
2679 		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
2680 	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
2681 		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
2682 	.d_INT_STATUS_ENABLE_ADDRESS = ADRASTEA_INT_STATUS_ENABLE_ADDRESS,
2683 	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
2684 		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB,
2685 	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
2686 		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK,
2687 	.d_HOST_INT_STATUS_ADDRESS = ADRASTEA_HOST_INT_STATUS_ADDRESS,
2688 	.d_CPU_INT_STATUS_ADDRESS = ADRASTEA_CPU_INT_STATUS_ADDRESS,
2689 	.d_ERROR_INT_STATUS_ADDRESS = ADRASTEA_ERROR_INT_STATUS_ADDRESS,
2690 	.d_ERROR_INT_STATUS_WAKEUP_MASK = ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK,
2691 	.d_ERROR_INT_STATUS_WAKEUP_LSB = ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB,
2692 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
2693 		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
2694 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
2695 		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
2696 	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
2697 		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
2698 	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
2699 		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
2700 	.d_COUNT_DEC_ADDRESS = ADRASTEA_COUNT_DEC_ADDRESS,
2701 	.d_HOST_INT_STATUS_CPU_MASK = ADRASTEA_HOST_INT_STATUS_CPU_MASK,
2702 	.d_HOST_INT_STATUS_CPU_LSB = ADRASTEA_HOST_INT_STATUS_CPU_LSB,
2703 	.d_HOST_INT_STATUS_ERROR_MASK = ADRASTEA_HOST_INT_STATUS_ERROR_MASK,
2704 	.d_HOST_INT_STATUS_ERROR_LSB = ADRASTEA_HOST_INT_STATUS_ERROR_LSB,
2705 	.d_HOST_INT_STATUS_COUNTER_MASK = ADRASTEA_HOST_INT_STATUS_COUNTER_MASK,
2706 	.d_HOST_INT_STATUS_COUNTER_LSB = ADRASTEA_HOST_INT_STATUS_COUNTER_LSB,
2707 	.d_RX_LOOKAHEAD_VALID_ADDRESS = ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS,
2708 	.d_WINDOW_DATA_ADDRESS = ADRASTEA_WINDOW_DATA_ADDRESS,
2709 	.d_WINDOW_READ_ADDR_ADDRESS = ADRASTEA_WINDOW_READ_ADDR_ADDRESS,
2710 	.d_WINDOW_WRITE_ADDR_ADDRESS = ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS,
2711 	.d_SOC_GLOBAL_RESET_ADDRESS = ADRASTEA_SOC_GLOBAL_RESET_ADDRESS,
2712 	.d_RTC_STATE_ADDRESS = ADRASTEA_RTC_STATE_ADDRESS,
2713 	.d_RTC_STATE_COLD_RESET_MASK = ADRASTEA_RTC_STATE_COLD_RESET_MASK,
2714 	.d_PCIE_LOCAL_BASE_ADDRESS = ADRASTEA_PCIE_LOCAL_BASE_ADDRESS,
2715 	.d_PCIE_SOC_WAKE_RESET = ADRASTEA_PCIE_SOC_WAKE_RESET,
2716 	.d_PCIE_SOC_WAKE_ADDRESS = ADRASTEA_PCIE_SOC_WAKE_ADDRESS,
2717 	.d_PCIE_SOC_WAKE_V_MASK = ADRASTEA_PCIE_SOC_WAKE_V_MASK,
2718 	.d_RTC_STATE_V_MASK = ADRASTEA_RTC_STATE_V_MASK,
2719 	.d_RTC_STATE_V_LSB = ADRASTEA_RTC_STATE_V_LSB,
2720 	.d_FW_IND_EVENT_PENDING = ADRASTEA_FW_IND_EVENT_PENDING,
2721 	.d_FW_IND_INITIALIZED = ADRASTEA_FW_IND_INITIALIZED,
2722 	.d_FW_IND_HELPER = ADRASTEA_FW_IND_HELPER,
2723 	.d_RTC_STATE_V_ON = ADRASTEA_RTC_STATE_V_ON,
2724 #if defined(SDIO_3_0)
2725 	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
2726 		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_MASK,
2727 	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
2728 		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_LSB,
2729 #endif
2730 	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
2731 	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
2732 	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
2733 	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
2734 	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
2735 	.d_HOST_CE_COUNT = ADRASTEA_CE_COUNT,
2736 	.d_ENABLE_MSI = 0,
2737 	.d_MUX_ID_MASK = 0xf000,
2738 	.d_TRANSACTION_ID_MASK = 0x0fff,
2739 	.d_DESC_DATA_FLAG_MASK = 0x1FFFE3E0,
2740 	.d_A_SOC_PCIE_PCIE_BAR0_START = ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START,
2741 };
2742 
2743 struct ce_reg_def genoa_ce_targetdef = {
2744 	/* copy_engine.c  */
2745 	.d_DST_WR_INDEX_ADDRESS = ADRASTEA_DST_WR_INDEX_OFFSET,
2746 	.d_SRC_WATERMARK_ADDRESS = ADRASTEA_SRC_WATERMARK_OFFSET,
2747 	.d_SRC_WATERMARK_LOW_MASK = ADRASTEA_SRC_WATERMARK_LOW_MASK,
2748 	.d_SRC_WATERMARK_HIGH_MASK = ADRASTEA_SRC_WATERMARK_HIGH_MASK,
2749 	.d_DST_WATERMARK_LOW_MASK = ADRASTEA_DST_WATERMARK_LOW_MASK,
2750 	.d_DST_WATERMARK_HIGH_MASK = ADRASTEA_DST_WATERMARK_HIGH_MASK,
2751 	.d_CURRENT_SRRI_ADDRESS = ADRASTEA_CURRENT_SRRI_OFFSET,
2752 	.d_CURRENT_DRRI_ADDRESS = ADRASTEA_CURRENT_DRRI_OFFSET,
2753 	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
2754 		ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
2755 	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
2756 		ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
2757 	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
2758 		ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
2759 	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
2760 		ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
2761 	.d_HOST_IS_ADDRESS = ADRASTEA_HOST_IS_OFFSET,
2762 	.d_MISC_IS_ADDRESS = ADRASTEA_MISC_IS_OFFSET,
2763 	.d_HOST_IS_COPY_COMPLETE_MASK = ADRASTEA_HOST_IS_COPY_COMPLETE_MASK,
2764 	.d_CE_WRAPPER_BASE_ADDRESS = GENOA_OFFSET +
2765 				     ADRASTEA_CE_WRAPPER_BASE_ADDRESS,
2766 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
2767 		GENOA_OFFSET +
2768 		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET,
2769 	.d_CE_DDR_ADDRESS_FOR_RRI_LOW =
2770 		GENOA_OFFSET + ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW,
2771 	.d_CE_DDR_ADDRESS_FOR_RRI_HIGH =
2772 		GENOA_OFFSET + ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH,
2773 	.d_HOST_IE_ADDRESS = ADRASTEA_HOST_IE_OFFSET,
2774 	.d_HOST_IE_COPY_COMPLETE_MASK = ADRASTEA_HOST_IE_COPY_COMPLETE_MASK,
2775 	.d_SR_BA_ADDRESS = ADRASTEA_SR_BA_OFFSET,
2776 	.d_SR_BA_ADDRESS_HIGH = ADRASTEA_SR_BA_HIGH_OFFSET,
2777 	.d_SR_SIZE_ADDRESS = ADRASTEA_SR_SIZE_OFFSET,
2778 	.d_CE_CTRL1_ADDRESS = ADRASTEA_CE_CTRL1_OFFSET,
2779 	.d_CE_CTRL1_DMAX_LENGTH_MASK = ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK,
2780 	.d_DR_BA_ADDRESS = ADRASTEA_DR_BA_OFFSET,
2781 	.d_DR_BA_ADDRESS_HIGH = ADRASTEA_DR_BA_HIGH_OFFSET,
2782 	.d_DR_SIZE_ADDRESS = ADRASTEA_DR_SIZE_OFFSET,
2783 	.d_CE_CMD_REGISTER = ADRASTEA_CE_CMD_REGISTER_OFFSET,
2784 	.d_CE_MSI_ADDRESS = MISSING_FOR_ADRASTEA,
2785 	.d_CE_MSI_ADDRESS_HIGH = MISSING_FOR_ADRASTEA,
2786 	.d_CE_MSI_DATA = MISSING_FOR_ADRASTEA,
2787 	.d_CE_MSI_ENABLE_BIT = MISSING_FOR_ADRASTEA,
2788 	.d_MISC_IE_ADDRESS = ADRASTEA_MISC_IE_OFFSET,
2789 	.d_MISC_IS_AXI_ERR_MASK = ADRASTEA_MISC_IS_AXI_ERR_MASK,
2790 	.d_MISC_IS_DST_ADDR_ERR_MASK = ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK,
2791 	.d_MISC_IS_SRC_LEN_ERR_MASK = ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK,
2792 	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK,
2793 	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
2794 		ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK,
2795 	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
2796 		ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK,
2797 	.d_SRC_WATERMARK_LOW_LSB = ADRASTEA_SRC_WATERMARK_LOW_LSB,
2798 	.d_SRC_WATERMARK_HIGH_LSB = ADRASTEA_SRC_WATERMARK_HIGH_LSB,
2799 	.d_DST_WATERMARK_LOW_LSB = ADRASTEA_DST_WATERMARK_LOW_LSB,
2800 	.d_DST_WATERMARK_HIGH_LSB = ADRASTEA_DST_WATERMARK_HIGH_LSB,
2801 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
2802 		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
2803 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
2804 		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
2805 	.d_CE_CTRL1_DMAX_LENGTH_LSB = ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB,
2806 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
2807 		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
2808 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
2809 		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
2810 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
2811 		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
2812 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
2813 		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
2814 	.d_CE_CTRL1_IDX_UPD_EN_MASK =
2815 	    ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M,
2816 	.d_CE_WRAPPER_DEBUG_OFFSET = ADRASTEA_CE_WRAPPER_DEBUG_OFFSET,
2817 	.d_CE_WRAPPER_DEBUG_SEL_MSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB,
2818 	.d_CE_WRAPPER_DEBUG_SEL_LSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB,
2819 	.d_CE_WRAPPER_DEBUG_SEL_MASK = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK,
2820 	.d_CE_DEBUG_OFFSET = ADRASTEA_CE_DEBUG_OFFSET,
2821 	.d_CE_DEBUG_SEL_MSB = ADRASTEA_CE_DEBUG_SEL_MSB,
2822 	.d_CE_DEBUG_SEL_LSB = ADRASTEA_CE_DEBUG_SEL_LSB,
2823 	.d_CE_DEBUG_SEL_MASK = ADRASTEA_CE_DEBUG_SEL_MASK,
2824 	.d_CE0_BASE_ADDRESS = GENOA_OFFSET + ADRASTEA_CE0_BASE_ADDRESS,
2825 	.d_CE1_BASE_ADDRESS = GENOA_OFFSET + ADRASTEA_CE1_BASE_ADDRESS,
2826 	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES =
2827 		MISSING_FOR_ADRASTEA,
2828 	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS =
2829 		MISSING_FOR_ADRASTEA,
2830 };
2831 
2832 #ifdef QCN7605_PCIE_SHADOW_REG_SUPPORT
2833 
2834 #define PCIE_SHADOW_REG_VALUE_0 0x2F024
2835 #define PCIE_SHADOW_REG_VALUE_1 0x2F028
2836 #define PCIE_SHADOW_REG_VALUE_2 0x2F02C
2837 #define PCIE_SHADOW_REG_VALUE_3 0x2F030
2838 #define PCIE_SHADOW_REG_VALUE_4 0x2F034
2839 #define PCIE_SHADOW_REG_VALUE_5 0x2F038
2840 #define PCIE_SHADOW_REG_VALUE_6 0x2F03C
2841 #define PCIE_SHADOW_REG_VALUE_7 0x2F040
2842 #define PCIE_SHADOW_REG_VALUE_8 0x2F044
2843 #define PCIE_SHADOW_REG_VALUE_9 0x2F048
2844 #define PCIE_SHADOW_REG_VALUE_10 0x2F04C
2845 #define PCIE_SHADOW_REG_VALUE_11 0x2F050
2846 #define PCIE_SHADOW_REG_VALUE_12 0x2F054
2847 #define PCIE_SHADOW_REG_VALUE_13 0x2F058
2848 #define PCIE_SHADOW_REG_VALUE_14 0x2F05C
2849 #define PCIE_SHADOW_REG_VALUE_15 0x2F060
2850 #define PCIE_SHADOW_REG_VALUE_16 0x2F064
2851 #define PCIE_SHADOW_REG_VALUE_17 0x2F068
2852 #define PCIE_SHADOW_REG_VALUE_18 0x2F06C
2853 #define PCIE_SHADOW_REG_VALUE_19 0x2F070
2854 #define PCIE_SHADOW_REG_VALUE_20 0x2F074
2855 #define PCIE_SHADOW_REG_VALUE_21 0x2F078
2856 #define PCIE_SHADOW_REG_VALUE_22 0x2F07C
2857 #define PCIE_SHADOW_REG_VALUE_23 0x2F080
2858 
2859 #define PCIE_SHADOW_REG_INTER_ADDR_0 0x21000
2860 #define PCIE_SHADOW_REG_INTER_ADDR_1 0x21004
2861 #define PCIE_SHADOW_REG_INTER_ADDR_2 0x21008
2862 #define PCIE_SHADOW_REG_INTER_ADDR_3 0x2100C
2863 #define PCIE_SHADOW_REG_INTER_ADDR_4 0x21010
2864 #define PCIE_SHADOW_REG_INTER_ADDR_5 0x21014
2865 #define PCIE_SHADOW_REG_INTER_ADDR_6 0x21018
2866 #define PCIE_SHADOW_REG_INTER_ADDR_7 0x2101C
2867 #define PCIE_SHADOW_REG_INTER_ADDR_8 0x21020
2868 #define PCIE_SHADOW_REG_INTER_ADDR_9 0x21024
2869 #define PCIE_SHADOW_REG_INTER_ADDR_10 0x21028
2870 #define PCIE_SHADOW_REG_INTER_ADDR_11 0x2102C
2871 #define PCIE_SHADOW_REG_INTER_ADDR_12 0x21030
2872 #define PCIE_SHADOW_REG_INTER_ADDR_13 0x21034
2873 #define PCIE_SHADOW_REG_INTER_ADDR_14 0x21038
2874 #define PCIE_SHADOW_REG_INTER_ADDR_15 0x2103C
2875 #define PCIE_SHADOW_REG_INTER_ADDR_16 0x21040
2876 #define PCIE_SHADOW_REG_INTER_ADDR_17 0x21044
2877 #define PCIE_SHADOW_REG_INTER_ADDR_18 0x21048
2878 #define PCIE_SHADOW_REG_INTER_ADDR_19 0x2104C
2879 #define PCIE_SHADOW_REG_INTER_ADDR_20 0x21050
2880 #define PCIE_SHADOW_REG_INTER_ADDR_21 0x21054
2881 #define PCIE_SHADOW_REG_INTER_ADDR_22 0x21058
2882 #define PCIE_SHADOW_REG_INTER_ADDR_23 0x2105C
2883 
2884 struct host_shadow_regs_s genoa_host_shadow_regs = {
2885 	.d_A_LOCAL_SHADOW_REG_VALUE_0  = PCIE_SHADOW_REG_VALUE_0,
2886 	.d_A_LOCAL_SHADOW_REG_VALUE_1  = PCIE_SHADOW_REG_VALUE_1,
2887 	.d_A_LOCAL_SHADOW_REG_VALUE_2  = PCIE_SHADOW_REG_VALUE_2,
2888 	.d_A_LOCAL_SHADOW_REG_VALUE_3  = PCIE_SHADOW_REG_VALUE_3,
2889 	.d_A_LOCAL_SHADOW_REG_VALUE_4  = PCIE_SHADOW_REG_VALUE_4,
2890 	.d_A_LOCAL_SHADOW_REG_VALUE_5  = PCIE_SHADOW_REG_VALUE_5,
2891 	.d_A_LOCAL_SHADOW_REG_VALUE_6  = PCIE_SHADOW_REG_VALUE_6,
2892 	.d_A_LOCAL_SHADOW_REG_VALUE_7  = PCIE_SHADOW_REG_VALUE_7,
2893 	.d_A_LOCAL_SHADOW_REG_VALUE_8  = PCIE_SHADOW_REG_VALUE_8,
2894 	.d_A_LOCAL_SHADOW_REG_VALUE_9  = PCIE_SHADOW_REG_VALUE_9,
2895 	.d_A_LOCAL_SHADOW_REG_VALUE_10 = PCIE_SHADOW_REG_VALUE_10,
2896 	.d_A_LOCAL_SHADOW_REG_VALUE_11 = PCIE_SHADOW_REG_VALUE_11,
2897 	.d_A_LOCAL_SHADOW_REG_VALUE_12 = PCIE_SHADOW_REG_VALUE_12,
2898 	.d_A_LOCAL_SHADOW_REG_VALUE_13 = PCIE_SHADOW_REG_VALUE_13,
2899 	.d_A_LOCAL_SHADOW_REG_VALUE_14 = PCIE_SHADOW_REG_VALUE_14,
2900 	.d_A_LOCAL_SHADOW_REG_VALUE_15 = PCIE_SHADOW_REG_VALUE_15,
2901 	.d_A_LOCAL_SHADOW_REG_VALUE_16 = PCIE_SHADOW_REG_VALUE_16,
2902 	.d_A_LOCAL_SHADOW_REG_VALUE_17 = PCIE_SHADOW_REG_VALUE_17,
2903 	.d_A_LOCAL_SHADOW_REG_VALUE_18 = PCIE_SHADOW_REG_VALUE_18,
2904 	.d_A_LOCAL_SHADOW_REG_VALUE_19 = PCIE_SHADOW_REG_VALUE_19,
2905 	.d_A_LOCAL_SHADOW_REG_VALUE_20 = PCIE_SHADOW_REG_VALUE_20,
2906 	.d_A_LOCAL_SHADOW_REG_VALUE_21 = PCIE_SHADOW_REG_VALUE_21,
2907 	.d_A_LOCAL_SHADOW_REG_VALUE_22 = PCIE_SHADOW_REG_VALUE_22,
2908 	.d_A_LOCAL_SHADOW_REG_VALUE_23 = PCIE_SHADOW_REG_VALUE_23,
2909 	.d_A_LOCAL_SHADOW_REG_ADDRESS_0  = PCIE_SHADOW_REG_INTER_ADDR_0,
2910 	.d_A_LOCAL_SHADOW_REG_ADDRESS_1  = PCIE_SHADOW_REG_INTER_ADDR_1,
2911 	.d_A_LOCAL_SHADOW_REG_ADDRESS_2  = PCIE_SHADOW_REG_INTER_ADDR_2,
2912 	.d_A_LOCAL_SHADOW_REG_ADDRESS_3  = PCIE_SHADOW_REG_INTER_ADDR_3,
2913 	.d_A_LOCAL_SHADOW_REG_ADDRESS_4  = PCIE_SHADOW_REG_INTER_ADDR_4,
2914 	.d_A_LOCAL_SHADOW_REG_ADDRESS_5  = PCIE_SHADOW_REG_INTER_ADDR_5,
2915 	.d_A_LOCAL_SHADOW_REG_ADDRESS_6  = PCIE_SHADOW_REG_INTER_ADDR_6,
2916 	.d_A_LOCAL_SHADOW_REG_ADDRESS_7  = PCIE_SHADOW_REG_INTER_ADDR_7,
2917 	.d_A_LOCAL_SHADOW_REG_ADDRESS_8  = PCIE_SHADOW_REG_INTER_ADDR_8,
2918 	.d_A_LOCAL_SHADOW_REG_ADDRESS_9  = PCIE_SHADOW_REG_INTER_ADDR_9,
2919 	.d_A_LOCAL_SHADOW_REG_ADDRESS_10 = PCIE_SHADOW_REG_INTER_ADDR_10,
2920 	.d_A_LOCAL_SHADOW_REG_ADDRESS_11 = PCIE_SHADOW_REG_INTER_ADDR_11,
2921 	.d_A_LOCAL_SHADOW_REG_ADDRESS_12 = PCIE_SHADOW_REG_INTER_ADDR_12,
2922 	.d_A_LOCAL_SHADOW_REG_ADDRESS_13 = PCIE_SHADOW_REG_INTER_ADDR_13,
2923 	.d_A_LOCAL_SHADOW_REG_ADDRESS_14 = PCIE_SHADOW_REG_INTER_ADDR_14,
2924 	.d_A_LOCAL_SHADOW_REG_ADDRESS_15 = PCIE_SHADOW_REG_INTER_ADDR_15,
2925 	.d_A_LOCAL_SHADOW_REG_ADDRESS_16 = PCIE_SHADOW_REG_INTER_ADDR_16,
2926 	.d_A_LOCAL_SHADOW_REG_ADDRESS_17 = PCIE_SHADOW_REG_INTER_ADDR_17,
2927 	.d_A_LOCAL_SHADOW_REG_ADDRESS_18 = PCIE_SHADOW_REG_INTER_ADDR_18,
2928 	.d_A_LOCAL_SHADOW_REG_ADDRESS_19 = PCIE_SHADOW_REG_INTER_ADDR_19,
2929 	.d_A_LOCAL_SHADOW_REG_ADDRESS_20 = PCIE_SHADOW_REG_INTER_ADDR_20,
2930 	.d_A_LOCAL_SHADOW_REG_ADDRESS_21 = PCIE_SHADOW_REG_INTER_ADDR_21,
2931 	.d_A_LOCAL_SHADOW_REG_ADDRESS_22 = PCIE_SHADOW_REG_INTER_ADDR_22,
2932 	.d_A_LOCAL_SHADOW_REG_ADDRESS_23 = PCIE_SHADOW_REG_INTER_ADDR_23,
2933 };
2934 
2935 #else
2936 
2937 struct host_shadow_regs_s genoa_host_shadow_regs = {
2938 	.d_A_LOCAL_SHADOW_REG_VALUE_0  =
2939 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0,
2940 	.d_A_LOCAL_SHADOW_REG_VALUE_1  =
2941 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1,
2942 	.d_A_LOCAL_SHADOW_REG_VALUE_2  =
2943 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2,
2944 	.d_A_LOCAL_SHADOW_REG_VALUE_3  =
2945 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3,
2946 	.d_A_LOCAL_SHADOW_REG_VALUE_4  =
2947 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4,
2948 	.d_A_LOCAL_SHADOW_REG_VALUE_5  =
2949 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5,
2950 	.d_A_LOCAL_SHADOW_REG_VALUE_6  =
2951 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6,
2952 	.d_A_LOCAL_SHADOW_REG_VALUE_7  =
2953 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7,
2954 	.d_A_LOCAL_SHADOW_REG_VALUE_8  =
2955 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8,
2956 	.d_A_LOCAL_SHADOW_REG_VALUE_9  =
2957 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9,
2958 	.d_A_LOCAL_SHADOW_REG_VALUE_10 =
2959 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10,
2960 	.d_A_LOCAL_SHADOW_REG_VALUE_11 =
2961 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11,
2962 	.d_A_LOCAL_SHADOW_REG_VALUE_12 =
2963 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12,
2964 	.d_A_LOCAL_SHADOW_REG_VALUE_13 =
2965 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13,
2966 	.d_A_LOCAL_SHADOW_REG_VALUE_14 =
2967 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14,
2968 	.d_A_LOCAL_SHADOW_REG_VALUE_15 =
2969 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15,
2970 	.d_A_LOCAL_SHADOW_REG_VALUE_16 =
2971 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16,
2972 	.d_A_LOCAL_SHADOW_REG_VALUE_17 =
2973 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17,
2974 	.d_A_LOCAL_SHADOW_REG_VALUE_18 =
2975 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18,
2976 	.d_A_LOCAL_SHADOW_REG_VALUE_19 =
2977 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19,
2978 	.d_A_LOCAL_SHADOW_REG_VALUE_20 =
2979 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20,
2980 	.d_A_LOCAL_SHADOW_REG_VALUE_21 =
2981 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21,
2982 	.d_A_LOCAL_SHADOW_REG_VALUE_22 =
2983 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22,
2984 	.d_A_LOCAL_SHADOW_REG_VALUE_23 =
2985 		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23,
2986 	.d_A_LOCAL_SHADOW_REG_ADDRESS_0  =
2987 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0,
2988 	.d_A_LOCAL_SHADOW_REG_ADDRESS_1  =
2989 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1,
2990 	.d_A_LOCAL_SHADOW_REG_ADDRESS_2  =
2991 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2,
2992 	.d_A_LOCAL_SHADOW_REG_ADDRESS_3  =
2993 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3,
2994 	.d_A_LOCAL_SHADOW_REG_ADDRESS_4  =
2995 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4,
2996 	.d_A_LOCAL_SHADOW_REG_ADDRESS_5  =
2997 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5,
2998 	.d_A_LOCAL_SHADOW_REG_ADDRESS_6  =
2999 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6,
3000 	.d_A_LOCAL_SHADOW_REG_ADDRESS_7  =
3001 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7,
3002 	.d_A_LOCAL_SHADOW_REG_ADDRESS_8  =
3003 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8,
3004 	.d_A_LOCAL_SHADOW_REG_ADDRESS_9  =
3005 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9,
3006 	.d_A_LOCAL_SHADOW_REG_ADDRESS_10 =
3007 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10,
3008 	.d_A_LOCAL_SHADOW_REG_ADDRESS_11 =
3009 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11,
3010 	.d_A_LOCAL_SHADOW_REG_ADDRESS_12 =
3011 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12,
3012 	.d_A_LOCAL_SHADOW_REG_ADDRESS_13 =
3013 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13,
3014 	.d_A_LOCAL_SHADOW_REG_ADDRESS_14 =
3015 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14,
3016 	.d_A_LOCAL_SHADOW_REG_ADDRESS_15 =
3017 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15,
3018 	.d_A_LOCAL_SHADOW_REG_ADDRESS_16 =
3019 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16,
3020 	.d_A_LOCAL_SHADOW_REG_ADDRESS_17 =
3021 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17,
3022 	.d_A_LOCAL_SHADOW_REG_ADDRESS_18 =
3023 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18,
3024 	.d_A_LOCAL_SHADOW_REG_ADDRESS_19 =
3025 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19,
3026 	.d_A_LOCAL_SHADOW_REG_ADDRESS_20 =
3027 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20,
3028 	.d_A_LOCAL_SHADOW_REG_ADDRESS_21 =
3029 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21,
3030 	.d_A_LOCAL_SHADOW_REG_ADDRESS_22 =
3031 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22,
3032 	.d_A_LOCAL_SHADOW_REG_ADDRESS_23 =
3033 		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23
3034 };
3035 #endif
3036 
3037 #endif /* ADRASTEA_REG_DEF_H */
3038