1 /* 2 * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 6 * 7 * 8 * Permission to use, copy, modify, and/or distribute this software for 9 * any purpose with or without fee is hereby granted, provided that the 10 * above copyright notice and this permission notice appear in all 11 * copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 14 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 15 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 16 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 17 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 18 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* 24 * This file was originally distributed by Qualcomm Atheros, Inc. 25 * under proprietary terms before Copyright ownership was assigned 26 * to the Linux Foundation. 27 */ 28 29 /** 30 * @file htt.h 31 * 32 * @details the public header file of HTT layer 33 */ 34 35 #ifndef _HTT_H_ 36 #define _HTT_H_ 37 38 #include <htt_deps.h> 39 #include <htt_common.h> 40 41 /* 42 * Unless explicitly specified to use 64 bits to represent physical addresses 43 * (or more precisely, bus addresses), default to 32 bits. 44 */ 45 #ifndef HTT_PADDR64 46 #define HTT_PADDR64 0 47 #endif 48 49 #ifndef offsetof 50 #define offsetof(type, field) ((unsigned int)(&((type *)0)->field)) 51 #endif 52 53 /* 54 * HTT version history: 55 * 1.0 initial numbered version 56 * 1.1 modifications to STATS messages. 57 * These modifications are not backwards compatible, but since the 58 * STATS messages themselves are non-essential (they are for debugging), 59 * the 1.1 version of the HTT message library as a whole is compatible 60 * with the 1.0 version. 61 * 1.2 reset mask IE added to STATS_REQ message 62 * 1.3 stat config IE added to STATS_REQ message 63 *---- 64 * 2.0 FW rx PPDU desc added to RX_IND message 65 * 2.1 Enable msdu_ext/frag_desc banking change for WIFI2.0 66 *---- 67 * 3.0 Remove HTT_H2T_MSG_TYPE_MGMT_TX message 68 * 3.1 Added HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND message 69 * 3.2 Added HTT_H2T_MSG_TYPE_WDI_IPA_CFG, 70 * HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST messages 71 * 3.3 Added HTT_H2T_MSG_TYPE_AGGR_CFG_EX message 72 * 3.4 Added tx_compl_req flag in HTT tx descriptor 73 * 3.5 Added flush and fail stats in rx_reorder stats structure 74 * 3.6 Added frag flag in HTT RX INORDER PADDR IND header 75 * 3.7 Made changes to support EOS Mac_core 3.0 76 * 3.8 Added txq_group information element definition; 77 * added optional txq_group suffix to TX_CREDIT_UPDATE_IND message 78 * 3.9 Added HTT_T2H CHAN_CHANGE message; 79 * Allow buffer addresses in bus-address format to be stored as 80 * either 32 bits or 64 bits. 81 * 3.10 Add optional TLV extensions to the VERSION_REQ and VERSION_CONF 82 * messages to specify which HTT options to use. 83 * Initial TLV options cover: 84 * - whether to use 32 or 64 bits to represent LL bus addresses 85 * - whether to use TX_COMPL_IND or TX_CREDIT_UPDATE_IND in HL systems 86 * - how many tx queue groups to use 87 * 3.11 Expand rx debug stats: 88 * - Expand the rx_reorder_stats struct with stats about successful and 89 * failed rx buffer allcoations. 90 * - Add a new rx_remote_buffer_mgmt_stats struct with stats about 91 * the supply, allocation, use, and recycling of rx buffers for the 92 * "remote ring" of rx buffers in host member in LL systems. 93 * Add RX_REMOTE_RING_BUFFER_INFO stats type for uploading these stats. 94 * 3.12 Add "rx offload packet error" message with initial "MIC error" subtype 95 * 3.13 Add constants + macros to support 64-bit address format for the 96 * tx fragments descriptor, the rx ring buffer, and the rx ring 97 * index shadow register. 98 * 3.14 Add a method for the host to provide detailed per-frame tx specs: 99 * - Add htt_tx_msdu_desc_ext_t struct def. 100 * - Add TLV to specify whether the target supports the HTT tx MSDU 101 * extension descriptor. 102 * - Change a reserved bit in the HTT tx MSDU descriptor to an 103 * "extension" bit, to specify whether a HTT tx MSDU extension 104 * descriptor is present. 105 * 3.15 Add HW rx desc info to per-MSDU info elems in RX_IN_ORD_PADDR_IND msg. 106 * (This allows the host to obtain key information about the MSDU 107 * from a memory location already in the cache, rather than taking a 108 * cache miss for each MSDU by reading the HW rx descs.) 109 * 3.16 Add htt_pkt_type_eth2 and define pkt_subtype flags to indicate 110 * whether a copy-engine classification result is appended to TX_FRM. 111 * 3.17 Add a version of the WDI_IPA_CFG message; add RX_RING2 to WDI_IPA_CFG 112 * 3.18 Add a PEER_DEL tx completion indication status, for HL cleanup of 113 * tx frames in the target after the peer has already been deleted. 114 * 3.19 Add HTT_DBG_STATS_RX_RATE_INFO_V2 and HTT_DBG_STATS_TX_RATE_INFO_V2 115 * 3.20 Expand rx_reorder_stats. 116 * 3.21 Add optional rx channel spec to HL RX_IND. 117 * 3.22 Expand rx_reorder_stats 118 * (distinguish duplicates within vs. outside block ack window) 119 * 3.23 Add HTT_T2H_MSG_TYPE_RATE_REPORT to report peer justified rate. 120 * The justified rate is calculated by two steps. The first is to multiply 121 * user-rate by (1 - PER) and the other is to smooth the step 1's result 122 * by a low pass filter. 123 * This change allows HL download scheduling to consider the WLAN rate 124 * that will be used for transmitting the downloaded frames. 125 * 3.24 Expand rx_reorder_stats 126 * (add counter for decrypt / MIC errors) 127 * 3.25 Expand rx_reorder_stats 128 * (add counter of frames received into both local + remote rings) 129 * 3.26 Add stats struct for counting rx of tx BF, MU, SU, and NDPA frames 130 * (HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT, rx_txbf_musu_ndpa_pkts_stats) 131 * 3.27 Add a new interface for flow-control. The following t2h messages have 132 * been included: HTT_T2H_MSG_TYPE_FLOW_POOL_MAP and 133 * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP 134 * 3.28 Add a new interface for ring interface change. The following two h2t 135 * and one t2h messages have been included: 136 * HTT_H2T_MSG_TYPE_SRING_SETUP, HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 137 * and HTT_T2H_MSG_TYPE_SRING_SETUP_DONE 138 * 3.29 Add definitions of htt_tx_msdu_desc_ext2_t descriptor and other 139 * information elements passed from the host to a Lithium target, 140 * Add definitions of the HTT_H2T ADD_WDS_ENTRY and DELETE_WDS_ENTRY 141 * messages and the HTT_T2H MAP_FLOW_INFO message (for use with Lithium 142 * targets). 143 * 3.30 Add pktlog flag inside HTT_T2H RX_IN_ORD_PADDR_IND message 144 * 3.31 Add HTT_H2T_MSG_TYPE_RFS_CONFIG 145 * 3.32 Add HTT_WDI_IPA_OPCODE_SHARING_STATS, HTT_WDI_IPA_OPCODE_SET_QUOTA and 146 * HTT_WDI_IPA_OPCODE_IND_QUOTA for getting quota and reporting WiFi 147 * sharing stats 148 * 3.33 Add HTT_TX_COMPL_IND_STAT_DROP and HTT_TX_COMPL_IND_STAT_HOST_INSPECT 149 * 3.34 Add HW_PEER_ID field to PEER_MAP 150 * 3.35 Revise bitfield defs of HTT_SRING_SETUP message 151 * (changes are not backwards compatible, but HTT_SRING_SETUP message is 152 * not yet in use) 153 * 3.36 Add HTT_H2T_MSG_TYPE_EXT_STATS_REQ and HTT_T2H_MSG_TYPE_EXT_STATS_CONF 154 * 3.37 Add HTT_PEER_TYPE and htt_mac_addr defs 155 * 3.38 Add holes_no_filled field to rx_reorder_stats 156 * 3.39 Add host_inspected flag to htt_tx_tcl_vdev_metadata 157 * 3.40 Add optional timestamps in the HTT tx completion 158 * 3.41 Add optional tx power spec in the HTT tx completion (for DSRC use) 159 * 3.42 Add PPDU_STATS_CFG + PPDU_STATS_IND 160 * 3.43 Add HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR defs 161 * 3.44 Add htt_tx_wbm_completion_v2 162 * 3.45 Add host_tx_desc_pool flag in htt_tx_msdu_desc_ext2_t 163 * 3.46 Add MAC ID and payload size fields to HTT_T2H_MSG_TYPE_PKTLOG header 164 * 3.47 Add HTT_T2H PEER_MAP_V2 and PEER_UNMAP_V2 165 * 3.48 Add pdev ID field to HTT_T2H_MSG_TYPE_PPDU_STATS_IND and 166 * HTT_T2H_MSG_TYPE_PKTLOG 167 * 3.49 Add HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND def 168 * 3.50 Add learning_frame flag to htt_tx_msdu_desc_ext2_t 169 * 3.51 Add SW peer ID and TID num to HTT TX WBM COMPLETION 170 * 3.52 Add HTT_T2H FLOW_POOL_RESIZE msg def 171 * 3.53 Update HTT_T2H FLOW_POOL_RESIZE msg def 172 * 3.54 Define mcast and mcast_valid flags within htt_tx_wbm_transmit_status 173 * 3.55 Add initiator / responder flags to RX_DELBA indication 174 * 3.56 Fix HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE bit-mask defs 175 * 3.57 Add support for in-band data within HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND 176 * 3.58 Add optional MSDU ack RSSI array to end of HTT_T2H TX_COMPL_IND msg 177 * 3.59 Add HTT_RXDMA_HOST_BUF_RING2 def 178 * 3.60 Add HTT_T2H_MSG_TYPE_PEER_STATS_IND def 179 * 3.61 Add rx offset fields to HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG msg 180 * 3.62 Add antenna mask to reserved space in htt_rx_ppdu_desc_t 181 * 3.63 Add HTT_HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND def 182 * 3.64 Add struct htt_tx_compl_ind_append_tx_tsf64 and add tx_tsf64 183 * array to the end of HTT_T2H TX_COMPL_IND msg 184 * 3.65 Add fields in htt_tx_msdu_desc_ext2_t to allow the host to provide 185 * a "cookie" to identify a MSDU, and to specify to not apply aggregation 186 * for a MSDU. 187 * 3.66 Add HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND msg. 188 * Add PKT_CAPTURE_MODE flag within HTT_T2H TX_I_ORD_PADDR_IND msg. 189 * 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg. 190 * 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP 191 * 3.69 Add htt_ul_ofdma_user_info_v0 defs 192 * 3.70 Add AST1-AST3 fields to HTT_T2H PEER_MAP_V2 msg 193 * 3.71 Add rx offload engine / flow search engine htt setup message defs for 194 * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG, HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG 195 * 3.72 Add tx_retry_cnt fields to htt_tx_offload_deliver_ind_hdr_t and 196 * htt_tx_data_hdr_information 197 * 3.73 Add channel pre-calibration data upload and download messages defs for 198 * HTT_T2H_MSG_TYPE_CHAN_CALDATA and HTT_H2T_MSG_TYPE_CHAN_CALDATA 199 * 3.74 Add HTT_T2H_MSG_TYPE_RX_FISA_CFG msg. 200 * 3.75 Add fp_ndp and mo_ndp flags in HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG. 201 * 3.76 Add HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG msg. 202 * 3.77 Add HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE msg. 203 * 3.78 Add htt_ppdu_id def. 204 * 3.79 Add HTT_NUM_AC_WMM def. 205 * 3.80 Add add WDS_FREE_COUNT bitfield in T2H PEER_UNMAP_V2 msg. 206 * 3.81 Add ppdu_start_tsf field in HTT_TX_WBM_COMPLETION_V2. 207 * 3.82 Add WIN_SIZE field to HTT_T2H_MSG_TYPE_RX_DELBA msg. 208 * 3.83 Shrink seq_idx field in HTT PPDU ID from 3 bits to 2. 209 * 3.84 Add fisa_control_bits_v2 def. 210 * 3.85 Add HTT_RX_PEER_META_DATA defs. 211 * 3.86 Add HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND def. 212 * 3.87 Add on-chip AST index field to PEER_MAP_V2 msg. 213 * 3.88 Add HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE def. 214 * 3.89 Add MSDU queue enumerations. 215 * 3.90 Add HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND def. 216 * 3.91 Add HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP, _UNMAP defs. 217 * 3.92 Add HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG def. 218 * 3.93 Add HTT_T2H_MSG_TYPE_PEER_MAP_V3 def. 219 * 3.94 Add HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG, 220 * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND defs. 221 * 3.95 Add HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def. 222 * 3.96 Modify HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def. 223 * 3.97 Add tx MSDU drop byte count fields in vdev_txrx_stats_hw_stats TLV. 224 * 3.98 Add htt_tx_tcl_metadata_v2 def. 225 * 3.99 Add HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ, _UNMAP_REQ, _MAP_REPORT_REQ and 226 * HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF defs. 227 * 3.100 Add htt_tx_wbm_completion_v3 def. 228 * 3.101 Add HTT_UL_OFDMA_USER_INFO_V1_BITMAP defs. 229 * 3.102 Add HTT_H2T_MSG_TYPE_MSI_SETUP def. 230 * 3.103 Add HTT_T2H_SAWF_MSDUQ_INFO_IND defs. 231 * 3.104 Add mgmt/ctrl/data specs in rx ring cfg. 232 * 3.105 Add HTT_H2T STREAMING_STATS_REQ + HTT_T2H STREAMING_STATS_IND defs. 233 * 3.106 Add HTT_T2H_PPDU_ID_FMT_IND def. 234 * 3.107 Add traffic_end_indication bitfield in htt_tx_msdu_desc_ext2_t. 235 * 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def. 236 * 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs. 237 * 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t. 238 * 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg. 239 * 3.112 Add logical_link_id field in rx_peer_metadata_v1. 240 * 3.113 Add add rx msdu,mpdu,ppdu fields in rx_ring_selection_cfg_t 241 * 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def. 242 * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and 243 * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. 244 * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. 245 * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. 246 * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. 247 * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. 248 * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. 249 * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. 250 * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg 251 * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. 252 * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. 253 * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. 254 * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def. 255 * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs. 256 * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND 257 * msg defs. 258 * 3.129 Add HTT_TX_FW2WBM_REINJECT_REASON_SAWF_SVC_CLASS_ID_ABSENT def. 259 * 3.130 Add H2T TX_LCE_SUPER_RULE_SETUP and T2H TX_LCE_SUPER_RULE_SETUP_DONE 260 * msg defs. 261 * 3.131 Add H2T TYPE_MSDUQ_RECFG_REQ + T2H MSDUQ_CFG_IND msg defs. 262 * 3.132 Add flow_classification_3_tuple_field_enable in H2T 3_TUPLE_HASH_CFG. 263 * 3.133 Add packet_type_enable_data_flags fields in rx_ring_selection_cfg. 264 * 3.134 Add qdata_refill flag in rx_peer_metadata_v1a. 265 * 3.135 Add HTT_HOST4_TO_FW_RXBUF_RING def. 266 */ 267 #define HTT_CURRENT_VERSION_MAJOR 3 268 #define HTT_CURRENT_VERSION_MINOR 135 269 270 #define HTT_NUM_TX_FRAG_DESC 1024 271 272 #define HTT_WIFI_IP_VERSION(x,y) ((x) == (y)) 273 274 #define HTT_CHECK_SET_VAL(field, val) \ 275 A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S)))) 276 277 /* macros to assist in sign-extending fields from HTT messages */ 278 #define HTT_SIGN_BIT_MASK(field) \ 279 ((field ## _M + (1 << field ## _S)) >> 1) 280 #define HTT_SIGN_BIT(_val, field) \ 281 (_val & HTT_SIGN_BIT_MASK(field)) 282 #define HTT_SIGN_BIT_UNSHIFTED(_val, field) \ 283 (HTT_SIGN_BIT(_val, field) >> field ## _S) 284 #define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \ 285 (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1) 286 #define HTT_SIGN_BIT_EXTENSION(_val, field) \ 287 (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \ 288 HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field))) 289 #define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \ 290 (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S)) 291 292 293 /* 294 * TEMPORARY: 295 * Provide HTT_H2T_MSG_TYPE_MGMT_TX as an alias for 296 * DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX until all code 297 * that refers to HTT_H2T_MSG_TYPE_MGMT_TX has been 298 * updated. 299 */ 300 #define HTT_H2T_MSG_TYPE_MGMT_TX DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX 301 302 /* 303 * TEMPORARY: 304 * Provide HTT_T2H_MSG_TYPE_RC_UPDATE_IND as an alias for 305 * DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND until all code 306 * that refers to HTT_T2H_MSG_TYPE_RC_UPDATE_IND has been 307 * updated. 308 */ 309 #define HTT_T2H_MSG_TYPE_RC_UPDATE_IND DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND 310 311 /** 312 * htt_dbg_stats_type - 313 * bit positions for each stats type within a stats type bitmask 314 * The bitmask contains 24 bits. 315 */ 316 enum htt_dbg_stats_type { 317 HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */ 318 HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */ 319 HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */ 320 HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */ 321 HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */ 322 HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */ 323 HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */ 324 HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */ 325 HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */ 326 HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */ 327 HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */ 328 HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */ 329 HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000 */ 330 HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */ 331 HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */ 332 HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */ 333 /* bits 16-23 currently reserved */ 334 335 /* keep this last */ 336 HTT_DBG_NUM_STATS 337 }; 338 339 /*=== HTT option selection TLVs === 340 * Certain HTT messages have alternatives or options. 341 * For such cases, the host and target need to agree on which option to use. 342 * Option specification TLVs can be appended to the VERSION_REQ and 343 * VERSION_CONF messages to select options other than the default. 344 * These TLVs are entirely optional - if they are not provided, there is a 345 * well-defined default for each option. If they are provided, they can be 346 * provided in any order. Each TLV can be present or absent independent of 347 * the presence / absence of other TLVs. 348 * 349 * The HTT option selection TLVs use the following format: 350 * |31 16|15 8|7 0| 351 * |---------------------------------+----------------+----------------| 352 * | value (payload) | length | tag | 353 * |-------------------------------------------------------------------| 354 * The value portion need not be only 2 bytes; it can be extended by any 355 * integer number of 4-byte units. The total length of the TLV, including 356 * the tag and length fields, must be a multiple of 4 bytes. The length 357 * field specifies the total TLV size in 4-byte units. Thus, the typical 358 * TLV, with a 1-byte tag field, a 1-byte length field, and a 2-byte value 359 * field, would store 0x1 in its length field, to show that the TLV occupies 360 * a single 4-byte unit. 361 */ 362 363 /*--- TLV header format - applies to all HTT option TLVs ---*/ 364 365 enum HTT_OPTION_TLV_TAGS { 366 HTT_OPTION_TLV_TAG_RESERVED0 = 0x0, 367 HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1, 368 HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2, 369 HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3, 370 HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4, 371 /* TCL_METADATA_VER: added to support V2 and higher of the TCL Data Cmd */ 372 HTT_OPTION_TLV_TAG_TCL_METADATA_VER = 0x5, 373 }; 374 375 #define HTT_TCL_METADATA_VER_SZ 4 376 377 PREPACK struct htt_option_tlv_header_t { 378 A_UINT8 tag; 379 A_UINT8 length; 380 } POSTPACK; 381 382 #define HTT_OPTION_TLV_TAG_M 0x000000ff 383 #define HTT_OPTION_TLV_TAG_S 0 384 #define HTT_OPTION_TLV_LENGTH_M 0x0000ff00 385 #define HTT_OPTION_TLV_LENGTH_S 8 386 /* 387 * value0 - 16 bit value field stored in word0 388 * The TLV's value field may be longer than 2 bytes, in which case 389 * the remainder of the value is stored in word1, word2, etc. 390 */ 391 #define HTT_OPTION_TLV_VALUE0_M 0xffff0000 392 #define HTT_OPTION_TLV_VALUE0_S 16 393 394 #define HTT_OPTION_TLV_TAG_SET(word, tag) \ 395 do { \ 396 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \ 397 (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \ 398 } while (0) 399 #define HTT_OPTION_TLV_TAG_GET(word) \ 400 (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S) 401 402 #define HTT_OPTION_TLV_LENGTH_SET(word, tag) \ 403 do { \ 404 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \ 405 (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \ 406 } while (0) 407 #define HTT_OPTION_TLV_LENGTH_GET(word) \ 408 (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S) 409 410 #define HTT_OPTION_TLV_VALUE0_SET(word, tag) \ 411 do { \ 412 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \ 413 (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \ 414 } while (0) 415 #define HTT_OPTION_TLV_VALUE0_GET(word) \ 416 (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S) 417 418 /*--- format of specific HTT option TLVs ---*/ 419 420 /* 421 * HTT option TLV for specifying LL bus address size 422 * Some chips require bus addresses used by the target to access buffers 423 * within the host's memory to be 32 bits; others require bus addresses 424 * used by the target to access buffers within the host's memory to be 425 * 64 bits. 426 * The LL_BUS_ADDR_SIZE TLV can be sent from the target to the host as 427 * a suffix to the VERSION_CONF message to specify which bus address format 428 * the target requires. 429 * If this LL_BUS_ADDR_SIZE TLV is not sent by the target, the host should 430 * default to providing bus addresses to the target in 32-bit format. 431 */ 432 enum HTT_OPTION_TLV_LL_BUS_ADDR_SIZE_VALUES { 433 HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0, 434 HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1, 435 }; 436 PREPACK struct htt_option_tlv_ll_bus_addr_size_t { 437 struct htt_option_tlv_header_t hdr; 438 A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */ 439 } POSTPACK; 440 441 /* 442 * HTT option TLV for specifying whether HL systems should indicate 443 * over-the-air tx completion for individual frames, or should instead 444 * send a bulk TX_CREDIT_UPDATE_IND except when the host explicitly 445 * requests an OTA tx completion for a particular tx frame. 446 * This option does not apply to LL systems, where the TX_COMPL_IND 447 * is mandatory. 448 * This option is primarily intended for HL systems in which the tx frame 449 * downloads over the host --> target bus are as slow as or slower than 450 * the transmissions over the WLAN PHY. For cases where the bus is faster 451 * than the WLAN PHY, the target will transmit relatively large A-MPDUs, 452 * and consequently will send one TX_COMPL_IND message that covers several 453 * tx frames. For cases where the WLAN PHY is faster than the bus, 454 * the target will end up transmitting very short A-MPDUs, and consequently 455 * sending many TX_COMPL_IND messages, which each cover a very small number 456 * of tx frames. 457 * The HL_SUPPRESS_TX_COMPL_IND TLV can be sent by the host to the target as 458 * a suffix to the VERSION_REQ message to request whether the host desires to 459 * use TX_CREDIT_UPDATE_IND rather than TX_COMPL_IND. The target can then 460 * send a HTT_SUPPRESS_TX_COMPL_IND TLV to the host as a suffix to the 461 * VERSION_CONF message to confirm whether TX_CREDIT_UPDATE_IND will be used 462 * rather than TX_COMPL_IND. TX_CREDIT_UPDATE_IND shall only be used if the 463 * host sends a HL_SUPPRESS_TX_COMPL_IND TLV requesting use of 464 * TX_CREDIT_UPDATE_IND, and the target sends a HL_SUPPRESS_TX_COMPLE_IND TLV 465 * back to the host confirming use of TX_CREDIT_UPDATE_IND. 466 * Lack of a HL_SUPPRESS_TX_COMPL_IND TLV from either host --> target or 467 * target --> host is equivalent to a HL_SUPPRESS_TX_COMPL_IND that 468 * explicitly specifies HL_ALLOW_TX_COMPL_IND in the value payload of the 469 * TLV. 470 */ 471 enum HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND_VALUES { 472 HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0, 473 HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1, 474 }; 475 PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t { 476 struct htt_option_tlv_header_t hdr; 477 A_UINT16 hl_suppress_tx_compl_ind; /* HL_SUPPRESS_TX_COMPL_IND enum */ 478 } POSTPACK; 479 480 /* 481 * HTT option TLV for specifying how many tx queue groups the target 482 * may establish. 483 * This TLV specifies the maximum value the target may send in the 484 * txq_group_id field of any TXQ_GROUP information elements sent by 485 * the target to the host. This allows the host to pre-allocate an 486 * appropriate number of tx queue group structs. 487 * 488 * The MAX_TX_QUEUE_GROUPS_TLV can be sent from the host to the target as 489 * a suffix to the VERSION_REQ message to specify whether the host supports 490 * tx queue groups at all, and if so if there is any limit on the number of 491 * tx queue groups that the host supports. 492 * The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as 493 * a suffix to the VERSION_CONF message. If the host has specified in the 494 * VER_REQ message a limit on the number of tx queue groups the host can 495 * support, the target shall limit its specification of the maximum tx groups 496 * to be no larger than this host-specified limit. 497 * 498 * If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host 499 * shall preallocate 4 tx queue group structs, and the target shall not 500 * specify a txq_group_id larger than 3. 501 */ 502 enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES { 503 HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0, 504 /* 505 * values 1 through N specify the max number of tx queue groups 506 * the sender supports 507 */ 508 HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff, 509 }; 510 /* TEMPORARY backwards-compatibility alias for a typo fix - 511 * The htt_option_tlv_mac_tx_queue_groups_t typo has been corrected 512 * to htt_option_tlv_max_tx_queue_groups_t, but an alias is provided 513 * to support the old name (with the typo) until all references to the 514 * old name are replaced with the new name. 515 */ 516 #define htt_option_tlv_mac_tx_queue_groups_t htt_option_tlv_max_tx_queue_groups_t 517 PREPACK struct htt_option_tlv_max_tx_queue_groups_t { 518 struct htt_option_tlv_header_t hdr; 519 A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */ 520 } POSTPACK; 521 522 /* 523 * HTT option TLV for specifying whether the target supports an extended 524 * version of the HTT tx descriptor. If the target provides this TLV 525 * and specifies in the TLV that the target supports an extended version 526 * of the HTT tx descriptor, the target must check the "extension" bit in 527 * the HTT tx descriptor, and if the extension bit is set, to expect a 528 * HTT tx MSDU extension descriptor immediately following the HTT tx MSDU 529 * descriptor. Furthermore, the target must provide room for the HTT 530 * tx MSDU extension descriptor in the target's TX_FRM buffer. 531 * This option is intended for systems where the host needs to explicitly 532 * control the transmission parameters such as tx power for individual 533 * tx frames. 534 * The SUPPORT_TX_MSDU_DESC_EXT TLB can be sent by the target to the host 535 * as a suffix to the VERSION_CONF message to explicitly specify whether 536 * the target supports the HTT tx MSDU extension descriptor. 537 * Lack of a SUPPORT_TX_MSDU_DESC_EXT from the target shall be interpreted 538 * by the host as lack of target support for the HTT tx MSDU extension 539 * descriptor; the host shall provide HTT tx MSDU extension descriptors in 540 * the HTT_H2T TX_FRM messages only if the target indicates it supports 541 * the HTT tx MSDU extension descriptor. 542 * The host is not required to provide the HTT tx MSDU extension descriptor 543 * just because the target supports it; the target must check the 544 * "extension" bit in the HTT tx MSDU descriptor to determine whether an 545 * extension descriptor is present. 546 */ 547 enum HTT_OPTION_TLV_SUPPORT_TX_MSDU_DESC_EXT_VALUES { 548 HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0, 549 HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1, 550 }; 551 PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { 552 struct htt_option_tlv_header_t hdr; 553 A_UINT16 tx_msdu_desc_ext_support; /* SUPPORT_TX_MSDU_DESC_EXT enum */ 554 } POSTPACK; 555 556 /* 557 * For the tcl data command V2 and higher support added a new 558 * version tag HTT_OPTION_TLV_TAG_TCL_METADATA_VER. 559 * This will be used as a TLV in HTT_H2T_MSG_TYPE_VERSION_REQ and 560 * HTT_T2H_MSG_TYPE_VERSION_CONF. 561 * HTT option TLV for specifying which version of the TCL metadata struct 562 * should be used: 563 * V1 -> use htt_tx_tcl_metadata struct 564 * V2 -> use htt_tx_tcl_metadata_v2 struct 565 * Old FW will only support V1. 566 * New FW will support V2. New FW will still support V1, at least during 567 * a transition period. 568 * Similarly, old host will only support V1, and new host will support V1 + V2. 569 * 570 * The host can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the 571 * HTT_H2T_MSG_TYPE_VERSION_REQ to indicate to the target which version(s) 572 * of TCL metadata the host supports. If the host doesn't provide a 573 * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_REQ message, it 574 * is implicitly understood that the host only supports V1. 575 * The target can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the 576 * HTT_T2H_MSG_TYPE_VERSION_CONF to indicate which version of TCL metadata 577 * the host shall use. The target shall only select one of the versions 578 * supported by the host. If the target doesn't provide a 579 * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it 580 * is implicitly understood that the V1 TCL metadata shall be used. 581 * 582 * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21 583 * read as version 2.1. We added support for Dynamic AST Index Allocation 584 * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2 585 * we will retain older behavior of making sure the AST Index for SAWF 586 * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1 587 * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and 588 * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index 589 * in TCLV2 command and do the dynamic AST allocations. 590 */ 591 enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { 592 HTT_OPTION_TLV_TCL_METADATA_V1 = 1, 593 HTT_OPTION_TLV_TCL_METADATA_V2 = 2, 594 /* values 3-20 reserved */ 595 HTT_OPTION_TLV_TCL_METADATA_V21 = 21, 596 }; 597 598 PREPACK struct htt_option_tlv_tcl_metadata_ver_t { 599 struct htt_option_tlv_header_t hdr; 600 A_UINT16 tcl_metadata_ver; /* TCL_METADATA_VER_VALUES enum */ 601 } POSTPACK; 602 603 #define HTT_OPTION_TLV_TCL_METADATA_VER_SET(word, value) \ 604 HTT_OPTION_TLV_VALUE0_SET(word, value) 605 #define HTT_OPTION_TLV_TCL_METADATA_VER_GET(word) \ 606 HTT_OPTION_TLV_VALUE0_GET(word) 607 608 typedef struct { 609 union { 610 /* BIT [11 : 0] :- tag 611 * BIT [23 : 12] :- length 612 * BIT [31 : 24] :- reserved 613 */ 614 A_UINT32 tag__length; 615 /* 616 * The following struct is not endian-portable. 617 * It is suitable for use within the target, which is known to be 618 * little-endian. 619 * The host should use the above endian-portable macros to access 620 * the tag and length bitfields in an endian-neutral manner. 621 */ 622 struct { 623 A_UINT32 tag : 12, /* BIT [11 : 0] */ 624 length : 12, /* BIT [23 : 12] */ 625 reserved : 8; /* BIT [31 : 24] */ 626 }; 627 }; 628 } htt_tlv_hdr_t; 629 630 /** HTT stats TLV tag values */ 631 typedef enum { 632 HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */ 633 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */ 634 HTT_STATS_TX_PDEV_SIFS_TAG = 2, /* htt_tx_pdev_stats_sifs_tlv_v */ 635 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, /* htt_tx_pdev_stats_flush_tlv_v */ 636 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, /* htt_tx_pdev_stats_phy_err_tlv_v */ 637 HTT_STATS_STRING_TAG = 5, /* htt_stats_string_tlv, PUBLISH_FUNC=get_sring_name_data */ 638 HTT_STATS_TX_HWQ_CMN_TAG = 6, /* htt_tx_hwq_stats_cmn_tlv, PUBLISH_CODE=#inbound_req->tx_hwq_id_mac_id_word = ((htt_tx_hwq_stats_cmn_tlv *)tag_buf)->mac_id__hwq_id__word;#, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 639 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, /* htt_tx_hwq_difs_latency_stats_tlv_v */ 640 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, /* htt_tx_hwq_cmd_result_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 641 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, /* htt_tx_hwq_cmd_stall_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 642 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, /* htt_tx_hwq_fes_result_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 643 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, /* htt_tx_tqm_gen_mpdu_stats_tlv_v */ 644 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, /* htt_tx_tqm_list_mpdu_stats_tlv_v */ 645 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, /* htt_tx_tqm_list_mpdu_cnt_tlv_v */ 646 HTT_STATS_TX_TQM_CMN_TAG = 14, /* htt_tx_tqm_cmn_stats_tlv */ 647 HTT_STATS_TX_TQM_PDEV_TAG = 15, /* htt_tx_tqm_pdev_stats_tlv_v */ 648 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, /* htt_tx_tqm_cmdq_status_tlv */ 649 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, /* htt_tx_de_eapol_packets_stats_tlv */ 650 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, /* htt_tx_de_classify_failed_stats_tlv */ 651 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, /* htt_tx_de_classify_stats_tlv */ 652 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, /* htt_tx_de_classify_status_stats_tlv */ 653 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, /* htt_tx_de_enqueue_packets_stats_tlv */ 654 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, /* htt_tx_de_enqueue_discard_stats_tlv */ 655 HTT_STATS_TX_DE_CMN_TAG = 23, /* htt_tx_de_cmn_stats_tlv */ 656 HTT_STATS_RING_IF_TAG = 24, /* htt_ring_if_stats_tlv */ 657 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, /* htt_tx_pdev_mu_mimo_sch_stats_tlv */ 658 HTT_STATS_SFM_CMN_TAG = 26, /* htt_sfm_cmn_tlv */ 659 HTT_STATS_SRING_STATS_TAG = 27, /* htt_sring_stats_tlv, PUBLISH_FUNC=create_json_response_for_sring_stats */ 660 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, /* htt_rx_pdev_fw_stats_tlv */ 661 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, /* htt_rx_pdev_fw_ring_mpdu_err_tlv_v */ 662 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, /* htt_rx_pdev_fw_mpdu_drop_tlv_v */ 663 HTT_STATS_RX_SOC_FW_STATS_TAG = 31, /* htt_rx_soc_fw_stats_tlv */ 664 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, /* htt_rx_soc_fw_refill_ring_empty_tlv_v */ 665 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, /* htt_rx_soc_fw_refill_ring_num_refill_tlv_v */ 666 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, /* htt_tx_pdev_rate_stats_tlv */ 667 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, /* htt_rx_pdev_rate_stats_tlv */ 668 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, /* htt_tx_pdev_stats_sched_per_txq_tlv, PUBLISH_CODE=#inbound_req->tx_sched_txq_id_mac_id_word = ((htt_tx_pdev_stats_sched_per_txq_tlv *)tag_buf)->mac_id__txq_id__word;#, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 669 HTT_STATS_TX_SCHED_CMN_TAG = 37, /* htt_stats_tx_sched_cmn_tlv, PUBLISH_SKIP */ 670 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, /* htt_tx_pdev_mu_mimo_mpdu_stats_tlv */ 671 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, /* htt_sched_txq_cmd_posted_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 672 HTT_STATS_RING_IF_CMN_TAG = 40, /* htt_ring_if_cmn_tlv */ 673 HTT_STATS_SFM_CLIENT_USER_TAG = 41, /* htt_sfm_client_user_tlv_v, PUBLISH_FUNC=create_json_response_for_sfm_client */ 674 HTT_STATS_SFM_CLIENT_TAG = 42, /* htt_sfm_client_tlv, PUBLISH_FUNC=create_json_response_for_sfm_client */ 675 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, /* htt_tx_tqm_error_stats_tlv */ 676 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, /* htt_sched_txq_cmd_reaped_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 677 HTT_STATS_SRING_CMN_TAG = 45, /* htt_sring_cmn_tlv */ 678 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, /* htt_tx_selfgen_ac_err_stats_tlv */ 679 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, /* htt_tx_selfgen_cmn_stats_tlv */ 680 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, /* htt_tx_selfgen_ac_stats_tlv */ 681 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, /* htt_tx_selfgen_ax_stats_tlv */ 682 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, /* htt_tx_selfgen_ax_err_stats_tlv */ 683 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, /* htt_tx_hwq_mu_mimo_sch_stats_tlv */ 684 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, /* htt_tx_hwq_mu_mimo_mpdu_stats_tlv */ 685 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, /* htt_tx_hwq_mu_mimo_cmn_stats_tlv */ 686 HTT_STATS_HW_INTR_MISC_TAG = 54, /* htt_hw_stats_intr_misc_tlv, PUBLISH_FUNC=create_json_response_for_hwstats_intr_misc */ 687 HTT_STATS_HW_WD_TIMEOUT_TAG = 55, /* htt_hw_stats_wd_timeout_tlv */ 688 HTT_STATS_HW_PDEV_ERRS_TAG = 56, /* htt_hw_stats_pdev_errs_tlv */ 689 HTT_STATS_COUNTER_NAME_TAG = 57, /* htt_counter_tlv */ 690 HTT_STATS_TX_TID_DETAILS_TAG = 58, /* htt_tx_tid_stats_tlv */ 691 HTT_STATS_RX_TID_DETAILS_TAG = 59, /* htt_rx_tid_stats_tlv */ 692 HTT_STATS_PEER_STATS_CMN_TAG = 60, /* htt_peer_stats_cmn_tlv */ 693 HTT_STATS_PEER_DETAILS_TAG = 61, /* htt_peer_details_tlv */ 694 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, /* htt_tx_peer_rate_stats_tlv */ 695 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, /* htt_rx_peer_rate_stats_tlv, TOPIC=advanced */ 696 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, /* htt_msdu_flow_stats_tlv */ 697 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, /* htt_tx_de_compl_stats_tlv */ 698 HTT_STATS_WHAL_TX_TAG = 66, /* htt_hw_stats_whal_tx_tlv */ 699 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, /* htt_tx_pdev_stats_sifs_hist_tlv_v */ 700 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, /* htt_rx_pdev_fw_stats_phy_err_tlv */ 701 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, /* htt_tx_tid_stats_v1_tlv */ 702 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, /* htt_pdev_cca_stats_hist_tlv (for 1 sec interval stats), PUBLISH_FUNC=update_htt_pdev_cca_stat_context */ 703 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, /* htt_pdev_cca_stats_hist_tlv (for 100 msec interval stats), PUBLISH_FUNC=update_htt_pdev_cca_stat_context */ 704 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, /* htt_pdev_stats_cca_stats_tlv, PUBLISH_FUNC=update_htt_pdev_cca_stat_context */ 705 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, /* htt_pdev_stats_cca_counters_tlv, PUBLISH_FUNC=create_json_response_for_htt_pdev_cca_stat */ 706 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, /* htt_tx_pdev_mpdu_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_tx_pdev_mpdu_stat */ 707 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, /* htt_pdev_stats_twt_sessions_tlv */ 708 HTT_STATS_PDEV_TWT_SESSION_TAG = 76, /* htt_pdev_stats_twt_session_tlv */ 709 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, /* htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v */ 710 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, /* htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v */ 711 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, /* htt_rx_reo_debug_stats_tlv_v */ 712 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, /* htt_tx_sounding_stats_tlv */ 713 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, /* htt_tx_pdev_stats_tx_ppdu_stats_tlv_v */ 714 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, /* htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v */ 715 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, /* htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v */ 716 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, /* htt_tx_hwq_txop_used_cnt_hist_tlv_v */ 717 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, /* htt_tx_de_fw2wbm_ring_full_hist_tlv */ 718 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, /* htt_sched_txq_sched_order_su_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 719 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, /* htt_sched_txq_sched_eligibility_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 720 HTT_STATS_PDEV_OBSS_PD_TAG = 88, /* htt_pdev_obss_pd_stats_tlv */ 721 HTT_STATS_HW_WAR_TAG = 89, /* htt_hw_war_stats_tlv */ 722 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, /* htt_ring_backpressure_stats_tlv, PUBLISH_FUNC=create_json_response_for_ring_bkp_pressure_stats */ 723 HTT_STATS_LATENCY_PROF_STATS_TAG = 91, /* htt_latency_prof_stats_tlv, PUBLISH_FUNC=create_json_response_for_latency_prof_stats */ 724 HTT_STATS_LATENCY_CTX_TAG = 92, /* htt_latency_prof_ctx_tlv */ 725 HTT_STATS_LATENCY_CNT_TAG = 93, /* htt_latency_prof_cnt_tlv */ 726 HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, /* htt_rx_pdev_ul_trigger_stats_tlv */ 727 HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, /* htt_rx_pdev_ul_ofdma_user_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_rx_pdev_ul_ofdma_user_stat */ 728 HTT_STATS_RX_PDEV_UL_MIMO_USER_STATS_TAG = 96, /* htt_rx_pdev_ul_mimo_user_stats_tlv */ 729 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, /* htt_rx_pdev_ul_mumimo_trig_stats_tlv */ 730 HTT_STATS_RX_FSE_STATS_TAG = 98, /* htt_rx_fse_stats_tlv */ 731 HTT_STATS_PEER_SCHED_STATS_TAG = 99, /* htt_peer_sched_stats_tlv, TOPIC=peer */ 732 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, /* htt_sched_txq_supercycle_triggers_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 733 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, /* htt_peer_ctrl_path_txrx_stats_tlv */ 734 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, /* htt_pdev_ctrl_path_tx_stats_tlv */ 735 HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, /* htt_rx_pdev_rate_ext_stats_tlv, PUBLISH_FUNC=create_json_response_for_rx_pdev_rate_ext */ 736 HTT_STATS_TX_PDEV_DL_MU_MIMO_STATS_TAG = 104, /* htt_tx_pdev_dl_mu_mimo_sch_stats_tlv */ 737 HTT_STATS_TX_PDEV_UL_MU_MIMO_STATS_TAG = 105, /* htt_tx_pdev_ul_mu_mimo_sch_stats_tlv */ 738 HTT_STATS_TX_PDEV_DL_MU_OFDMA_STATS_TAG = 106, /* htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv */ 739 HTT_STATS_TX_PDEV_UL_MU_OFDMA_STATS_TAG = 107, /* htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv */ 740 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, /* htt_tx_peer_rate_txbf_stats_tlv */ 741 HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG = 109, /* htt_stats_error_tlv_v */ 742 HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG = 110, /* htt_stats_error_tlv_v */ 743 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, /* htt_tx_selfgen_ac_sched_status_stats_tlv */ 744 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, /* htt_tx_selfgen_ax_sched_status_stats_tlv */ 745 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, /* htt_txbf_ofdma_ndpa_stats_tlv - DEPRECATED */ 746 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, /* htt_txbf_ofdma_ndp_stats_tlv - DEPRECATED */ 747 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, /* htt_txbf_ofdma_brp_stats_tlv - DEPRECATED */ 748 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, /* htt_txbf_ofdma_steer_stats_tlv - DEPRECATED */ 749 HTT_STATS_STA_UL_OFDMA_STATS_TAG = 117, /* htt_sta_ul_ofdma_stats_tlv */ 750 HTT_STATS_VDEV_RTT_RESP_STATS_TAG = 118, /* htt_vdev_rtt_resp_stats_tlv */ 751 HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG = 119, /* htt_pktlog_and_htt_ring_stats_tlv */ 752 HTT_STATS_DLPAGER_STATS_TAG = 120, /* htt_dlpager_stats_tlv */ 753 HTT_STATS_PHY_COUNTERS_TAG = 121, /* htt_phy_counters_tlv */ 754 HTT_STATS_PHY_STATS_TAG = 122, /* htt_phy_stats_tlv */ 755 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, /* htt_phy_reset_counters_tlv */ 756 HTT_STATS_PHY_RESET_STATS_TAG = 124, /* htt_phy_reset_stats_tlv */ 757 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, /* htt_t2h_soc_txrx_stats_common_tlv */ 758 HTT_STATS_VDEV_TXRX_STATS_HW_STATS_TAG = 126, /* htt_t2h_vdev_txrx_stats_hw_stats_tlv */ 759 HTT_STATS_VDEV_RTT_INIT_STATS_TAG = 127, /* htt_vdev_rtt_init_stats_tlv */ 760 HTT_STATS_PER_RATE_STATS_TAG = 128, /* htt_tx_rate_stats_per_tlv, PUBLISH_FUNC=create_json_response_for_htt_tx_rate_stats_per */ 761 HTT_STATS_MU_PPDU_DIST_TAG = 129, /* htt_pdev_mu_ppdu_dist_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_mu_ppdu */ 762 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, /* htt_tx_pdev_mumimo_grp_stats_tlv */ 763 HTT_STATS_TX_PDEV_BE_RATE_STATS_TAG = 131, /* htt_tx_pdev_rate_stats_be_tlv, TOPIC=advanced */ 764 HTT_STATS_AST_ENTRY_TAG = 132, /* htt_ast_entry_tlv */ 765 HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG = 133, /* htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ 766 HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG = 134, /* htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ 767 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, /* htt_tx_pdev_rate_stats_be_ofdma_tlv */ 768 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG = 136, /* htt_rx_pdev_ul_mumimo_trig_be_stats_tlv, TOPIC=advanced */ 769 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv, TOPIC=advanced */ 770 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv, TOPIC=advanced */ 771 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, /* htt_tx_selfgen_be_sched_status_stats_tlv, TOPIC=advanced */ 772 HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */ 773 HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ 774 HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */ 775 HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv, TOPIC=advanced */ 776 HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, /* htt_tx_pdev_rate_stats_sawf_tlv, TOPIC=advanced */ 777 HTT_STATS_STRM_GEN_MPDUS_TAG = 145, /* htt_stats_strm_gen_mpdus_tlv_t */ 778 HTT_STATS_STRM_GEN_MPDUS_DETAILS_TAG = 146, /* htt_stats_strm_gen_mpdus_details_tlv_t */ 779 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, /* htt_txbf_ofdma_ax_ndpa_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 780 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, /* htt_txbf_ofdma_ax_ndp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 781 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, /* htt_txbf_ofdma_ax_brp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 782 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, /* htt_txbf_ofdma_ax_steer_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 783 HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG = 151, /* htt_txbf_ofdma_be_ndpa_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 784 HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG = 152, /* htt_txbf_ofdma_be_ndp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 785 HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG = 153, /* htt_txbf_ofdma_be_brp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 786 HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG = 154, /* htt_txbf_ofdma_be_steer_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 787 HTT_STATS_DMAC_RESET_STATS_TAG = 155, /* htt_dmac_reset_stats_tlv */ 788 HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG = 156, /* htt_rx_pdev_be_ul_ofdma_user_stats_tlv, TOPIC=advanced */ 789 HTT_STATS_PHY_TPC_STATS_TAG = 157, /* htt_phy_tpc_stats_tlv */ 790 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, /* htt_pdev_puncture_stats_tlv */ 791 HTT_STATS_ML_PEER_DETAILS_TAG = 159, /* htt_ml_peer_details_tlv */ 792 HTT_STATS_ML_PEER_EXT_DETAILS_TAG = 160, /* htt_ml_peer_ext_details_tlv */ 793 HTT_STATS_ML_LINK_INFO_DETAILS_TAG = 161, /* htt_ml_link_info_tlv */ 794 HTT_STATS_TX_PDEV_PPDU_DUR_TAG = 162, /* htt_tx_pdev_ppdu_dur_stats_tlv, TOPIC=advanced */ 795 HTT_STATS_RX_PDEV_PPDU_DUR_TAG = 163, /* htt_rx_pdev_ppdu_dur_stats_tlv, TOPIC=advanced */ 796 HTT_STATS_ODD_PDEV_MANDATORY_TAG = 164, /* htt_odd_mandatory_pdev_stats_tlv */ 797 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, /* htt_pdev_sched_algo_ofdma_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_pdev_sched_algo_ofdma_stats */ 798 HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, /* htt_odd_mandatory_mumimo_pdev_stats_tlv */ 799 HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, /* htt_odd_mandatory_muofdma_pdev_stats_tlv */ 800 HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv - DEPRECATED */ 801 HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v - DEPRECATED */ 802 HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */ 803 HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v, TOPIC=advanced */ 804 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv, TOPIC=advanced */ 805 HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv, TOPIC=advanced */ 806 HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */ 807 HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v, TOPIC=advanced */ 808 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ 809 HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ 810 HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ 811 HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ 812 HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */ 813 HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */ 814 HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */ 815 HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */ 816 HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */ 817 HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ 818 HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ 819 HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */ 820 HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */ 821 HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */ 822 HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */ 823 HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */ 824 HTT_STATS_WHAL_WSI_TAG = 192, /* htt_stats_whal_wsi_tlv */ 825 HTT_STATS_LATENCY_PROF_CAL_DATA_TAG = 193, /* htt_stats_latency_prof_cal_data_tlv */ 826 HTT_STATS_PDEV_RTT_RESP_STATS_TAG = 194, /* htt_stats_pdev_rtt_resp_stats_tlv */ 827 HTT_STATS_PDEV_RTT_INIT_STATS_TAG = 195, /* htt_stats_pdev_rtt_init_stats_tlv */ 828 HTT_STATS_PDEV_RTT_HW_STATS_TAG = 196, /* htt_stats_pdev_rtt_hw_stats_tlv */ 829 HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG = 197, /* htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv */ 830 HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG = 198, /* htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv */ 831 HTT_STATS_GTX_TAG = 199, /* htt_stats_gtx_tlv */ 832 HTT_STATS_TX_PDEV_WIFI_RADAR_TAG = 200, /* htt_stats_tx_pdev_wifi_radar_tlv */ 833 HTT_STATS_TXBF_OFDMA_BE_PARBW_TAG = 201, /* htt_stats_txbf_ofdma_be_parbw_tlv */ 834 HTT_STATS_RX_PDEV_RSSI_HIST_TAG = 202, /* htt_stats_rx_pdev_rssi_hist_tlv */ 835 836 HTT_STATS_MAX_TAG, 837 } htt_stats_tlv_tag_t; 838 /* retain deprecated enum name as an alias for the current enum name */ 839 typedef htt_stats_tlv_tag_t htt_tlv_tag_t; 840 841 #define HTT_STATS_TLV_TAG_M 0x00000fff 842 #define HTT_STATS_TLV_TAG_S 0 843 #define HTT_STATS_TLV_LENGTH_M 0x00fff000 844 #define HTT_STATS_TLV_LENGTH_S 12 845 846 #define HTT_STATS_TLV_TAG_GET(_var) \ 847 (((_var) & HTT_STATS_TLV_TAG_M) >> \ 848 HTT_STATS_TLV_TAG_S) 849 850 #define HTT_STATS_TLV_TAG_SET(_var, _val) \ 851 do { \ 852 HTT_CHECK_SET_VAL(HTT_STATS_TLV_TAG, _val); \ 853 ((_var) |= ((_val) << HTT_STATS_TLV_TAG_S)); \ 854 } while (0) 855 856 #define HTT_STATS_TLV_LENGTH_GET(_var) \ 857 (((_var) & HTT_STATS_TLV_LENGTH_M) >> \ 858 HTT_STATS_TLV_LENGTH_S) 859 #define HTT_STATS_TLV_LENGTH_SET(_var, _val) \ 860 do { \ 861 HTT_CHECK_SET_VAL(HTT_STATS_TLV_LENGTH, _val); \ 862 ((_var) |= ((_val) << HTT_STATS_TLV_LENGTH_S)); \ 863 } while (0) 864 865 866 /*=== host -> target messages ===============================================*/ 867 868 enum htt_h2t_msg_type { 869 HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, 870 HTT_H2T_MSG_TYPE_TX_FRM = 0x1, 871 HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, 872 HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, 873 HTT_H2T_MSG_TYPE_SYNC = 0x4, 874 HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, 875 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, 876 DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ 877 HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, 878 HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, 879 HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ 880 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 881 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 882 HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, 883 HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, 884 HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, 885 HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10, 886 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 887 HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, 888 HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, 889 HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, 890 HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, 891 HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, 892 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 893 HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18, 894 HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, 895 HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a, 896 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 897 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c, 898 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d, 899 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e, 900 HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f, 901 HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, 902 HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, 903 HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, 904 HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, 905 HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, 906 HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, 907 HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP = 0x26, 908 HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ = 0x27, 909 910 /* keep this last */ 911 HTT_H2T_NUM_MSGS 912 }; 913 914 /* 915 * HTT host to target message type - 916 * stored in bits 7:0 of the first word of the message 917 */ 918 #define HTT_H2T_MSG_TYPE_M 0xff 919 #define HTT_H2T_MSG_TYPE_S 0 920 921 #define HTT_H2T_MSG_TYPE_SET(word, msg_type) \ 922 do { \ 923 HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \ 924 (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \ 925 } while (0) 926 #define HTT_H2T_MSG_TYPE_GET(word) \ 927 (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S) 928 929 /** 930 * @brief host -> target version number request message definition 931 * 932 * MSG_TYPE => HTT_H2T_MSG_TYPE_VERSION_REQ 933 * 934 * 935 * |31 24|23 16|15 8|7 0| 936 * |----------------+----------------+----------------+----------------| 937 * | reserved | msg type | 938 * |-------------------------------------------------------------------| 939 * : option request TLV (optional) | 940 * :...................................................................: 941 * 942 * The VER_REQ message may consist of a single 4-byte word, or may be 943 * extended with TLVs that specify which HTT options the host is requesting 944 * from the target. 945 * The following option TLVs may be appended to the VER_REQ message: 946 * - HL_SUPPRESS_TX_COMPL_IND 947 * - HL_MAX_TX_QUEUE_GROUPS 948 * These TLVs may appear in an arbitrary order. Any number of these TLVs 949 * may be appended to the VER_REQ message (but only one TLV of each type). 950 * 951 * Header fields: 952 * - MSG_TYPE 953 * Bits 7:0 954 * Purpose: identifies this as a version number request message 955 * Value: 0x0 (HTT_H2T_MSG_TYPE_VERSION_REQ) 956 */ 957 958 #define HTT_VER_REQ_BYTES 4 959 960 /* TBDXXX: figure out a reasonable number */ 961 #define HTT_HL_DATA_SVC_PIPE_DEPTH 24 962 #define HTT_LL_DATA_SVC_PIPE_DEPTH 64 963 964 /** 965 * @brief HTT tx MSDU descriptor 966 * 967 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_FRM 968 * 969 * @details 970 * The HTT tx MSDU descriptor is created by the host HTT SW for each 971 * tx MSDU. The HTT tx MSDU descriptor contains the information that 972 * the target firmware needs for the FW's tx processing, particularly 973 * for creating the HW msdu descriptor. 974 * The same HTT tx descriptor is used for HL and LL systems, though 975 * a few fields within the tx descriptor are used only by LL or 976 * only by HL. 977 * The HTT tx descriptor is defined in two manners: by a struct with 978 * bitfields, and by a series of [dword offset, bit mask, bit shift] 979 * definitions. 980 * The target should use the struct def, for simplicitly and clarity, 981 * but the host shall use the bit-mast + bit-shift defs, to be endian- 982 * neutral. Specifically, the host shall use the get/set macros built 983 * around the mask + shift defs. 984 */ 985 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_S 0 986 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_M 0x1 987 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_S 1 988 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_M 0x2 989 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_S 2 990 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_M 0x4 991 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_S 3 992 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_M 0x8 993 994 #define HTT_TX_VDEV_ID_WORD 0 995 #define HTT_TX_VDEV_ID_MASK 0x3f 996 #define HTT_TX_VDEV_ID_SHIFT 16 997 998 #define HTT_TX_L3_CKSUM_OFFLOAD 1 999 #define HTT_TX_L4_CKSUM_OFFLOAD 2 1000 1001 #define HTT_TX_MSDU_LEN_DWORD 1 1002 #define HTT_TX_MSDU_LEN_MASK 0xffff; 1003 1004 /* 1005 * HTT_VAR_PADDR macros 1006 * Allow physical / bus addresses to be either a single 32-bit value, 1007 * or a 64-bit value, stored as a little-endian lo,hi pair of 32-bit parts 1008 */ 1009 #define HTT_VAR_PADDR32(var_name) \ 1010 A_UINT32 var_name 1011 #define HTT_VAR_PADDR64_LE(var_name) \ 1012 struct { \ 1013 /* little-endian: lo precedes hi */ \ 1014 A_UINT32 lo; \ 1015 A_UINT32 hi; \ 1016 } var_name 1017 1018 /* 1019 * TEMPLATE_HTT_TX_MSDU_DESC_T: 1020 * This macro defines a htt_tx_msdu_descXXX_t in which any physical 1021 * addresses are stored in a XXX-bit field. 1022 * This macro is used to define both htt_tx_msdu_desc32_t and 1023 * htt_tx_msdu_desc64_t structs. 1024 */ 1025 #define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \ 1026 PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \ 1027 { \ 1028 /* DWORD 0: flags and meta-data */ \ 1029 A_UINT32 \ 1030 msg_type: 8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \ 1031 \ 1032 /* pkt_subtype - \ 1033 * Detailed specification of the tx frame contents, extending the \ 1034 * general specification provided by pkt_type. \ 1035 * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \ 1036 * pkt_type | pkt_subtype \ 1037 * ============================================================== \ 1038 * 802.3 | bit 0:3 - Reserved \ 1039 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1040 * | not appended to the HTT message \ 1041 * | 0x1 - Copy-Engine Classification Results \ 1042 * | appended to the HTT message in the \ 1043 * | format: \ 1044 * | [HTT tx desc, frame header, \ 1045 * | CE classification results] \ 1046 * | The CE classification results begin \ 1047 * | at the next 4-byte boundary after \ 1048 * | the frame header. \ 1049 * ------------+------------------------------------------------- \ 1050 * Eth2 | bit 0:3 - Reserved \ 1051 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1052 * | not appended to the HTT message \ 1053 * | 0x1 - Copy-Engine Classification Results \ 1054 * | appended to the HTT message. \ 1055 * | See the above specification of the \ 1056 * | CE classification results location. \ 1057 * ------------+------------------------------------------------- \ 1058 * native WiFi | bit 0:3 - Reserved \ 1059 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1060 * | not appended to the HTT message \ 1061 * | 0x1 - Copy-Engine Classification Results \ 1062 * | appended to the HTT message. \ 1063 * | See the above specification of the \ 1064 * | CE classification results location. \ 1065 * ------------+------------------------------------------------- \ 1066 * mgmt | 0x0 - 802.11 MAC header absent \ 1067 * | 0x1 - 802.11 MAC header present \ 1068 * ------------+------------------------------------------------- \ 1069 * raw | bit 0: 0x0 - 802.11 MAC header absent \ 1070 * | 0x1 - 802.11 MAC header present \ 1071 * | bit 1: 0x0 - allow aggregation \ 1072 * | 0x1 - don't allow aggregation \ 1073 * | bit 2: 0x0 - perform encryption \ 1074 * | 0x1 - don't perform encryption \ 1075 * | bit 3: 0x0 - perform tx classification / queuing \ 1076 * | 0x1 - don't perform tx classification; \ 1077 * | insert the frame into the "misc" \ 1078 * | tx queue \ 1079 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1080 * | not appended to the HTT message \ 1081 * | 0x1 - Copy-Engine Classification Results \ 1082 * | appended to the HTT message. \ 1083 * | See the above specification of the \ 1084 * | CE classification results location. \ 1085 */ \ 1086 pkt_subtype: 5, \ 1087 \ 1088 /* pkt_type - \ 1089 * General specification of the tx frame contents. \ 1090 * The htt_pkt_type enum should be used to specify and check the \ 1091 * value of this field. \ 1092 */ \ 1093 pkt_type: 3, \ 1094 \ 1095 /* vdev_id - \ 1096 * ID for the vdev that is sending this tx frame. \ 1097 * For certain non-standard packet types, e.g. pkt_type == raw \ 1098 * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \ 1099 * This field is used primarily for determining where to queue \ 1100 * broadcast and multicast frames. \ 1101 */ \ 1102 vdev_id: 6, \ 1103 /* ext_tid - \ 1104 * The extended traffic ID. \ 1105 * If the TID is unknown, the extended TID is set to \ 1106 * HTT_TX_EXT_TID_INVALID. \ 1107 * If the tx frame is QoS data, then the extended TID has the 0-15 \ 1108 * value of the QoS TID. \ 1109 * If the tx frame is non-QoS data, then the extended TID is set to \ 1110 * HTT_TX_EXT_TID_NON_QOS. \ 1111 * If the tx frame is multicast or broadcast, then the extended TID \ 1112 * is set to HTT_TX_EXT_TID_MCAST_BCAST. \ 1113 */ \ 1114 ext_tid: 5, \ 1115 \ 1116 /* postponed - \ 1117 * This flag indicates whether the tx frame has been downloaded to \ 1118 * the target before but discarded by the target, and now is being \ 1119 * downloaded again; or if this is a new frame that is being \ 1120 * downloaded for the first time. \ 1121 * This flag allows the target to determine the correct order for \ 1122 * transmitting new vs. old frames. \ 1123 * value: 0 -> new frame, 1 -> re-send of a previously sent frame \ 1124 * This flag only applies to HL systems, since in LL systems, \ 1125 * the tx flow control is handled entirely within the target. \ 1126 */ \ 1127 postponed: 1, \ 1128 \ 1129 /* extension - \ 1130 * This flag indicates whether a HTT tx MSDU extension descriptor \ 1131 * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor. \ 1132 * \ 1133 * 0x0 - no extension MSDU descriptor is present \ 1134 * 0x1 - an extension MSDU descriptor immediately follows the \ 1135 * regular MSDU descriptor \ 1136 */ \ 1137 extension: 1, \ 1138 \ 1139 /* cksum_offload - \ 1140 * This flag indicates whether checksum offload is enabled or not \ 1141 * for this frame. Target FW use this flag to turn on HW checksumming \ 1142 * 0x0 - No checksum offload \ 1143 * 0x1 - L3 header checksum only \ 1144 * 0x2 - L4 checksum only \ 1145 * 0x3 - L3 header checksum + L4 checksum \ 1146 */ \ 1147 cksum_offload: 2, \ 1148 \ 1149 /* tx_comp_req - \ 1150 * This flag indicates whether Tx Completion \ 1151 * from fw is required or not. \ 1152 * This flag is only relevant if tx completion is not \ 1153 * universally enabled. \ 1154 * For all LL systems, tx completion is mandatory, \ 1155 * so this flag will be irrelevant. \ 1156 * For HL systems tx completion is optional, but HL systems in which \ 1157 * the bus throughput exceeds the WLAN throughput will \ 1158 * probably want to always use tx completion, and thus \ 1159 * would not check this flag. \ 1160 * This flag is required when tx completions are not used universally, \ 1161 * but are still required for certain tx frames for which \ 1162 * an OTA delivery acknowledgment is needed by the host. \ 1163 * In practice, this would be for HL systems in which the \ 1164 * bus throughput is less than the WLAN throughput. \ 1165 * \ 1166 * 0x0 - Tx Completion Indication from Fw not required \ 1167 * 0x1 - Tx Completion Indication from Fw is required \ 1168 */ \ 1169 tx_compl_req: 1; \ 1170 \ 1171 \ 1172 /* DWORD 1: MSDU length and ID */ \ 1173 A_UINT32 \ 1174 len: 16, /* MSDU length, in bytes */ \ 1175 id: 16; /* MSDU ID used to identify the MSDU to the host, \ 1176 * and this id is used to calculate fragmentation \ 1177 * descriptor pointer inside the target based on \ 1178 * the base address, configured inside the target. \ 1179 */ \ 1180 \ 1181 /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \ 1182 /* frags_desc_ptr - \ 1183 * The fragmentation descriptor pointer tells the HW's MAC DMA \ 1184 * where the tx frame's fragments reside in memory. \ 1185 * This field only applies to LL systems, since in HL systems the \ 1186 * (degenerate single-fragment) fragmentation descriptor is created \ 1187 * within the target. \ 1188 */ \ 1189 _paddr__frags_desc_ptr_; \ 1190 \ 1191 /* DWORD 3 (or 4): peerid, chanfreq */ \ 1192 /* \ 1193 * Peer ID : Target can use this value to know which peer-id packet \ 1194 * destined to. \ 1195 * It's intended to be specified by host in case of NAWDS. \ 1196 */ \ 1197 A_UINT16 peerid; \ 1198 \ 1199 /* \ 1200 * Channel frequency: This identifies the desired channel \ 1201 * frequency (in mhz) for tx frames. This is used by FW to help \ 1202 * determine when it is safe to transmit or drop frames for \ 1203 * off-channel operation. \ 1204 * The default value of zero indicates to FW that the corresponding \ 1205 * VDEV's home channel (if there is one) is the desired channel \ 1206 * frequency. \ 1207 */ \ 1208 A_UINT16 chanfreq; \ 1209 \ 1210 /* Reason reserved is commented is increasing the htt structure size \ 1211 * leads to some weird issues. \ 1212 * A_UINT32 reserved_dword3_bits0_31; \ 1213 */ \ 1214 } POSTPACK 1215 /* define a htt_tx_msdu_desc32_t type */ 1216 TEMPLATE_HTT_TX_MSDU_DESC_T(32, HTT_VAR_PADDR32(frags_desc_ptr)); 1217 /* define a htt_tx_msdu_desc64_t type */ 1218 TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr)); 1219 /* 1220 * Make htt_tx_msdu_desc_t be an alias for either 1221 * htt_tx_msdu_desc32_t or htt_tx_msdu_desc64_t 1222 */ 1223 #if HTT_PADDR64 1224 #define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t 1225 #else 1226 #define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t 1227 #endif 1228 1229 /* decriptor information for Management frame*/ 1230 /* 1231 * THIS htt_mgmt_tx_desc_t STRUCT IS DEPRECATED - DON'T USE IT. 1232 * BOTH MANAGEMENT AND DATA FRAMES SHOULD USE htt_tx_msdu_desc_t. 1233 */ 1234 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 1235 extern A_UINT32 mgmt_hdr_len; 1236 PREPACK struct htt_mgmt_tx_desc_t { 1237 A_UINT32 msg_type; 1238 #if HTT_PADDR64 1239 A_UINT64 frag_paddr; /* DMAble address of the data */ 1240 #else 1241 A_UINT32 frag_paddr; /* DMAble address of the data */ 1242 #endif 1243 A_UINT32 desc_id; /* returned to host during completion 1244 * to free the meory*/ 1245 A_UINT32 len; /* Fragment length */ 1246 A_UINT32 vdev_id; /* virtual device ID*/ 1247 A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */ 1248 } POSTPACK; 1249 1250 PREPACK struct htt_mgmt_tx_compl_ind { 1251 A_UINT32 desc_id; 1252 A_UINT32 status; 1253 } POSTPACK; 1254 1255 /* 1256 * This SDU header size comes from the summation of the following: 1257 * 1. Max of: 1258 * a. Native WiFi header, for native WiFi frames: 24 bytes 1259 * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4) 1260 * b. 802.11 header, for raw frames: 36 bytes 1261 * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4, 1262 * QoS header, HT header) 1263 * c. 802.3 header, for ethernet frames: 14 bytes 1264 * (destination address, source address, ethertype / length) 1265 * 2. Max of: 1266 * a. IPv4 header, up through the DiffServ Code Point: 2 bytes 1267 * b. IPv6 header, up through the Traffic Class: 2 bytes 1268 * 3. 802.1Q VLAN header: 4 bytes 1269 * 4. LLC/SNAP header: 8 bytes 1270 */ 1271 #define HTT_TX_HDR_SIZE_NATIVE_WIFI 30 1272 #define HTT_TX_HDR_SIZE_802_11_RAW 36 1273 #define HTT_TX_HDR_SIZE_ETHERNET 14 1274 1275 #define HTT_TX_HDR_SIZE_OUTER_HDR_MAX HTT_TX_HDR_SIZE_802_11_RAW 1276 A_COMPILE_TIME_ASSERT( 1277 htt_encap_hdr_size_max_check_nwifi, 1278 HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_NATIVE_WIFI); 1279 A_COMPILE_TIME_ASSERT( 1280 htt_encap_hdr_size_max_check_enet, 1281 HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_ETHERNET); 1282 1283 #define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */ 1284 #define HTT_LL_TX_HDR_SIZE_IP 16 /* up to the end of UDP header for IPv4 case */ 1285 1286 #define HTT_TX_HDR_SIZE_802_1Q 4 1287 #define HTT_TX_HDR_SIZE_LLC_SNAP 8 1288 1289 1290 #define HTT_COMMON_TX_FRM_HDR_LEN \ 1291 (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \ 1292 HTT_TX_HDR_SIZE_802_1Q + \ 1293 HTT_TX_HDR_SIZE_LLC_SNAP) 1294 1295 #define HTT_HL_TX_FRM_HDR_LEN \ 1296 (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP) 1297 1298 #define HTT_LL_TX_FRM_HDR_LEN \ 1299 (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP) 1300 1301 #define HTT_TX_DESC_LEN sizeof(struct htt_tx_msdu_desc_t) 1302 1303 /* dword 0 */ 1304 #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_BYTES 0 1305 #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_DWORD 0 1306 #define HTT_TX_DESC_PKT_SUBTYPE_M 0x00001f00 1307 #define HTT_TX_DESC_PKT_SUBTYPE_S 8 1308 1309 #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_BYTES 0 1310 #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_DWORD 0 1311 #define HTT_TX_DESC_NO_ENCRYPT_M 0x00000400 1312 #define HTT_TX_DESC_NO_ENCRYPT_S 10 1313 1314 #define HTT_TX_DESC_PKT_TYPE_OFFSET_BYTES 0 1315 #define HTT_TX_DESC_PKT_TYPE_OFFSET_DWORD 0 1316 #define HTT_TX_DESC_PKT_TYPE_M 0x0000e000 1317 #define HTT_TX_DESC_PKT_TYPE_S 13 1318 1319 #define HTT_TX_DESC_VDEV_ID_OFFSET_BYTES 0 1320 #define HTT_TX_DESC_VDEV_ID_OFFSET_DWORD 0 1321 #define HTT_TX_DESC_VDEV_ID_M 0x003f0000 1322 #define HTT_TX_DESC_VDEV_ID_S 16 1323 1324 #define HTT_TX_DESC_EXT_TID_OFFSET_BYTES 0 1325 #define HTT_TX_DESC_EXT_TID_OFFSET_DWORD 0 1326 #define HTT_TX_DESC_EXT_TID_M 0x07c00000 1327 #define HTT_TX_DESC_EXT_TID_S 22 1328 1329 #define HTT_TX_DESC_POSTPONED_OFFSET_BYTES 0 1330 #define HTT_TX_DESC_POSTPONED_OFFSET_DWORD 0 1331 #define HTT_TX_DESC_POSTPONED_M 0x08000000 1332 #define HTT_TX_DESC_POSTPONED_S 27 1333 1334 #define HTT_TX_DESC_EXTENSION_OFFSET_BYTE 0 1335 #define HTT_TX_DESC_EXTENSION_OFFSET_DWORD 0 1336 #define HTT_TX_DESC_EXTENSION_M 0x10000000 1337 #define HTT_TX_DESC_EXTENSION_S 28 1338 1339 #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_BYTES 0 1340 #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_DWORD 0 1341 #define HTT_TX_DESC_CKSUM_OFFLOAD_M 0x60000000 1342 #define HTT_TX_DESC_CKSUM_OFFLOAD_S 29 1343 1344 #define HTT_TX_DESC_TX_COMP_OFFSET_BYTES 0 1345 #define HTT_TX_DESC_TX_COMP_OFFSET_DWORD 0 1346 #define HTT_TX_DESC_TX_COMP_M 0x80000000 1347 #define HTT_TX_DESC_TX_COMP_S 31 1348 1349 /* dword 1 */ 1350 #define HTT_TX_DESC_FRM_LEN_OFFSET_BYTES 4 1351 #define HTT_TX_DESC_FRM_LEN_OFFSET_DWORD 1 1352 #define HTT_TX_DESC_FRM_LEN_M 0x0000ffff 1353 #define HTT_TX_DESC_FRM_LEN_S 0 1354 1355 #define HTT_TX_DESC_FRM_ID_OFFSET_BYTES 4 1356 #define HTT_TX_DESC_FRM_ID_OFFSET_DWORD 1 1357 #define HTT_TX_DESC_FRM_ID_M 0xffff0000 1358 #define HTT_TX_DESC_FRM_ID_S 16 1359 1360 /* dword 2 */ 1361 #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_BYTES 8 1362 #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_DWORD 2 1363 /* for systems using 64-bit format for bus addresses */ 1364 #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_M 0xffffffff 1365 #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_S 0 1366 #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_M 0xffffffff 1367 #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_S 0 1368 /* for systems using 32-bit format for bus addresses */ 1369 #define HTT_TX_DESC_FRAGS_DESC_PADDR_M 0xffffffff 1370 #define HTT_TX_DESC_FRAGS_DESC_PADDR_S 0 1371 1372 /* dword 3 */ 1373 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 16 1374 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 12 1375 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \ 1376 (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2) 1377 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \ 1378 (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2) 1379 1380 #if HTT_PADDR64 1381 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 1382 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 1383 #else 1384 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 1385 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 1386 #endif 1387 1388 #define HTT_TX_DESC_PEER_ID_M 0x0000ffff 1389 #define HTT_TX_DESC_PEER_ID_S 0 1390 /* 1391 * TEMPORARY: 1392 * The original definitions for the PEER_ID fields contained typos 1393 * (with _DESC_PADDR appended to this PEER_ID field name). 1394 * Retain deprecated original names for PEER_ID fields until all code that 1395 * refers to them has been updated. 1396 */ 1397 #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \ 1398 HTT_TX_DESC_PEER_ID_OFFSET_BYTES 1399 #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \ 1400 HTT_TX_DESC_PEER_ID_OFFSET_DWORD 1401 #define HTT_TX_DESC_PEERID_DESC_PADDR_M \ 1402 HTT_TX_DESC_PEER_ID_M 1403 #define HTT_TX_DESC_PEERID_DESC_PADDR_S \ 1404 HTT_TX_DESC_PEER_ID_S 1405 1406 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 16 /* to dword with chan freq */ 1407 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 12 /* to dword with chan freq */ 1408 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \ 1409 (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2) 1410 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \ 1411 (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2) 1412 1413 #if HTT_PADDR64 1414 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 1415 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 1416 #else 1417 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 1418 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 1419 #endif 1420 1421 #define HTT_TX_DESC_CHAN_FREQ_M 0xffff0000 1422 #define HTT_TX_DESC_CHAN_FREQ_S 16 1423 1424 #define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \ 1425 (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S) 1426 #define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \ 1427 do { \ 1428 HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \ 1429 ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \ 1430 } while (0) 1431 1432 #define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \ 1433 (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S) 1434 #define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \ 1435 do { \ 1436 HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \ 1437 ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \ 1438 } while (0) 1439 1440 #define HTT_TX_DESC_PKT_TYPE_GET(_var) \ 1441 (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S) 1442 #define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \ 1443 do { \ 1444 HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \ 1445 ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \ 1446 } while (0) 1447 1448 #define HTT_TX_DESC_VDEV_ID_GET(_var) \ 1449 (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S) 1450 #define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \ 1451 do { \ 1452 HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \ 1453 ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \ 1454 } while (0) 1455 1456 #define HTT_TX_DESC_EXT_TID_GET(_var) \ 1457 (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S) 1458 #define HTT_TX_DESC_EXT_TID_SET(_var, _val) \ 1459 do { \ 1460 HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \ 1461 ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \ 1462 } while (0) 1463 1464 #define HTT_TX_DESC_POSTPONED_GET(_var) \ 1465 (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S) 1466 #define HTT_TX_DESC_POSTPONED_SET(_var, _val) \ 1467 do { \ 1468 HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \ 1469 ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \ 1470 } while (0) 1471 1472 #define HTT_TX_DESC_EXTENSION_GET(_var) \ 1473 (((_var) & HTT_TX_DESC_EXTENSION_M) >> HTT_TX_DESC_EXTENSION_S) 1474 #define HTT_TX_DESC_EXTENSION_SET(_var, _val) \ 1475 do { \ 1476 HTT_CHECK_SET_VAL(HTT_TX_DESC_EXTENSION, _val); \ 1477 ((_var) |= ((_val) << HTT_TX_DESC_EXTENSION_S)); \ 1478 } while (0) 1479 1480 #define HTT_TX_DESC_FRM_LEN_GET(_var) \ 1481 (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S) 1482 #define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \ 1483 do { \ 1484 HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \ 1485 ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \ 1486 } while (0) 1487 1488 #define HTT_TX_DESC_FRM_ID_GET(_var) \ 1489 (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S) 1490 #define HTT_TX_DESC_FRM_ID_SET(_var, _val) \ 1491 do { \ 1492 HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \ 1493 ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \ 1494 } while (0) 1495 1496 #define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \ 1497 (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S) 1498 #define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \ 1499 do { \ 1500 HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \ 1501 ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \ 1502 } while (0) 1503 1504 #define HTT_TX_DESC_TX_COMP_GET(_var) \ 1505 (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S) 1506 #define HTT_TX_DESC_TX_COMP_SET(_var, _val) \ 1507 do { \ 1508 HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \ 1509 ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \ 1510 } while (0) 1511 1512 #define HTT_TX_DESC_PEER_ID_GET(_var) \ 1513 (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S) 1514 #define HTT_TX_DESC_PEER_ID_SET(_var, _val) \ 1515 do { \ 1516 HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \ 1517 ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \ 1518 } while (0) 1519 1520 #define HTT_TX_DESC_CHAN_FREQ_GET(_var) \ 1521 (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S) 1522 #define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \ 1523 do { \ 1524 HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \ 1525 ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \ 1526 } while (0) 1527 1528 1529 /* enums used in the HTT tx MSDU extension descriptor */ 1530 enum { 1531 htt_tx_guard_interval_regular = 0, 1532 htt_tx_guard_interval_short = 1, 1533 }; 1534 1535 enum { 1536 htt_tx_preamble_type_ofdm = 0, 1537 htt_tx_preamble_type_cck = 1, 1538 htt_tx_preamble_type_ht = 2, 1539 htt_tx_preamble_type_vht = 3, 1540 }; 1541 1542 enum { 1543 htt_tx_bandwidth_5MHz = 0, 1544 htt_tx_bandwidth_10MHz = 1, 1545 htt_tx_bandwidth_20MHz = 2, 1546 htt_tx_bandwidth_40MHz = 3, 1547 htt_tx_bandwidth_80MHz = 4, 1548 htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */ 1549 }; 1550 1551 /** 1552 * @brief HTT tx MSDU extension descriptor 1553 * @details 1554 * If the target supports HTT tx MSDU extension descriptors, the host has 1555 * the option of appending the following struct following the regular 1556 * HTT tx MSDU descriptor (and setting the "extension" flag in the regular 1557 * HTT tx MSDU descriptor, to show that the extension descriptor is present). 1558 * The HTT tx MSDU extension descriptors allows the host to provide detailed 1559 * tx specs for each frame. 1560 */ 1561 PREPACK struct htt_tx_msdu_desc_ext_t { 1562 /* DWORD 0: flags */ 1563 A_UINT32 1564 valid_pwr: 1, /* bit 0: if set, tx pwr spec is valid */ 1565 valid_mcs_mask: 1, /* bit 1: if set, tx MCS mask spec is valid */ 1566 valid_nss_mask: 1, /* bit 2: if set, tx Nss mask spec is valid */ 1567 valid_guard_interval: 1, /* bit 3: if set, tx guard intv spec is valid*/ 1568 valid_preamble_type_mask: 1, /* 4: if set, tx preamble mask is valid */ 1569 valid_chainmask: 1, /* bit 5: if set, tx chainmask spec is valid */ 1570 valid_retries: 1, /* bit 6: if set, tx retries spec is valid */ 1571 valid_bandwidth: 1, /* bit 7: if set, tx bandwidth spec is valid */ 1572 valid_expire_tsf: 1, /* bit 8: if set, tx expire TSF spec is valid*/ 1573 is_dsrc: 1, /* bit 9: if set, MSDU is a DSRC frame */ 1574 reserved0_31_7: 22; /* bits 31:10 - unused, set to 0x0 */ 1575 1576 /* DWORD 1: tx power, tx rate, tx BW */ 1577 A_UINT32 1578 /* pwr - 1579 * Specify what power the tx frame needs to be transmitted at. 1580 * The power a signed (two's complement) value is in units of 0.5 dBm. 1581 * The value needs to be appropriately sign-extended when extracting 1582 * the value from the message and storing it in a variable that is 1583 * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro 1584 * automatically handles this sign-extension.) 1585 * If the transmission uses multiple tx chains, this power spec is 1586 * the total transmit power, assuming incoherent combination of 1587 * per-chain power to produce the total power. 1588 */ 1589 pwr: 8, 1590 1591 /* mcs_mask - 1592 * Specify the allowable values for MCS index (modulation and coding) 1593 * to use for transmitting the frame. 1594 * 1595 * For HT / VHT preamble types, this mask directly corresponds to 1596 * the HT or VHT MCS indices that are allowed. For each bit N set 1597 * within the mask, MCS index N is allowed for transmitting the frame. 1598 * For legacy CCK and OFDM rates, separate bits are provided for CCK 1599 * rates versus OFDM rates, so the host has the option of specifying 1600 * that the target must transmit the frame with CCK or OFDM rates 1601 * (not HT or VHT), but leaving the decision to the target whether 1602 * to use CCK or OFDM. 1603 * 1604 * For CCK and OFDM, the bits within this mask are interpreted as 1605 * follows: 1606 * bit 0 -> CCK 1 Mbps rate is allowed 1607 * bit 1 -> CCK 2 Mbps rate is allowed 1608 * bit 2 -> CCK 5.5 Mbps rate is allowed 1609 * bit 3 -> CCK 11 Mbps rate is allowed 1610 * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed 1611 * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed 1612 * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed 1613 * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed 1614 * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed 1615 * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed 1616 * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed 1617 * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed 1618 * 1619 * The MCS index specification needs to be compatible with the 1620 * bandwidth mask specification. For example, a MCS index == 9 1621 * specification is inconsistent with a preamble type == VHT, 1622 * Nss == 1, and channel bandwidth == 20 MHz. 1623 * 1624 * Furthermore, the host has only a limited ability to specify to 1625 * the target to select from HT + legacy rates, or VHT + legacy rates, 1626 * since this mcs_mask can specify either HT/VHT rates or legacy rates. 1627 */ 1628 mcs_mask: 12, 1629 1630 /* nss_mask - 1631 * Specify which numbers of spatial streams (MIMO factor) are permitted. 1632 * Each bit in this mask corresponds to a Nss value: 1633 * bit 0: if set, Nss = 1 (non-MIMO) is permitted 1634 * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted 1635 * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted 1636 * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted 1637 * The values in the Nss mask must be suitable for the recipient, e.g. 1638 * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a 1639 * recipient which only supports 2x2 MIMO. 1640 */ 1641 nss_mask: 4, 1642 1643 /* guard_interval - 1644 * Specify a htt_tx_guard_interval enum value to indicate whether 1645 * the transmission should use a regular guard interval or a 1646 * short guard interval. 1647 */ 1648 guard_interval: 1, 1649 1650 /* preamble_type_mask - 1651 * Specify which preamble types (CCK, OFDM, HT, VHT) the target 1652 * may choose from for transmitting this frame. 1653 * The bits in this mask correspond to the values in the 1654 * htt_tx_preamble_type enum. For example, to allow the target 1655 * to transmit the frame as either CCK or OFDM, this field would 1656 * be set to 1657 * (1 << htt_tx_preamble_type_ofdm) | 1658 * (1 << htt_tx_preamble_type_cck) 1659 */ 1660 preamble_type_mask: 4, 1661 1662 reserved1_31_29: 3; /* unused, set to 0x0 */ 1663 1664 /* DWORD 2: tx chain mask, tx retries */ 1665 A_UINT32 1666 /* chain_mask - specify which chains to transmit from */ 1667 chain_mask: 4, 1668 1669 /* retry_limit - 1670 * Specify the maximum number of transmissions, including the 1671 * initial transmission, to attempt before giving up if no ack 1672 * is received. 1673 * If the tx rate is specified, then all retries shall use the 1674 * same rate as the initial transmission. 1675 * If no tx rate is specified, the target can choose whether to 1676 * retain the original rate during the retransmissions, or to 1677 * fall back to a more robust rate. 1678 */ 1679 retry_limit: 4, 1680 1681 /* bandwidth_mask - 1682 * Specify what channel widths may be used for the transmission. 1683 * A value of zero indicates "don't care" - the target may choose 1684 * the transmission bandwidth. 1685 * The bits within this mask correspond to the htt_tx_bandwidth 1686 * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc. 1687 * The bandwidth_mask must be consistent with the preamble_type_mask 1688 * and mcs_mask specs, if they are provided. For example, 80 MHz and 1689 * 160 MHz can only be enabled in the mask if preamble_type == VHT. 1690 */ 1691 bandwidth_mask: 6, 1692 1693 reserved2_31_14: 18; /* unused, set to 0x0 */ 1694 1695 /* DWORD 3: tx expiry time (TSF) LSBs */ 1696 A_UINT32 expire_tsf_lo; 1697 1698 /* DWORD 4: tx expiry time (TSF) MSBs */ 1699 A_UINT32 expire_tsf_hi; 1700 1701 A_UINT32 reserved_for_future_expansion_set_to_zero[3]; 1702 } POSTPACK; 1703 1704 /* DWORD 0 */ 1705 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M 0x00000001 1706 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S 0 1707 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 1708 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S 1 1709 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 1710 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_S 2 1711 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000008 1712 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S 3 1713 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M 0x00000010 1714 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S 4 1715 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000020 1716 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S 5 1717 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M 0x00000040 1718 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S 6 1719 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M 0x00000080 1720 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S 7 1721 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000100 1722 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S 8 1723 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M 0x00000200 1724 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S 9 1725 1726 /* DWORD 1 */ 1727 #define HTT_TX_MSDU_EXT_DESC_PWR_M 0x000000ff 1728 #define HTT_TX_MSDU_EXT_DESC_PWR_S 0 1729 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_M 0x000fff00 1730 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_S 8 1731 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_M 0x00f00000 1732 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_S 20 1733 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M 0x01000000 1734 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S 24 1735 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M 0x1c000000 1736 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S 25 1737 1738 /* DWORD 2 */ 1739 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M 0x0000000f 1740 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S 0 1741 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M 0x000000f0 1742 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S 4 1743 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M 0x00003f00 1744 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S 8 1745 1746 1747 /* DWORD 0 */ 1748 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_GET(_var) \ 1749 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ 1750 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S) 1751 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_SET(_var, _val) \ 1752 do { \ 1753 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \ 1754 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \ 1755 } while (0) 1756 1757 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ 1758 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \ 1759 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S) 1760 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ 1761 do { \ 1762 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \ 1763 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \ 1764 } while (0) 1765 1766 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ 1767 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ 1768 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S) 1769 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ 1770 do { \ 1771 HTT_CHECK_SET_VAL( \ 1772 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ 1773 ((_var) |= ((_val) \ 1774 << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ 1775 } while (0) 1776 1777 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_GET(_var) \ 1778 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >> \ 1779 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S) 1780 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_SET(_var, _val) \ 1781 do { \ 1782 HTT_CHECK_SET_VAL( \ 1783 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \ 1784 ((_var) |= ((_val) \ 1785 << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \ 1786 } while (0) 1787 1788 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ 1789 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ 1790 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S) 1791 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ 1792 do { \ 1793 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \ 1794 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \ 1795 } while (0) 1796 1797 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_GET(_var) \ 1798 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \ 1799 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S) 1800 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ 1801 do { \ 1802 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \ 1803 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \ 1804 } while (0) 1805 1806 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_GET(_var) \ 1807 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \ 1808 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S) 1809 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_SET(_var, _val) \ 1810 do { \ 1811 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \ 1812 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \ 1813 } while (0) 1814 1815 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ 1816 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ 1817 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S) 1818 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ 1819 do { \ 1820 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ 1821 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\ 1822 } while (0) 1823 1824 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_GET(_var) \ 1825 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \ 1826 HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S) 1827 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_SET(_var, _val) \ 1828 do { \ 1829 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \ 1830 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \ 1831 } while (0) 1832 1833 1834 /* DWORD 1 */ 1835 #define HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) \ 1836 (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \ 1837 HTT_TX_MSDU_EXT_DESC_PWR_S) 1838 #define HTT_TX_MSDU_EXT_DESC_PWR_GET(_var) \ 1839 (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \ 1840 HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR)) 1841 #define HTT_TX_MSDU_EXT_DESC_PWR_SET(_var, _val) \ 1842 ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \ 1843 HTT_TX_MSDU_EXT_DESC_PWR_M) 1844 1845 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_GET(_var) \ 1846 (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \ 1847 HTT_TX_MSDU_EXT_DESC_MCS_MASK_S) 1848 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_SET(_var, _val) \ 1849 do { \ 1850 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \ 1851 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \ 1852 } while (0) 1853 1854 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_GET(_var) \ 1855 (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \ 1856 HTT_TX_MSDU_EXT_DESC_NSS_MASK_S) 1857 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_SET(_var, _val) \ 1858 do { \ 1859 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \ 1860 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \ 1861 } while (0) 1862 1863 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_GET(_var) \ 1864 (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \ 1865 HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S) 1866 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_SET(_var, _val) \ 1867 do { \ 1868 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \ 1869 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \ 1870 } while (0) 1871 1872 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_GET(_var) \ 1873 (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \ 1874 HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S) 1875 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_SET(_var, _val) \ 1876 do { \ 1877 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK, _val); \ 1878 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \ 1879 } while (0) 1880 1881 1882 /* DWORD 2 */ 1883 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_GET(_var) \ 1884 (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \ 1885 HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S) 1886 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_SET(_var, _val) \ 1887 do { \ 1888 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \ 1889 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \ 1890 } while (0) 1891 1892 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_GET(_var) \ 1893 (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \ 1894 HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S) 1895 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_SET(_var, _val) \ 1896 do { \ 1897 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \ 1898 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \ 1899 } while (0) 1900 1901 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_GET(_var) \ 1902 (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \ 1903 HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S) 1904 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_SET(_var, _val) \ 1905 do { \ 1906 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \ 1907 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \ 1908 } while (0) 1909 1910 1911 typedef enum { 1912 HTT_11AX_HE_LTF_SUBTYPE_1X, 1913 HTT_11AX_HE_LTF_SUBTYPE_2X, 1914 HTT_11AX_HE_LTF_SUBTYPE_4X, 1915 } htt_11ax_ltf_subtype_t; 1916 1917 typedef enum { 1918 HTT_TX_MSDU_EXT2_DESC_PREAM_OFDM, 1919 HTT_TX_MSDU_EXT2_DESC_PREAM_CCK, 1920 HTT_TX_MSDU_EXT2_DESC_PREAM_HT , 1921 HTT_TX_MSDU_EXT2_DESC_PREAM_VHT, 1922 HTT_TX_MSDU_EXT2_DESC_PREAM_HE_SU, 1923 HTT_TX_MSDU_EXT2_DESC_PREAM_HE_EXT_SU, 1924 } htt_tx_ext2_preamble_type_t; 1925 1926 #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_M 0x00000001 1927 #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_S 0 1928 #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_M 0x00000002 1929 #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_S 1 1930 #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_M 0x00000004 1931 #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_S 2 1932 #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_M 0x00000008 1933 #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_S 3 1934 #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_M 0x00000010 1935 #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_S 4 1936 #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_M 0x00000020 1937 #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_S 5 1938 1939 /* Rx buffer addr qdata ctrl pkt */ 1940 struct htt_h2t_rx_buffer_addr_info { 1941 A_UINT32 buffer_addr_31_0 : 32; // [31:0] 1942 A_UINT32 buffer_addr_39_32 : 8, // [7:0] 1943 return_buffer_manager : 4, // [11:8] 1944 sw_buffer_cookie : 20; // [31:12] 1945 }; 1946 1947 /** 1948 * @brief HTT tx MSDU extension descriptor v2 1949 * @details 1950 * In Lithium, if htt_tx_tcl_metadata->valid_htt_ext is set, this structure 1951 * is received as tcl_exit_base->host_meta_info in firmware. 1952 * Also there is no htt_tx_msdu_desc_t in Lithium since most of those fields 1953 * are already part of tcl_exit_base. 1954 */ 1955 PREPACK struct htt_tx_msdu_desc_ext2_t { 1956 /* DWORD 0: flags */ 1957 A_UINT32 1958 valid_pwr : 1, /* if set, tx pwr spec is valid */ 1959 valid_mcs_mask : 1, /* if set, tx MCS mask is valid */ 1960 valid_nss_mask : 1, /* if set, tx Nss mask is valid */ 1961 valid_preamble_type : 1, /* if set, tx preamble spec is valid */ 1962 valid_retries : 1, /* if set, tx retries spec is valid */ 1963 valid_bw_info : 1, /* if set, tx dyn_bw and bw_mask are valid */ 1964 valid_guard_interval : 1, /* if set, tx guard intv spec is valid */ 1965 valid_chainmask : 1, /* if set, tx chainmask is valid */ 1966 valid_encrypt_type : 1, /* if set, encrypt type is valid */ 1967 valid_key_flags : 1, /* if set, key flags is valid */ 1968 valid_expire_tsf : 1, /* if set, tx expire TSF spec is valid */ 1969 valid_chanfreq : 1, /* if set, chanfreq is valid */ 1970 is_dsrc : 1, /* if set, MSDU is a DSRC frame */ 1971 guard_interval : 2, /* 0.4us, 0.8us, 1.6us, 3.2us */ 1972 encrypt_type : 2, /* 0 = NO_ENCRYPT, 1973 1 = ENCRYPT, 1974 2 ~ 3 - Reserved */ 1975 /* retry_limit - 1976 * Specify the maximum number of transmissions, including the 1977 * initial transmission, to attempt before giving up if no ack 1978 * is received. 1979 * If the tx rate is specified, then all retries shall use the 1980 * same rate as the initial transmission. 1981 * If no tx rate is specified, the target can choose whether to 1982 * retain the original rate during the retransmissions, or to 1983 * fall back to a more robust rate. 1984 */ 1985 retry_limit : 4, 1986 use_dcm_11ax : 1, /* If set, Use Dual subcarrier modulation. 1987 * Valid only for 11ax preamble types HE_SU 1988 * and HE_EXT_SU 1989 */ 1990 ltf_subtype_11ax : 2, /* Takes enum values of htt_11ax_ltf_subtype_t 1991 * Valid only for 11ax preamble types HE_SU 1992 * and HE_EXT_SU 1993 */ 1994 dyn_bw : 1, /* 0 = static bw, 1 = dynamic bw */ 1995 bw_mask : 6, /* Valid only if dyn_bw == 0 (static bw). 1996 * (Bit mask of 5, 10, 20, 40, 80, 160Mhz. 1997 * Refer to HTT_TX_MSDU_EXT2_DESC_BW defs.) 1998 */ 1999 host_tx_desc_pool : 1; /* If set, Firmware allocates tx_descriptors 2000 * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead 2001 * of WAL_BUFFERID_TX_TCL_DATA_EXP. 2002 * Use cases: 2003 * Any time firmware uses TQM-BYPASS for Data 2004 * TID, firmware expect host to set this bit. 2005 */ 2006 2007 /* DWORD 1: tx power, tx rate */ 2008 A_UINT32 2009 power : 8, /* unit of the power field is 0.5 dbm 2010 * similar to pwr field in htt_tx_msdu_desc_ext_t 2011 * signed value ranging from -64dbm to 63.5 dbm 2012 */ 2013 mcs_mask : 12, /* mcs bit mask of 0 ~ 11 2014 * Setting more than one MCS isn't currently 2015 * supported by the target (but is supported 2016 * in the interface in case in the future 2017 * the target supports specifications of 2018 * a limited set of MCS values. 2019 */ 2020 nss_mask : 8, /* Nss bit mask 0 ~ 7 2021 * Setting more than one Nss isn't currently 2022 * supported by the target (but is supported 2023 * in the interface in case in the future 2024 * the target supports specifications of 2025 * a limited set of Nss values. 2026 */ 2027 pream_type : 3, /* Takes enum values of htt_tx_ext2_preamble_type_t */ 2028 update_peer_cache : 1; /* When set these custom values will be 2029 * used for all packets, until the next 2030 * update via this ext header. 2031 * This is to make sure not all packets 2032 * need to include this header. 2033 */ 2034 2035 /* DWORD 2: tx chain mask, tx retries */ 2036 A_UINT32 2037 /* chain_mask - specify which chains to transmit from */ 2038 chain_mask : 8, 2039 2040 key_flags : 8, /* Key Index and related flags - used in mesh mode 2041 * TODO: Update Enum values for key_flags 2042 */ 2043 2044 /* 2045 * Channel frequency: This identifies the desired channel 2046 * frequency (in MHz) for tx frames. This is used by FW to help 2047 * determine when it is safe to transmit or drop frames for 2048 * off-channel operation. 2049 * The default value of zero indicates to FW that the corresponding 2050 * VDEV's home channel (if there is one) is the desired channel 2051 * frequency. 2052 */ 2053 chanfreq : 16; 2054 2055 /* DWORD 3: tx expiry time (TSF) LSBs */ 2056 A_UINT32 expire_tsf_lo; 2057 2058 /* DWORD 4: tx expiry time (TSF) MSBs */ 2059 A_UINT32 expire_tsf_hi; 2060 2061 /* DWORD 5: flags to control routing / processing of the MSDU */ 2062 A_UINT32 2063 /* learning_frame 2064 * When this flag is set, this frame will be dropped by FW 2065 * rather than being enqueued to the Transmit Queue Manager (TQM) HW. 2066 */ 2067 learning_frame : 1, 2068 /* send_as_standalone 2069 * This will indicate if the msdu needs to be sent as a singleton PPDU, 2070 * i.e. with no A-MSDU or A-MPDU aggregation. 2071 * The scope is extended to other use-cases. 2072 */ 2073 send_as_standalone : 1, 2074 /* is_host_opaque_valid 2075 * Host should set this bit to 1 if the host_opaque_cookie is populated 2076 * with valid information. 2077 */ 2078 is_host_opaque_valid : 1, 2079 traffic_end_indication: 1, 2080 rsvd0 : 28; 2081 2082 /* DWORD 6 : Host opaque cookie for special frames */ 2083 A_UINT32 host_opaque_cookie : 16, /* see is_host_opaque_valid */ 2084 rsvd1 : 16; 2085 2086 /* DWORD 7-8 : Rx buffer addr for qdata frames */ 2087 struct htt_h2t_rx_buffer_addr_info rx_buffer_addr; 2088 2089 /* 2090 * This structure can be expanded further up to 32 bytes 2091 * by adding further DWORDs as needed. 2092 */ 2093 } POSTPACK; 2094 2095 /* DWORD 0 */ 2096 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_M 0x00000001 2097 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S 0 2098 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 2099 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S 1 2100 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 2101 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S 2 2102 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M 0x00000008 2103 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S 3 2104 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M 0x00000010 2105 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S 4 2106 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M 0x00000020 2107 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S 5 2108 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000040 2109 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S 6 2110 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000080 2111 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S 7 2112 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M 0x00000100 2113 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S 8 2114 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M 0x00000200 2115 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S 9 2116 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000400 2117 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S 10 2118 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M 0x00000800 2119 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S 11 2120 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M 0x00001000 2121 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S 12 2122 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M 0x00006000 2123 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S 13 2124 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M 0x00018000 2125 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S 15 2126 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M 0x001e0000 2127 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S 17 2128 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M 0x00200000 2129 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S 21 2130 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M 0x00c00000 2131 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S 22 2132 #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_M 0x01000000 2133 #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_S 24 2134 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_M 0x7e000000 2135 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_S 25 2136 2137 /* DWORD 1 */ 2138 #define HTT_TX_MSDU_EXT2_DESC_PWR_M 0x000000ff 2139 #define HTT_TX_MSDU_EXT2_DESC_PWR_S 0 2140 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M 0x000fff00 2141 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S 8 2142 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M 0x0ff00000 2143 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S 20 2144 #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_M 0x70000000 2145 #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_S 28 2146 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_M 0x80000000 2147 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_S 31 2148 2149 /* DWORD 2 */ 2150 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M 0x000000ff 2151 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S 0 2152 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_M 0x0000ff00 2153 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S 8 2154 #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_M 0xffff0000 2155 #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_S 16 2156 2157 /* DWORD 5 */ 2158 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M 0x00000001 2159 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S 0 2160 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M 0x00000002 2161 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S 1 2162 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M 0x00000004 2163 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S 2 2164 2165 /* DWORD 6 */ 2166 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M 0x0000FFFF 2167 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S 0 2168 2169 2170 /* DWORD 0 */ 2171 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_GET(_var) \ 2172 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ 2173 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S) 2174 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_SET(_var, _val) \ 2175 do { \ 2176 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR, _val); \ 2177 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S)); \ 2178 } while (0) 2179 2180 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ 2181 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M) >> \ 2182 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S) 2183 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ 2184 do { \ 2185 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK, _val); \ 2186 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S)); \ 2187 } while (0) 2188 2189 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_GET(_var) \ 2190 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M) >> \ 2191 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S) 2192 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_SET(_var, _val) \ 2193 do { \ 2194 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK, _val); \ 2195 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S)); \ 2196 } while (0) 2197 2198 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_GET(_var) \ 2199 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M) >> \ 2200 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S) 2201 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_SET(_var, _val) \ 2202 do { \ 2203 HTT_CHECK_SET_VAL( \ 2204 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE, _val); \ 2205 ((_var) |= ((_val) \ 2206 << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S)); \ 2207 } while (0) 2208 2209 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_GET(_var) \ 2210 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M) >> \ 2211 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S) 2212 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ 2213 do { \ 2214 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES, _val); \ 2215 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S)); \ 2216 } while (0) 2217 2218 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_GET(_var) \ 2219 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M) >> \ 2220 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S) 2221 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_SET(_var, _val) \ 2222 do { \ 2223 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO, _val); \ 2224 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S)); \ 2225 } while (0) 2226 2227 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ 2228 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ 2229 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S) 2230 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ 2231 do { \ 2232 HTT_CHECK_SET_VAL( \ 2233 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ 2234 ((_var) |= ((_val) \ 2235 << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ 2236 } while (0) 2237 2238 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ 2239 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ 2240 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S) 2241 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ 2242 do { \ 2243 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK, _val); \ 2244 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S)); \ 2245 } while (0) 2246 2247 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_GET(_var) \ 2248 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M) >> \ 2249 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S) 2250 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_SET(_var, _val) \ 2251 do { \ 2252 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE, _val); \ 2253 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S));\ 2254 } while (0) 2255 2256 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(_var) \ 2257 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M) >> \ 2258 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S) 2259 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(_var, _val) \ 2260 do { \ 2261 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS, _val); \ 2262 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S));\ 2263 } while (0) 2264 2265 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ 2266 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ 2267 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S) 2268 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ 2269 do { \ 2270 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ 2271 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S));\ 2272 } while (0) 2273 2274 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_GET(_var) \ 2275 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M) >> \ 2276 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S) 2277 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_SET(_var, _val) \ 2278 do { \ 2279 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ, _val); \ 2280 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S)); \ 2281 } while (0) 2282 2283 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_GET(_var) \ 2284 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M) >> \ 2285 HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S) 2286 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_SET(_var, _val) \ 2287 do { \ 2288 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC, _val); \ 2289 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S)); \ 2290 } while (0) 2291 2292 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_GET(_var) \ 2293 (((_var) & HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M) >> \ 2294 HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S) 2295 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_SET(_var, _val) \ 2296 do { \ 2297 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL, _val); \ 2298 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S)); \ 2299 } while (0) 2300 2301 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_GET(_var) \ 2302 (((_var) & HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M) >> \ 2303 HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S) 2304 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_SET(_var, _val) \ 2305 do { \ 2306 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE, _val); \ 2307 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S)); \ 2308 } while (0) 2309 2310 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_GET(_var) \ 2311 (((_var) & HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M) >> \ 2312 HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S) 2313 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_SET(_var, _val) \ 2314 do { \ 2315 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT, _val); \ 2316 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S)); \ 2317 } while (0) 2318 2319 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_GET(_var) \ 2320 (((_var) & HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M) >> \ 2321 HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S) 2322 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_SET(_var, _val) \ 2323 do { \ 2324 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX, _val); \ 2325 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S)); \ 2326 } while (0) 2327 2328 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_GET(_var) \ 2329 (((_var) & HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M) >> \ 2330 HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S) 2331 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_SET(_var, _val) \ 2332 do { \ 2333 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX, _val); \ 2334 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S)); \ 2335 } while (0) 2336 2337 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_GET(_var) \ 2338 (((_var) & HTT_TX_MSDU_EXT2_DESC_BW_MASK_M) >> \ 2339 HTT_TX_MSDU_EXT2_DESC_BW_MASK_S) 2340 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_SET(_var, _val) \ 2341 do { \ 2342 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_BW_MASK, _val); \ 2343 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_BW_MASK_S)); \ 2344 } while (0) 2345 2346 #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_GET(_var) \ 2347 (((_var) & HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_M) >> \ 2348 HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S) 2349 #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_SET(_var, _val) \ 2350 do { \ 2351 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK, _val); \ 2352 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S)); \ 2353 } while (0) 2354 2355 /* DWORD 1 */ 2356 #define HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) \ 2357 (((_var) & HTT_TX_MSDU_EXT2_DESC_PWR_M) >> \ 2358 HTT_TX_MSDU_EXT2_DESC_PWR_S) 2359 #define HTT_TX_MSDU_EXT2_DESC_PWR_GET(_var) \ 2360 (HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) | \ 2361 HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT2_DESC_PWR)) 2362 #define HTT_TX_MSDU_EXT2_DESC_PWR_SET(_var, _val) \ 2363 ((_var) |= (((_val) << HTT_TX_MSDU_EXT2_DESC_PWR_S)) & \ 2364 HTT_TX_MSDU_EXT2_DESC_PWR_M) 2365 2366 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_GET(_var) \ 2367 (((_var) & HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M) >> \ 2368 HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S) 2369 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_SET(_var, _val) \ 2370 do { \ 2371 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_MCS_MASK, _val); \ 2372 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S)); \ 2373 } while (0) 2374 2375 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_GET(_var) \ 2376 (((_var) & HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M) >> \ 2377 HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S) 2378 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_SET(_var, _val) \ 2379 do { \ 2380 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_NSS_MASK, _val); \ 2381 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S)); \ 2382 } while (0) 2383 2384 #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_GET(_var) \ 2385 (((_var) & HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_M) >> \ 2386 HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S) 2387 #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_SET(_var, _val) \ 2388 do { \ 2389 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE, _val); \ 2390 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S)); \ 2391 } while (0) 2392 2393 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_GET(_var) \ 2394 (((_var) & HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_M) >> \ 2395 HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S) 2396 #define HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_SET(_var, _val) \ 2397 do { \ 2398 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE, _val); \ 2399 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S)); \ 2400 } while (0) 2401 2402 /* DWORD 2 */ 2403 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_GET(_var) \ 2404 (((_var) & HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M) >> \ 2405 HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S) 2406 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_SET(_var, _val) \ 2407 do { \ 2408 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK, _val); \ 2409 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S)); \ 2410 } while (0) 2411 2412 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_GET(_var) \ 2413 (((_var) & HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_MASK_M) >> \ 2414 HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S) 2415 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_SET(_var, _val) \ 2416 do { \ 2417 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS, _val); \ 2418 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S)); \ 2419 } while (0) 2420 2421 #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_GET(_var) \ 2422 (((_var) & HTT_TX_MSDU_EXT2_DESC_CHANFREQ_MASK_M) >> \ 2423 HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S) 2424 #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_SET(_var, _val) \ 2425 do { \ 2426 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHANFREQ, _val); \ 2427 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S)); \ 2428 } while (0) 2429 2430 /* DWORD 5 */ 2431 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_GET(_var) \ 2432 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M) >> \ 2433 HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S) 2434 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_SET(_var, _val) \ 2435 do { \ 2436 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME, _val); \ 2437 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S)); \ 2438 } while (0) 2439 2440 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_GET(_var) \ 2441 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M) >> \ 2442 HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S) 2443 2444 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET(_var, _val) \ 2445 do { \ 2446 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE, _val); \ 2447 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S)); \ 2448 } while (0) 2449 2450 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_GET(_var) \ 2451 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M) >> \ 2452 HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S) 2453 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET(_var, _val) \ 2454 do { \ 2455 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID, _val); \ 2456 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S)); \ 2457 } while (0) 2458 2459 /* DWORD 6 */ 2460 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_GET(_var) \ 2461 (((_var) & HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M) >> \ 2462 HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S) 2463 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET(_var, _val) \ 2464 do { \ 2465 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE, _val); \ 2466 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S)); \ 2467 } while (0) 2468 2469 /* DWORD 7 */ 2470 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF 2471 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_S 0 2472 2473 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \ 2474 do { \ 2475 HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0, value); \ 2476 (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_S; \ 2477 } while (0) 2478 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \ 2479 (((word) & HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_S) 2480 2481 /* DWORD 8 */ 2482 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF 2483 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_S 0 2484 2485 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \ 2486 do { \ 2487 HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32, value); \ 2488 (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_S; \ 2489 } while (0) 2490 #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \ 2491 (((word) & HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_S) 2492 2493 #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_M 0x00000F00 2494 #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_S 8 2495 2496 #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_SET(word, value) \ 2497 do { \ 2498 HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER, value); \ 2499 (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_S; \ 2500 } while (0) 2501 #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_GET(word) \ 2502 (((word) & HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_M) >> HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_S) 2503 2504 #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF000 2505 #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 12 2506 2507 #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \ 2508 do { \ 2509 HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \ 2510 (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \ 2511 } while (0) 2512 #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \ 2513 (((word) & HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S) 2514 2515 typedef enum { 2516 HTT_TCL_METADATA_TYPE_PEER_BASED = 0, 2517 HTT_TCL_METADATA_TYPE_VDEV_BASED = 1, 2518 } htt_tcl_metadata_type; 2519 2520 /** 2521 * @brief HTT TCL command number format 2522 * @details 2523 * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and 2524 * available to firmware as tcl_exit_base->tcl_status_number. 2525 * For regular / multicast packets host will send vdev and mac id and for 2526 * NAWDS packets, host will send peer id. 2527 * A_UINT32 is used to avoid endianness conversion problems. 2528 * tcl_status_number size is 16 bits, hence only 16 bits can be used. 2529 */ 2530 2531 typedef struct { 2532 A_UINT32 2533 type: 1, /* vdev_id based or peer_id based */ 2534 rsvd: 31; 2535 } htt_tx_tcl_vdev_or_peer_t; 2536 2537 typedef struct { 2538 A_UINT32 2539 type: 1, /* vdev_id based or peer_id based */ 2540 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2541 vdev_id: 8, 2542 pdev_id: 2, 2543 host_inspected:1, 2544 opt_dp_ctrl: 1, /* 1 -> qdata consent pkt */ 2545 rsvd: 18; 2546 } htt_tx_tcl_vdev_metadata; 2547 2548 typedef struct { 2549 A_UINT32 2550 type: 1, /* vdev_id based or peer_id based */ 2551 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2552 peer_id: 14, 2553 rsvd: 16; 2554 } htt_tx_tcl_peer_metadata; 2555 2556 PREPACK struct htt_tx_tcl_metadata { 2557 union { 2558 htt_tx_tcl_vdev_or_peer_t vdev_or_peer; 2559 htt_tx_tcl_vdev_metadata vdev_meta; 2560 htt_tx_tcl_peer_metadata peer_meta; 2561 }; 2562 } POSTPACK; 2563 2564 /* DWORD 0 */ 2565 #define HTT_TX_TCL_METADATA_TYPE_M 0x00000001 2566 #define HTT_TX_TCL_METADATA_TYPE_S 0 2567 #define HTT_TX_TCL_METADATA_VALID_HTT_M 0x00000002 2568 #define HTT_TX_TCL_METADATA_VALID_HTT_S 1 2569 2570 /* VDEV metadata */ 2571 #define HTT_TX_TCL_METADATA_VDEV_ID_M 0x000003fc 2572 #define HTT_TX_TCL_METADATA_VDEV_ID_S 2 2573 #define HTT_TX_TCL_METADATA_PDEV_ID_M 0x00000c00 2574 #define HTT_TX_TCL_METADATA_PDEV_ID_S 10 2575 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_M 0x00001000 2576 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_S 12 2577 #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_M 0x00002000 2578 #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_S 13 2579 2580 /* PEER metadata */ 2581 #define HTT_TX_TCL_METADATA_PEER_ID_M 0x0000fffc 2582 #define HTT_TX_TCL_METADATA_PEER_ID_S 2 2583 2584 #define HTT_TX_TCL_METADATA_TYPE_GET(_var) \ 2585 (((_var) & HTT_TX_TCL_METADATA_TYPE_M) >> \ 2586 HTT_TX_TCL_METADATA_TYPE_S) 2587 #define HTT_TX_TCL_METADATA_TYPE_SET(_var, _val) \ 2588 do { \ 2589 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE, _val); \ 2590 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_S)); \ 2591 } while (0) 2592 2593 #define HTT_TX_TCL_METADATA_VALID_HTT_GET(_var) \ 2594 (((_var) & HTT_TX_TCL_METADATA_VALID_HTT_M) >> \ 2595 HTT_TX_TCL_METADATA_VALID_HTT_S) 2596 #define HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \ 2597 do { \ 2598 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VALID_HTT, _val); \ 2599 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VALID_HTT_S)); \ 2600 } while (0) 2601 2602 #define HTT_TX_TCL_METADATA_VDEV_ID_GET(_var) \ 2603 (((_var) & HTT_TX_TCL_METADATA_VDEV_ID_M) >> \ 2604 HTT_TX_TCL_METADATA_VDEV_ID_S) 2605 #define HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \ 2606 do { \ 2607 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VDEV_ID, _val); \ 2608 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VDEV_ID_S)); \ 2609 } while (0) 2610 2611 #define HTT_TX_TCL_METADATA_PDEV_ID_GET(_var) \ 2612 (((_var) & HTT_TX_TCL_METADATA_PDEV_ID_M) >> \ 2613 HTT_TX_TCL_METADATA_PDEV_ID_S) 2614 #define HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val) \ 2615 do { \ 2616 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PDEV_ID, _val); \ 2617 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PDEV_ID_S)); \ 2618 } while (0) 2619 2620 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_GET(_var) \ 2621 (((_var) & HTT_TX_TCL_METADATA_HOST_INSPECTED_M) >> \ 2622 HTT_TX_TCL_METADATA_HOST_INSPECTED_S) 2623 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \ 2624 do { \ 2625 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_HOST_INSPECTED, _val); \ 2626 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_HOST_INSPECTED_S)); \ 2627 } while (0) 2628 2629 #define HTT_TX_TCL_METADATA_PEER_ID_GET(_var) \ 2630 (((_var) & HTT_TX_TCL_METADATA_PEER_ID_M) >> \ 2631 HTT_TX_TCL_METADATA_PEER_ID_S) 2632 #define HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \ 2633 do { \ 2634 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PEER_ID, _val); \ 2635 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PEER_ID_S)); \ 2636 } while (0) 2637 2638 #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_GET(_var) \ 2639 (((_var) & HTT_TX_TCL_METADATA_OPT_DP_CTRL_M) >> \ 2640 HTT_TX_TCL_METADATA_OPT_DP_CTRL_S) 2641 #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_SET(_var, _val) \ 2642 do { \ 2643 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_OPT_DP_CTRL, _val); \ 2644 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_OPT_DP_CTRL_S)); \ 2645 } while (0) 2646 2647 /*------------------------------------------------------------------ 2648 * V2 Version of TCL Data Command 2649 * V2 Version to support peer_id, vdev_id, svc_class_id and 2650 * MLO global_seq all flavours of TCL Data Cmd. 2651 *-----------------------------------------------------------------*/ 2652 2653 typedef enum { 2654 HTT_TCL_METADATA_V2_TYPE_PEER_BASED = 0, 2655 HTT_TCL_METADATA_V2_TYPE_VDEV_BASED = 1, 2656 HTT_TCL_METADATA_V2_TYPE_SVC_ID_BASED = 2, 2657 HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED = 3, 2658 } htt_tcl_metadata_type_v2; 2659 2660 /** 2661 * @brief HTT TCL command number format 2662 * @details 2663 * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and 2664 * available to firmware as tcl_exit_base->tcl_status_number. 2665 * A_UINT32 is used to avoid endianness conversion problems. 2666 * tcl_status_number size is 16 bits, hence only 16 bits can be used. 2667 */ 2668 typedef struct { 2669 A_UINT32 2670 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2671 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2672 vdev_id: 8, 2673 pdev_id: 2, 2674 host_inspected:1, 2675 rsvd: 2, 2676 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2677 } htt_tx_tcl_vdev_metadata_v2; 2678 2679 typedef struct { 2680 A_UINT32 2681 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2682 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2683 peer_id: 13, 2684 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2685 } htt_tx_tcl_peer_metadata_v2; 2686 2687 typedef struct { 2688 A_UINT32 2689 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2690 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2691 svc_class_id: 8, 2692 ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */ 2693 rsvd: 2, 2694 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2695 } htt_tx_tcl_svc_class_id_metadata; 2696 2697 typedef struct { 2698 A_UINT32 2699 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2700 host_inspected: 1, 2701 global_seq_no: 12, 2702 rsvd: 1, 2703 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2704 } htt_tx_tcl_global_seq_metadata; 2705 2706 PREPACK struct htt_tx_tcl_metadata_v2 { 2707 union { 2708 htt_tx_tcl_vdev_metadata_v2 vdev_meta_v2; 2709 htt_tx_tcl_peer_metadata_v2 peer_meta_v2; 2710 htt_tx_tcl_svc_class_id_metadata svc_class_id_meta; 2711 htt_tx_tcl_global_seq_metadata global_seq_meta; 2712 }; 2713 } POSTPACK; 2714 2715 /* DWORD 0 */ 2716 #define HTT_TX_TCL_METADATA_TYPE_V2_M 0x00000003 2717 #define HTT_TX_TCL_METADATA_TYPE_V2_S 0 2718 2719 /* Valid htt ext for V2 tcl data cmd used by VDEV, PEER and SVC_ID meta */ 2720 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M 0x00000004 2721 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S 2 2722 2723 /* VDEV V2 metadata */ 2724 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_M 0x000007f8 2725 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_S 3 2726 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_M 0x00001800 2727 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_S 11 2728 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M 0x00002000 2729 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S 13 2730 2731 /* PEER V2 metadata */ 2732 #define HTT_TX_TCL_METADATA_V2_PEER_ID_M 0x0000fff8 2733 #define HTT_TX_TCL_METADATA_V2_PEER_ID_S 3 2734 2735 /* SVC_CLASS_ID metadata */ 2736 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_M 0x000007f8 2737 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_S 3 2738 2739 /* Global Seq no metadata */ 2740 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M 0x00000004 2741 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S 2 2742 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M 0x00007ff8 2743 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S 3 2744 2745 2746 /*----- Get and Set V2 type field in Vdev, Peer, Svc_Class_Id, Global_seq_no */ 2747 #define HTT_TX_TCL_METADATA_TYPE_V2_GET(_var) \ 2748 (((_var) & HTT_TX_TCL_METADATA_TYPE_V2_M) >> \ 2749 HTT_TX_TCL_METADATA_TYPE_V2_S) 2750 #define HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val) \ 2751 do { \ 2752 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE_V2, _val); \ 2753 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_V2_S)); \ 2754 } while (0) 2755 2756 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_GET(_var) \ 2757 (((_var) & HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M) >> \ 2758 HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S) 2759 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val) \ 2760 do { \ 2761 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID, _val); \ 2762 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S)); \ 2763 } while (0) 2764 2765 /*----- Get and Set V2 type field in Vdev meta fields ----*/ 2766 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_GET(_var) \ 2767 (((_var) & HTT_TX_TCL_METADATA_V2_VDEV_ID_M) >> \ 2768 HTT_TX_TCL_METADATA_V2_VDEV_ID_S) 2769 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val) \ 2770 do { \ 2771 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VDEV_ID, _val); \ 2772 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VDEV_ID_S)); \ 2773 } while (0) 2774 2775 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_GET(_var) \ 2776 (((_var) & HTT_TX_TCL_METADATA_V2_PDEV_ID_M) >> \ 2777 HTT_TX_TCL_METADATA_V2_PDEV_ID_S) 2778 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val) \ 2779 do { \ 2780 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PDEV_ID, _val); \ 2781 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PDEV_ID_S)); \ 2782 } while (0) 2783 2784 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_GET(_var) \ 2785 (((_var) & HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M) >> \ 2786 HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S) 2787 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val) \ 2788 do { \ 2789 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_HOST_INSPECTED, _val); \ 2790 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S)); \ 2791 } while (0) 2792 2793 /*----- Get and Set V2 type field in Peer meta fields ----*/ 2794 #define HTT_TX_TCL_METADATA_V2_PEER_ID_GET(_var) \ 2795 (((_var) & HTT_TX_TCL_METADATA_V2_PEER_ID_M) >> \ 2796 HTT_TX_TCL_METADATA_V2_PEER_ID_S) 2797 #define HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val) \ 2798 do { \ 2799 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PEER_ID, _val); \ 2800 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PEER_ID_S)); \ 2801 } while (0) 2802 2803 /*----- Get and Set V2 type field in Service Class fields ----*/ 2804 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_GET(_var) \ 2805 (((_var) & HTT_TX_TCL_METADATA_SVC_CLASS_ID_M) >> \ 2806 HTT_TX_TCL_METADATA_SVC_CLASS_ID_S) 2807 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_SET(_var, _val) \ 2808 do { \ 2809 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_SVC_CLASS_ID, _val); \ 2810 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_SVC_CLASS_ID_S)); \ 2811 } while (0) 2812 2813 /*----- Get and Set V2 type field in Global sequence fields ----*/ 2814 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_GET(_var) \ 2815 (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M) >> \ 2816 HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S) 2817 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(_var, _val) \ 2818 do { \ 2819 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED, _val); \ 2820 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S)); \ 2821 } while (0) 2822 2823 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_GET(_var) \ 2824 (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M) >> \ 2825 HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S) 2826 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(_var, _val) \ 2827 do { \ 2828 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_NO, _val); \ 2829 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S)); \ 2830 } while (0) 2831 2832 /*------------------------------------------------------------------ 2833 * End V2 Version of TCL Data Command 2834 *-----------------------------------------------------------------*/ 2835 2836 typedef enum { 2837 HTT_TX_FW2WBM_TX_STATUS_OK, 2838 HTT_TX_FW2WBM_TX_STATUS_DROP, 2839 HTT_TX_FW2WBM_TX_STATUS_TTL, 2840 HTT_TX_FW2WBM_TX_STATUS_REINJECT, 2841 HTT_TX_FW2WBM_TX_STATUS_INSPECT, 2842 HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, 2843 HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH, 2844 2845 HTT_TX_FW2WBM_TX_STATUS_MAX 2846 } htt_tx_fw2wbm_tx_status_t; 2847 2848 typedef enum { 2849 HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, /* deprecated */ 2850 HTT_TX_FW2WBM_REINJECT_REASON_RAW_ENCAP_EXP /* current */ = 2851 HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, 2852 HTT_TX_FW2WBM_REINJECT_REASON_INJECT_VIA_EXP, 2853 HTT_TX_FW2WBM_REINJECT_REASON_MCAST, 2854 HTT_TX_FW2WBM_REINJECT_REASON_ARP, 2855 HTT_TX_FW2WBM_REINJECT_REASON_DHCP, 2856 HTT_TX_FW2WBM_REINJECT_REASON_FLOW_CONTROL, 2857 HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST, 2858 HTT_TX_FW2WBM_REINJECT_REASON_SAWF_SVC_CLASS_ID_ABSENT, 2859 HTT_TX_FW2WBM_REINJECT_REASON_OPT_DP_CTRL, /* tx qdata packet */ 2860 2861 HTT_TX_FW2WBM_REINJECT_REASON_MAX, 2862 } htt_tx_fw2wbm_reinject_reason_t; 2863 2864 /** 2865 * @brief HTT TX WBM Completion from firmware to host 2866 * @details 2867 * This structure is passed from firmware to host overlaid on wbm_release_ring 2868 * DWORD 3 and 4 for software based completions (Exception frames and 2869 * TQM bypass frames) 2870 * For software based completions, wbm_release_ring->release_source_module will 2871 * be set to release_source_fw 2872 */ 2873 PREPACK struct htt_tx_wbm_completion { 2874 A_UINT32 2875 sch_cmd_id: 24, 2876 exception_frame: 1, /* If set, this packet was queued via exception path */ 2877 rsvd0_31_25: 7; 2878 2879 A_UINT32 2880 ack_frame_rssi: 8, /* If this frame is removed as the result of the 2881 * reception of an ACK or BA, this field indicates 2882 * the RSSI of the received ACK or BA frame. 2883 * When the frame is removed as result of a direct 2884 * remove command from the SW, this field is set 2885 * to 0x0 (which is never a valid value when real 2886 * RSSI is available). 2887 * Units: dB w.r.t noise floor 2888 */ 2889 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2890 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2891 rsvd1_31_16: 16; 2892 } POSTPACK; 2893 2894 /* DWORD 0 */ 2895 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M 0x00ffffff 2896 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S 0 2897 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_M 0x01000000 2898 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_S 24 2899 2900 /* DWORD 1 */ 2901 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_M 0x000000ff 2902 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_S 0 2903 #define HTT_TX_WBM_COMPLETION_TX_STATUS_M 0x00000f00 2904 #define HTT_TX_WBM_COMPLETION_TX_STATUS_S 8 2905 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_M 0x0000f000 2906 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_S 12 2907 2908 /* DWORD 0 */ 2909 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_GET(_var) \ 2910 (((_var) & HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M) >> \ 2911 HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S) 2912 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_SET(_var, _val) \ 2913 do { \ 2914 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_SCH_CMD_ID, _val); \ 2915 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S)); \ 2916 } while (0) 2917 2918 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_GET(_var) \ 2919 (((_var) & HTT_TX_WBM_COMPLETION_EXP_FRAME_M) >> \ 2920 HTT_TX_WBM_COMPLETION_EXP_FRAME_S) 2921 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_SET(_var, _val) \ 2922 do { \ 2923 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_EXP_FRAME, _val); \ 2924 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_EXP_FRAME_S)); \ 2925 } while (0) 2926 2927 /* DWORD 1 */ 2928 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_GET(_var) \ 2929 (((_var) & HTT_TX_WBM_COMPLETION_ACK_RSSI_M) >> \ 2930 HTT_TX_WBM_COMPLETION_ACK_RSSI_S) 2931 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_SET(_var, _val) \ 2932 do { \ 2933 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_ACK_RSSI, _val); \ 2934 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_ACK_RSSI_S)); \ 2935 } while (0) 2936 2937 #define HTT_TX_WBM_COMPLETION_TX_STATUS_GET(_var) \ 2938 (((_var) & HTT_TX_WBM_COMPLETION_TX_STATUS_M) >> \ 2939 HTT_TX_WBM_COMPLETION_TX_STATUS_S) 2940 #define HTT_TX_WBM_COMPLETION_TX_STATUS_SET(_var, _val) \ 2941 do { \ 2942 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_TX_STATUS, _val); \ 2943 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_TX_STATUS_S)); \ 2944 } while (0) 2945 2946 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_GET(_var) \ 2947 (((_var) & HTT_TX_WBM_COMPLETION_REINJECT_REASON_M) >> \ 2948 HTT_TX_WBM_COMPLETION_REINJECT_REASON_S) 2949 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_SET(_var, _val) \ 2950 do { \ 2951 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_REINJECT_REASON, _val); \ 2952 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_REINJECT_REASON_S)); \ 2953 } while (0) 2954 2955 /** 2956 * @brief HTT TX WBM Completion from firmware to host 2957 * @details 2958 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 2959 * (WBM) offload HW. 2960 * This structure is passed from firmware to host overlaid on wbm_release_ring 2961 * For software based completions, release_source_module will 2962 * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using 2963 * struct wbm_release_ring and then switch to this after looking at 2964 * release_source_module. 2965 */ 2966 PREPACK struct htt_tx_wbm_completion_v2 { 2967 A_UINT32 2968 used_by_hw0; /* Refer to struct wbm_release_ring */ 2969 A_UINT32 2970 used_by_hw1; /* Refer to struct wbm_release_ring */ 2971 A_UINT32 2972 used_by_hw2: 9, /* Refer to struct wbm_release_ring */ 2973 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2974 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2975 exception_frame: 1, 2976 transmit_count: 7, /* Refer to struct wbm_release_ring */ 2977 rsvd0: 5, /* For future use */ 2978 used_by_hw4: 1, /* wbm_internal_error bit being used by HW */ 2979 rsvd1: 1; /* For future use */ 2980 A_UINT32 2981 data0: 32; /* data0,1 and 2 changes based on tx_status type 2982 * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 2983 * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used. 2984 * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used. 2985 * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used. 2986 */ 2987 A_UINT32 2988 data1: 32; 2989 A_UINT32 2990 data2: 32; 2991 A_UINT32 2992 used_by_hw3; /* Refer to struct wbm_release_ring */ 2993 } POSTPACK; 2994 2995 /* DWORD 1, 2 and part of 3 are accessed via HW header files */ 2996 /* DWORD 3 */ 2997 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M 0x00001e00 2998 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S 9 2999 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M 0x0001e000 3000 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13 3001 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000 3002 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17 3003 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000 3004 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18 3005 3006 /* DWORD 3 */ 3007 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \ 3008 (((_var) & HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M) >> \ 3009 HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S) 3010 3011 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_SET(_var, _val) \ 3012 do { \ 3013 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TX_STATUS, _val); \ 3014 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S)); \ 3015 } while (0) 3016 3017 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(_var) \ 3018 (((_var) & HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M) >> \ 3019 HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S) 3020 3021 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_SET(_var, _val) \ 3022 do { \ 3023 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON, _val); \ 3024 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S)); \ 3025 } while (0) 3026 3027 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_GET(_var) \ 3028 (((_var) & HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M) >> \ 3029 HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S) 3030 3031 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_SET(_var, _val) \ 3032 do { \ 3033 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_EXP_FRAME, _val); \ 3034 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \ 3035 } while (0) 3036 3037 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \ 3038 (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \ 3039 HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S) 3040 3041 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \ 3042 do { \ 3043 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \ 3044 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \ 3045 } while (0) 3046 3047 /** 3048 * @brief HTT TX WBM Completion from firmware to host (V3) 3049 * @details 3050 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3051 * (WBM) offload HW. 3052 * This structure is passed from firmware to host overlaid on wbm_release_ring 3053 * For software based completions, release_source_module will 3054 * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using 3055 * struct wbm_release_ring and then switch to this after looking at 3056 * release_source_module. 3057 * Due to overlap with WBM block, htt_tx_wbm_completion_v3 will be used 3058 * by new generations of targets. 3059 */ 3060 PREPACK struct htt_tx_wbm_completion_v3 { 3061 A_UINT32 3062 used_by_hw0; /* Refer to struct wbm_release_ring */ 3063 A_UINT32 3064 used_by_hw1; /* Refer to struct wbm_release_ring */ 3065 A_UINT32 3066 used_by_hw2: 13, /* Refer to struct wbm_release_ring */ 3067 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 3068 used_by_hw3: 15; 3069 A_UINT32 3070 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 3071 exception_frame: 1, 3072 transmit_count: 7, /* Refer to struct wbm_release_ring */ 3073 rsvd0: 20; /* For future use */ 3074 A_UINT32 3075 data0: 32; /* data0,1 and 2 changes based on tx_status type 3076 * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 3077 * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used. 3078 * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used. 3079 * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used. 3080 */ 3081 A_UINT32 3082 data1: 32; 3083 A_UINT32 3084 data2: 32; 3085 A_UINT32 3086 rsvd1: 20, 3087 used_by_hw4: 12; /* Refer to struct wbm_release_ring */ 3088 } POSTPACK; 3089 3090 /* DWORD 3 */ 3091 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000 3092 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13 3093 3094 /* DWORD 4 */ 3095 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F 3096 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0 3097 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010 3098 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4 3099 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0 3100 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5 3101 3102 3103 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \ 3104 (((_var) & HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M) >> \ 3105 HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S) 3106 3107 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_SET(_var, _val) \ 3108 do { \ 3109 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TX_STATUS, _val); \ 3110 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S)); \ 3111 } while (0) 3112 3113 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(_var) \ 3114 (((_var) & HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M) >> \ 3115 HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S) 3116 3117 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_SET(_var, _val) \ 3118 do { \ 3119 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON, _val); \ 3120 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S)); \ 3121 } while (0) 3122 3123 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_GET(_var) \ 3124 (((_var) & HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M) >> \ 3125 HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S) 3126 3127 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_SET(_var, _val) \ 3128 do { \ 3129 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_EXP_FRAME, _val); \ 3130 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \ 3131 } while (0) 3132 3133 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \ 3134 (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \ 3135 HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S) 3136 3137 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \ 3138 do { \ 3139 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \ 3140 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \ 3141 } while (0) 3142 3143 3144 typedef enum { 3145 TX_FRAME_TYPE_UNDEFINED = 0, 3146 TX_FRAME_TYPE_EAPOL = 1, 3147 } htt_tx_wbm_status_frame_type; 3148 3149 /** 3150 * @brief HTT TX WBM transmit status from firmware to host 3151 * @details 3152 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3153 * (WBM) offload HW. 3154 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3155 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 3156 * or HTT_TX_FW2WBM_TX_STATUS_TTL 3157 */ 3158 PREPACK struct htt_tx_wbm_transmit_status { 3159 A_UINT32 3160 sch_cmd_id: 24, 3161 ack_frame_rssi: 8; /* If this frame is removed as the result of the 3162 * reception of an ACK or BA, this field indicates 3163 * the RSSI of the received ACK or BA frame. 3164 * When the frame is removed as result of a direct 3165 * remove command from the SW, this field is set 3166 * to 0x0 (which is never a valid value when real 3167 * RSSI is available). 3168 * Units: dB w.r.t noise floor 3169 */ 3170 A_UINT32 3171 sw_peer_id: 16, 3172 tid_num: 5, 3173 valid: 1, /* If this "valid" flag is set, the sw_peer_id 3174 * and tid_num fields contain valid data. 3175 * If this "valid" flag is not set, the 3176 * sw_peer_id and tid_num fields must be ignored. 3177 */ 3178 mcast: 1, 3179 mcast_valid: 1, /* If this "mcast_valid" is set, the mcast field 3180 * contains valid data. 3181 */ 3182 frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */ 3183 transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the 3184 * transmit_count field in struct 3185 * htt_tx_wbm_completion_vx has valid data. 3186 */ 3187 reserved: 3; 3188 A_UINT32 3189 ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast 3190 * packets in the wbm completion path 3191 */ 3192 } POSTPACK; 3193 3194 /* DWORD 4 */ 3195 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M 0x00ffffff 3196 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S 0 3197 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M 0xff000000 3198 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S 24 3199 3200 /* DWORD 5 */ 3201 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M 0x0000ffff 3202 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S 0 3203 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_M 0x001f0000 3204 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_S 16 3205 #define HTT_TX_WBM_COMPLETION_V2_VALID_M 0x00200000 3206 #define HTT_TX_WBM_COMPLETION_V2_VALID_S 21 3207 #define HTT_TX_WBM_COMPLETION_V2_MCAST_M 0x00400000 3208 #define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22 3209 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000 3210 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23 3211 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000 3212 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24 3213 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000 3214 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28 3215 3216 /* DWORD 4 */ 3217 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \ 3218 (((_var) & HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M) >> \ 3219 HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S) 3220 3221 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_SET(_var, _val) \ 3222 do { \ 3223 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID, _val); \ 3224 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S)); \ 3225 } while (0) 3226 3227 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var) \ 3228 (((_var) & HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M) >> \ 3229 HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S) 3230 3231 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_SET(_var, _val) \ 3232 do { \ 3233 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI, _val); \ 3234 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S)); \ 3235 } while (0) 3236 3237 /* DWORD 5 */ 3238 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var) \ 3239 (((_var) & HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M) >> \ 3240 HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S) 3241 3242 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_SET(_var, _val) \ 3243 do { \ 3244 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID, _val); \ 3245 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S)); \ 3246 } while (0) 3247 3248 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var) \ 3249 (((_var) & HTT_TX_WBM_COMPLETION_V2_TID_NUM_M) >> \ 3250 HTT_TX_WBM_COMPLETION_V2_TID_NUM_S) 3251 3252 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_SET(_var, _val) \ 3253 do { \ 3254 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TID_NUM, _val); \ 3255 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TID_NUM_S)); \ 3256 } while (0) 3257 3258 #define HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var) \ 3259 (((_var) & HTT_TX_WBM_COMPLETION_V2_VALID_M) >> \ 3260 HTT_TX_WBM_COMPLETION_V2_VALID_S) 3261 3262 #define HTT_TX_WBM_COMPLETION_V2_VALID_SET(_var, _val) \ 3263 do { \ 3264 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VALID, _val); \ 3265 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VALID_S)); \ 3266 } while (0) 3267 3268 #define HTT_TX_WBM_COMPLETION_V2_MCAST_GET(_var) \ 3269 (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_M) >> \ 3270 HTT_TX_WBM_COMPLETION_V2_MCAST_S) 3271 3272 #define HTT_TX_WBM_COMPLETION_V2_MCAST_SET(_var, _val) \ 3273 do { \ 3274 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST, _val); \ 3275 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_S)); \ 3276 } while (0) 3277 3278 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_GET(_var) \ 3279 (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M) >> \ 3280 HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S) 3281 3282 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_SET(_var, _val) \ 3283 do { \ 3284 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ 3285 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \ 3286 } while (0) 3287 3288 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \ 3289 (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \ 3290 HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S) 3291 3292 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \ 3293 do { \ 3294 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \ 3295 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \ 3296 3297 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \ 3298 (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \ 3299 HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S) 3300 3301 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \ 3302 do { \ 3303 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ 3304 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \ 3305 } while (0) 3306 3307 3308 /** 3309 * @brief HTT TX WBM reinject status from firmware to host 3310 * @details 3311 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3312 * (WBM) offload HW. 3313 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3314 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_REINJECT. 3315 */ 3316 PREPACK struct htt_tx_wbm_reinject_status { 3317 A_UINT32 3318 sw_peer_id : 16, 3319 data_length : 16; 3320 A_UINT32 3321 tid : 5, 3322 msduq_idx : 4, 3323 reserved1 : 23; 3324 A_UINT32 3325 reserved2: 32; 3326 } POSTPACK; 3327 3328 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_M 0x0000ffff 3329 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_S 0 3330 #define HTT_TX_WBM_REINJECT_DATA_LEN_M 0xffff0000 3331 #define HTT_TX_WBM_REINJECT_DATA_LEN_S 16 3332 3333 #define HTT_TX_WBM_REINJECT_TID_M 0x0000001f 3334 #define HTT_TX_WBM_REINJECT_TID_S 0 3335 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_M 0x000001e0 3336 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_S 5 3337 3338 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_GET(_var)\ 3339 (((_var) & HTT_TX_WBM_REINJECT_SW_PEER_ID_M) >>\ 3340 HTT_TX_WBM_REINJECT_SW_PEER_ID_S)\ 3341 3342 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_SET(_var, _val)\ 3343 do {\ 3344 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_SW_PEER_ID, _val); \ 3345 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_SW_PEER_ID_S));\ 3346 } while(0) 3347 3348 #define HTT_TX_WBM_REINJECT_DATA_LEN_GET(_var)\ 3349 (((_var) & HTT_TX_WBM_REINJECT_DATA_LEN_M) >>\ 3350 HTT_TX_WBM_REINJECT_DATA_LEN_S)\ 3351 3352 #define HTT_TX_WBM_REINJECT_DATA_LEN_SET(_var, _val)\ 3353 do {\ 3354 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_DATA_LEN, _val); \ 3355 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_DATA_LEN_S));\ 3356 } while(0) 3357 3358 #define HTT_TX_WBM_REINJECT_TID_GET(_var)\ 3359 (((_var) & HTT_TX_WBM_REINJECT_TID_M) >>\ 3360 HTT_TX_WBM_REINJECT_TID_S)\ 3361 3362 #define HTT_TX_WBM_REINJECT_TID_SET(_var, _val)\ 3363 do {\ 3364 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_TID, _val); \ 3365 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_TID_S));\ 3366 } while(0) 3367 3368 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_GET(_var)\ 3369 (((_var) & HTT_TX_WBM_REINJECT_MSDUQ_ID_M) >>\ 3370 HTT_TX_WBM_REINJECT_MSDUQ_ID_S)\ 3371 3372 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_SET(_var, _val)\ 3373 do {\ 3374 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_MSDUQ_ID, _val); \ 3375 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_MSDUQ_ID_S));\ 3376 } while(0) 3377 3378 3379 3380 3381 3382 3383 3384 /** 3385 * @brief HTT TX WBM multicast echo check notification from firmware to host 3386 * @details 3387 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3388 * (WBM) offload HW. 3389 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3390 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY. 3391 * FW sends SA addresses to host for all multicast/broadcast packets received on 3392 * STA side. 3393 */ 3394 PREPACK struct htt_tx_wbm_mec_addr_notify { 3395 A_UINT32 3396 mec_sa_addr_31_0; 3397 A_UINT32 3398 mec_sa_addr_47_32: 16, 3399 sa_ast_index: 16; 3400 A_UINT32 3401 vdev_id: 8, 3402 reserved0: 24; 3403 3404 } POSTPACK; 3405 3406 /* DWORD 4 - mec_sa_addr_31_0 */ 3407 /* DWORD 5 */ 3408 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M 0x0000ffff 3409 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S 0 3410 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M 0xffff0000 3411 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S 16 3412 3413 /* DWORD 6 */ 3414 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M 0x000000ff 3415 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S 0 3416 3417 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_GET(_var) \ 3418 (((_var) & HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M) >> \ 3419 HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S) 3420 3421 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_SET(_var, _val) \ 3422 do { \ 3423 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32, _val); \ 3424 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S)); \ 3425 } while (0) 3426 3427 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_GET(_var) \ 3428 (((_var) & HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M) >> \ 3429 HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S) 3430 3431 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_SET(_var, _val) \ 3432 do { \ 3433 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX, _val); \ 3434 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S)); \ 3435 } while (0) 3436 3437 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var) \ 3438 (((_var) & HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M) >> \ 3439 HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S) 3440 3441 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_SET(_var, _val) \ 3442 do { \ 3443 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VDEV_ID, _val); \ 3444 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S)); \ 3445 } while (0) 3446 3447 typedef enum { 3448 TX_FLOW_PRIORITY_BE, 3449 TX_FLOW_PRIORITY_HIGH, 3450 TX_FLOW_PRIORITY_LOW, 3451 } htt_tx_flow_priority_t; 3452 3453 typedef enum { 3454 TX_FLOW_LATENCY_SENSITIVE, 3455 TX_FLOW_LATENCY_INSENSITIVE, 3456 } htt_tx_flow_latency_t; 3457 3458 typedef enum { 3459 TX_FLOW_BEST_EFFORT_TRAFFIC, 3460 TX_FLOW_INTERACTIVE_TRAFFIC, 3461 TX_FLOW_PERIODIC_TRAFFIC, 3462 TX_FLOW_BURSTY_TRAFFIC, 3463 TX_FLOW_OVER_SUBSCRIBED_TRAFFIC, 3464 } htt_tx_flow_traffic_pattern_t; 3465 3466 /** 3467 * @brief HTT TX Flow search metadata format 3468 * @details 3469 * Host will set this metadata in flow table's flow search entry along with 3470 * to_tqm_if_m0_fw. It indicates to forward the first MSDU to both the 3471 * firmware and TQM ring if the flow search entry wins. 3472 * This metadata is available to firmware in that first MSDU's 3473 * tcl_exit_base->meta_data_fse. Firmware uses this metadata to map a new flow 3474 * to one of the available flows for specific tid and returns the tqm flow 3475 * pointer as part of htt_tx_map_flow_info message. 3476 */ 3477 PREPACK struct htt_tx_flow_metadata { 3478 A_UINT32 3479 rsvd0_1_0: 2, 3480 tid: 4, 3481 priority: 3, /* Takes enum values of htt_tx_flow_priority_t */ 3482 traffic_pattern: 3, /* Takes enum values of htt_tx_flow_traffic_pattern_t */ 3483 tid_override: 1, /* If set, tid field in this struct is the final tid. 3484 * Else choose final tid based on latency, priority. 3485 */ 3486 dedicated_flowq: 1, /* Dedicated flowq per 5 tuple flow. */ 3487 latency_sensitive: 2, /* Takes enum values of htt_tx_flow_latency_t */ 3488 host_flow_identifier: 16; /* Used by host to map flow metadata with flow entry */ 3489 } POSTPACK; 3490 3491 /* DWORD 0 */ 3492 #define HTT_TX_FLOW_METADATA_TID_M 0x0000003c 3493 #define HTT_TX_FLOW_METADATA_TID_S 2 3494 #define HTT_TX_FLOW_METADATA_PRIORITY_M 0x000001c0 3495 #define HTT_TX_FLOW_METADATA_PRIORITY_S 6 3496 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M 0x00000e00 3497 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S 9 3498 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_M 0x00001000 3499 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_S 12 3500 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M 0x00002000 3501 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S 13 3502 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M 0x0000c000 3503 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S 14 3504 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M 0xffff0000 3505 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S 16 3506 3507 /* DWORD 0 */ 3508 #define HTT_TX_FLOW_METADATA_TID_GET(_var) \ 3509 (((_var) & HTT_TX_FLOW_METADATA_TID_M) >> \ 3510 HTT_TX_FLOW_METADATA_TID_S) 3511 #define HTT_TX_FLOW_METADATA_TID_SET(_var, _val) \ 3512 do { \ 3513 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID, _val); \ 3514 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_S)); \ 3515 } while (0) 3516 3517 #define HTT_TX_FLOW_METADATA_PRIORITY_GET(_var) \ 3518 (((_var) & HTT_TX_FLOW_PRIORITY_M) >> \ 3519 HTT_TX_FLOW_METADATA_PRIORITY_S) 3520 #define HTT_TX_FLOW_METADATA_PRIORITY_SET(_var, _val) \ 3521 do { \ 3522 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_PRIORITY, _val); \ 3523 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_PRIORITY_S)); \ 3524 } while (0) 3525 3526 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_GET(_var) \ 3527 (((_var) & HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M) >> \ 3528 HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S) 3529 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_SET(_var, _val) \ 3530 do { \ 3531 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN, _val); \ 3532 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S)); \ 3533 } while (0) 3534 3535 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_GET(_var) \ 3536 (((_var) & HTT_TX_FLOW_METADATA_TID_OVERRIDE_M) >> \ 3537 HTT_TX_FLOW_METADATA_TID_OVERRIDE_S) 3538 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_SET(_var, _val) \ 3539 do { \ 3540 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID_OVERRIDE, _val); \ 3541 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_OVERRIDE_S)); \ 3542 } while (0) 3543 3544 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_GET(_var) \ 3545 (((_var) & HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M) >> \ 3546 HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S) 3547 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_SET(_var, _val) \ 3548 do { \ 3549 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ, _val); \ 3550 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S)); \ 3551 } while (0) 3552 3553 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_GET(_var) \ 3554 (((_var) & HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M) >> \ 3555 HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S) 3556 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_SET(_var, _val) \ 3557 do { \ 3558 HTT_CHECK_SET_VAL(HTT_TX_FLOW_LATENCY_SENSITIVE, _val); \ 3559 ((_var) |= ((_val) << HTT_TX_FLOW_LATENCY_SENSITIVE_S)); \ 3560 } while (0) 3561 3562 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_GET(_var) \ 3563 (((_var) & HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M) >> \ 3564 HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S) 3565 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_SET(_var, _val) \ 3566 do { \ 3567 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_HOST_FLOW_ID, _val); \ 3568 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S)); \ 3569 } while (0) 3570 3571 3572 /** 3573 * @brief host -> target ADD WDS Entry 3574 * 3575 * MSG_TYPE => HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY 3576 * 3577 * @brief host -> target DELETE WDS Entry 3578 * 3579 * MSG_TYPE => HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY 3580 * 3581 * @details 3582 * HTT wds entry from source port learning 3583 * Host will learn wds entries from rx and send this message to firmware 3584 * to enable firmware to configure/delete AST entries for wds clients. 3585 * Firmware creates Source address's AST entry with Transmit MAC's peer_id 3586 * and when SA's entry is deleted, firmware removes this AST entry 3587 * 3588 * The message would appear as follows: 3589 * 3590 * |31 30|29 |17 16|15 8|7 0| 3591 * |----------------+----------------+----------------+----------------| 3592 * | rsvd0 |PDVID| vdev_id | msg_type | 3593 * |-------------------------------------------------------------------| 3594 * | sa_addr_31_0 | 3595 * |-------------------------------------------------------------------| 3596 * | | ta_peer_id | sa_addr_47_32 | 3597 * |-------------------------------------------------------------------| 3598 * Where PDVID = pdev_id 3599 * 3600 * The message is interpreted as follows: 3601 * 3602 * dword0 - b'0:7 - msg_type: This will be set to 3603 * 0xd (HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY) or 3604 * 0xe (HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY) 3605 * 3606 * dword0 - b'8:15 - vdev_id 3607 * 3608 * dword0 - b'16:17 - pdev_id 3609 * 3610 * dword0 - b'18:31 - rsvd10: Reserved for future use 3611 * 3612 * dword1 - b'0:31 - sa_addr_31_0: Lower 32 bits of source mac address 3613 * 3614 * dword2 - b'0:15 - sa_addr_47_32: Upper 16 bits of source mac address 3615 * 3616 * dword2 - b'16:19 - ta_peer_id: peer id of Transmit MAC 3617 */ 3618 3619 PREPACK struct htt_wds_entry { 3620 A_UINT32 3621 msg_type: 8, 3622 vdev_id: 8, 3623 pdev_id: 2, 3624 rsvd0: 14; 3625 A_UINT32 sa_addr_31_0; 3626 A_UINT32 3627 sa_addr_47_32: 16, 3628 ta_peer_id: 14, 3629 rsvd2: 2; 3630 } POSTPACK; 3631 3632 /* DWORD 0 */ 3633 #define HTT_WDS_ENTRY_VDEV_ID_M 0x0000ff00 3634 #define HTT_WDS_ENTRY_VDEV_ID_S 8 3635 #define HTT_WDS_ENTRY_PDEV_ID_M 0x00030000 3636 #define HTT_WDS_ENTRY_PDEV_ID_S 16 3637 3638 /* DWORD 2 */ 3639 #define HTT_WDS_ENTRY_SA_ADDR_47_32_M 0x0000ffff 3640 #define HTT_WDS_ENTRY_SA_ADDR_47_32_S 0 3641 #define HTT_WDS_ENTRY_TA_PEER_ID_M 0x3fff0000 3642 #define HTT_WDS_ENTRY_TA_PEER_ID_S 16 3643 3644 /* DWORD 0 */ 3645 #define HTT_WDS_ENTRY_VDEV_ID_GET(_var) \ 3646 (((_var) & HTT_WDS_ENTRY_VDEV_ID_M) >> \ 3647 HTT_WDS_ENTRY_VDEV_ID_S) 3648 #define HTT_WDS_ENTRY_VDEV_ID_SET(_var, _val) \ 3649 do { \ 3650 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_VDEV_ID, _val); \ 3651 ((_var) |= ((_val) << HTT_WDS_ENTRY_VDEV_ID_S)); \ 3652 } while (0) 3653 3654 #define HTT_WDS_ENTRY_PDEV_ID_GET(_var) \ 3655 (((_var) & HTT_WDS_ENTRY_PDEV_ID_M) >> \ 3656 HTT_WDS_ENTRY_PDEV_ID_S) 3657 #define HTT_WDS_ENTRY_PDEV_ID_SET(_var, _val) \ 3658 do { \ 3659 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_PDEV_ID, _val); \ 3660 ((_var) |= ((_val) << HTT_WDS_ENTRY_PDEV_ID_S)); \ 3661 } while (0) 3662 3663 /* DWORD 2 */ 3664 #define HTT_WDS_ENTRY_SA_ADDR_47_32_GET(_var) \ 3665 (((_var) & HTT_WDS_ENTRY_SA_ADDR_47_32_M) >> \ 3666 HTT_WDS_ENTRY_SA_ADDR_47_32_S) 3667 #define HTT_WDS_ENTRY_SA_ADDR_47_32_SET(_var, _val) \ 3668 do { \ 3669 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_SA_ADDR_47_32, _val); \ 3670 ((_var) |= ((_val) << HTT_WDS_ENTRY_SA_ADDR_47_32_S)); \ 3671 } while (0) 3672 3673 #define HTT_WDS_ENTRY_TA_PEER_ID_GET(_var) \ 3674 (((_var) & HTT_WDS_ENTRY_TA_PEER_ID_M) >> \ 3675 HTT_WDS_ENTRY_TA_PEER_ID_S) 3676 #define HTT_WDS_ENTRY_TA_PEER_ID_SET(_var, _val) \ 3677 do { \ 3678 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_TA_PEER_ID, _val); \ 3679 ((_var) |= ((_val) << HTT_WDS_ENTRY_TA_PEER_ID_S)); \ 3680 } while (0) 3681 3682 3683 /** 3684 * @brief MAC DMA rx ring setup specification 3685 * 3686 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_CFG 3687 * 3688 * @details 3689 * To allow for dynamic rx ring reconfiguration and to avoid race 3690 * conditions, the host SW never directly programs the MAC DMA rx ring(s) 3691 * it uses. Instead, it sends this message to the target, indicating how 3692 * the rx ring used by the host should be set up and maintained. 3693 * The message consists of a 4-octet header followed by 1 or 2 rx ring setup 3694 * specifications. 3695 * 3696 * |31 16|15 8|7 0| 3697 * |---------------------------------------------------------------| 3698 * header: | reserved | num rings | msg type | 3699 * |---------------------------------------------------------------| 3700 * payload 1: | FW_IDX shadow register physical address (bits 31:0) | 3701 #if HTT_PADDR64 3702 * | FW_IDX shadow register physical address (bits 63:32) | 3703 #endif 3704 * |---------------------------------------------------------------| 3705 * | rx ring base physical address (bits 31:0) | 3706 #if HTT_PADDR64 3707 * | rx ring base physical address (bits 63:32) | 3708 #endif 3709 * |---------------------------------------------------------------| 3710 * | rx ring buffer size | rx ring length | 3711 * |---------------------------------------------------------------| 3712 * | FW_IDX initial value | enabled flags | 3713 * |---------------------------------------------------------------| 3714 * | MSDU payload offset | 802.11 header offset | 3715 * |---------------------------------------------------------------| 3716 * | PPDU end offset | PPDU start offset | 3717 * |---------------------------------------------------------------| 3718 * | MPDU end offset | MPDU start offset | 3719 * |---------------------------------------------------------------| 3720 * | MSDU end offset | MSDU start offset | 3721 * |---------------------------------------------------------------| 3722 * | frag info offset | rx attention offset | 3723 * |---------------------------------------------------------------| 3724 * payload 2, if present, has the same format as payload 1 3725 * Header fields: 3726 * - MSG_TYPE 3727 * Bits 7:0 3728 * Purpose: identifies this as an rx ring configuration message 3729 * Value: 0x2 (HTT_H2T_MSG_TYPE_RX_RING_CFG) 3730 * - NUM_RINGS 3731 * Bits 15:8 3732 * Purpose: indicates whether the host is setting up one rx ring or two 3733 * Value: 1 or 2 3734 * Payload: 3735 * for systems using 64-bit format for bus addresses: 3736 * - IDX_SHADOW_REG_PADDR_LO 3737 * Bits 31:0 3738 * Value: lower 4 bytes of physical address of the host's 3739 * FW_IDX shadow register 3740 * - IDX_SHADOW_REG_PADDR_HI 3741 * Bits 31:0 3742 * Value: upper 4 bytes of physical address of the host's 3743 * FW_IDX shadow register 3744 * - RING_BASE_PADDR_LO 3745 * Bits 31:0 3746 * Value: lower 4 bytes of physical address of the host's rx ring 3747 * - RING_BASE_PADDR_HI 3748 * Bits 31:0 3749 * Value: uppper 4 bytes of physical address of the host's rx ring 3750 * for systems using 32-bit format for bus addresses: 3751 * - IDX_SHADOW_REG_PADDR 3752 * Bits 31:0 3753 * Value: physical address of the host's FW_IDX shadow register 3754 * - RING_BASE_PADDR 3755 * Bits 31:0 3756 * Value: physical address of the host's rx ring 3757 * - RING_LEN 3758 * Bits 15:0 3759 * Value: number of elements in the rx ring 3760 * - RING_BUF_SZ 3761 * Bits 31:16 3762 * Value: size of the buffers referenced by the rx ring, in byte units 3763 * - ENABLED_FLAGS 3764 * Bits 15:0 3765 * Value: 1-bit flags to show whether different rx fields are enabled 3766 * bit 0: 802.11 header enabled (1) or disabled (0) 3767 * bit 1: MSDU payload enabled (1) or disabled (0) 3768 * bit 2: PPDU start enabled (1) or disabled (0) 3769 * bit 3: PPDU end enabled (1) or disabled (0) 3770 * bit 4: MPDU start enabled (1) or disabled (0) 3771 * bit 5: MPDU end enabled (1) or disabled (0) 3772 * bit 6: MSDU start enabled (1) or disabled (0) 3773 * bit 7: MSDU end enabled (1) or disabled (0) 3774 * bit 8: rx attention enabled (1) or disabled (0) 3775 * bit 9: frag info enabled (1) or disabled (0) 3776 * bit 10: unicast rx enabled (1) or disabled (0) 3777 * bit 11: multicast rx enabled (1) or disabled (0) 3778 * bit 12: ctrl rx enabled (1) or disabled (0) 3779 * bit 13: mgmt rx enabled (1) or disabled (0) 3780 * bit 14: null rx enabled (1) or disabled (0) 3781 * bit 15: phy data rx enabled (1) or disabled (0) 3782 * - IDX_INIT_VAL 3783 * Bits 31:16 3784 * Purpose: Specify the initial value for the FW_IDX. 3785 * Value: the number of buffers initially present in the host's rx ring 3786 * - OFFSET_802_11_HDR 3787 * Bits 15:0 3788 * Value: offset in QUAD-bytes of 802.11 header from the buffer start 3789 * - OFFSET_MSDU_PAYLOAD 3790 * Bits 31:16 3791 * Value: offset in QUAD-bytes of MSDU payload from the buffer start 3792 * - OFFSET_PPDU_START 3793 * Bits 15:0 3794 * Value: offset in QUAD-bytes of PPDU start rx desc from the buffer start 3795 * - OFFSET_PPDU_END 3796 * Bits 31:16 3797 * Value: offset in QUAD-bytes of PPDU end rx desc from the buffer start 3798 * - OFFSET_MPDU_START 3799 * Bits 15:0 3800 * Value: offset in QUAD-bytes of MPDU start rx desc from the buffer start 3801 * - OFFSET_MPDU_END 3802 * Bits 31:16 3803 * Value: offset in QUAD-bytes of MPDU end rx desc from the buffer start 3804 * - OFFSET_MSDU_START 3805 * Bits 15:0 3806 * Value: offset in QUAD-bytes of MSDU start rx desc from the buffer start 3807 * - OFFSET_MSDU_END 3808 * Bits 31:16 3809 * Value: offset in QUAD-bytes of MSDU end rx desc from the buffer start 3810 * - OFFSET_RX_ATTN 3811 * Bits 15:0 3812 * Value: offset in QUAD-bytes of rx attention word from the buffer start 3813 * - OFFSET_FRAG_INFO 3814 * Bits 31:16 3815 * Value: offset in QUAD-bytes of frag info table 3816 */ 3817 /* header fields */ 3818 #define HTT_RX_RING_CFG_NUM_RINGS_M 0xff00 3819 #define HTT_RX_RING_CFG_NUM_RINGS_S 8 3820 3821 /* payload fields */ 3822 /* for systems using a 64-bit format for bus addresses */ 3823 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_M 0xffffffff 3824 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_S 0 3825 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_M 0xffffffff 3826 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_S 0 3827 #define HTT_RX_RING_CFG_BASE_PADDR_HI_M 0xffffffff 3828 #define HTT_RX_RING_CFG_BASE_PADDR_HI_S 0 3829 #define HTT_RX_RING_CFG_BASE_PADDR_LO_M 0xffffffff 3830 #define HTT_RX_RING_CFG_BASE_PADDR_LO_S 0 3831 3832 /* for systems using a 32-bit format for bus addresses */ 3833 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_M 0xffffffff 3834 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_S 0 3835 #define HTT_RX_RING_CFG_BASE_PADDR_M 0xffffffff 3836 #define HTT_RX_RING_CFG_BASE_PADDR_S 0 3837 3838 #define HTT_RX_RING_CFG_LEN_M 0xffff 3839 #define HTT_RX_RING_CFG_LEN_S 0 3840 #define HTT_RX_RING_CFG_BUF_SZ_M 0xffff0000 3841 #define HTT_RX_RING_CFG_BUF_SZ_S 16 3842 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_M 0x1 3843 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_S 0 3844 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M 0x2 3845 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S 1 3846 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_M 0x4 3847 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_S 2 3848 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_M 0x8 3849 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_S 3 3850 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_M 0x10 3851 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_S 4 3852 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_M 0x20 3853 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_S 5 3854 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_M 0x40 3855 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_S 6 3856 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_M 0x80 3857 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_S 7 3858 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_M 0x100 3859 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_S 8 3860 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M 0x200 3861 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S 9 3862 #define HTT_RX_RING_CFG_ENABLED_UCAST_M 0x400 3863 #define HTT_RX_RING_CFG_ENABLED_UCAST_S 10 3864 #define HTT_RX_RING_CFG_ENABLED_MCAST_M 0x800 3865 #define HTT_RX_RING_CFG_ENABLED_MCAST_S 11 3866 #define HTT_RX_RING_CFG_ENABLED_CTRL_M 0x1000 3867 #define HTT_RX_RING_CFG_ENABLED_CTRL_S 12 3868 #define HTT_RX_RING_CFG_ENABLED_MGMT_M 0x2000 3869 #define HTT_RX_RING_CFG_ENABLED_MGMT_S 13 3870 #define HTT_RX_RING_CFG_ENABLED_NULL_M 0x4000 3871 #define HTT_RX_RING_CFG_ENABLED_NULL_S 14 3872 #define HTT_RX_RING_CFG_ENABLED_PHY_M 0x8000 3873 #define HTT_RX_RING_CFG_ENABLED_PHY_S 15 3874 #define HTT_RX_RING_CFG_IDX_INIT_VAL_M 0xffff0000 3875 #define HTT_RX_RING_CFG_IDX_INIT_VAL_S 16 3876 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_M 0xffff 3877 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_S 0 3878 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M 0xffff0000 3879 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S 16 3880 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_M 0xffff 3881 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_S 0 3882 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_M 0xffff0000 3883 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_S 16 3884 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_M 0xffff 3885 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_S 0 3886 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_M 0xffff0000 3887 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_S 16 3888 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_M 0xffff 3889 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_S 0 3890 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_M 0xffff0000 3891 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_S 16 3892 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_M 0xffff 3893 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_S 0 3894 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M 0xffff0000 3895 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S 16 3896 3897 #define HTT_RX_RING_CFG_HDR_BYTES 4 3898 #define HTT_RX_RING_CFG_PAYLD_BYTES_64 44 3899 #define HTT_RX_RING_CFG_PAYLD_BYTES_32 36 3900 #if HTT_PADDR64 3901 #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64 3902 #else 3903 #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32 3904 #endif 3905 #define HTT_RX_RING_CFG_BYTES(num_rings) \ 3906 (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES) 3907 3908 3909 #define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \ 3910 (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S) 3911 #define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \ 3912 do { \ 3913 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \ 3914 ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \ 3915 } while (0) 3916 3917 /* degenerate case for 32-bit fields */ 3918 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_GET(_var) (_var) 3919 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) \ 3920 ((_var) = (_val)) 3921 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_GET(_var) (_var) 3922 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) \ 3923 ((_var) = (_val)) 3924 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_GET(_var) (_var) 3925 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) \ 3926 ((_var) = (_val)) 3927 3928 /* degenerate case for 32-bit fields */ 3929 #define HTT_RX_RING_CFG_BASE_PADDR_HI_GET(_var) (_var) 3930 #define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) \ 3931 ((_var) = (_val)) 3932 #define HTT_RX_RING_CFG_BASE_PADDR_LO_GET(_var) (_var) 3933 #define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) \ 3934 ((_var) = (_val)) 3935 #define HTT_RX_RING_CFG_BASE_PADDR_GET(_var) (_var) 3936 #define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) \ 3937 ((_var) = (_val)) 3938 3939 #define HTT_RX_RING_CFG_LEN_GET(_var) \ 3940 (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S) 3941 #define HTT_RX_RING_CFG_LEN_SET(_var, _val) \ 3942 do { \ 3943 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \ 3944 ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \ 3945 } while (0) 3946 3947 #define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \ 3948 (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S) 3949 #define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \ 3950 do { \ 3951 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \ 3952 ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \ 3953 } while (0) 3954 3955 #define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \ 3956 (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \ 3957 HTT_RX_RING_CFG_IDX_INIT_VAL_S) 3958 #define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \ 3959 do { \ 3960 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \ 3961 ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \ 3962 } while (0) 3963 3964 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \ 3965 (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \ 3966 HTT_RX_RING_CFG_ENABLED_802_11_HDR_S) 3967 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \ 3968 do { \ 3969 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \ 3970 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \ 3971 } while (0) 3972 3973 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \ 3974 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \ 3975 HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S) 3976 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \ 3977 do { \ 3978 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \ 3979 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \ 3980 } while (0) 3981 3982 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \ 3983 (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \ 3984 HTT_RX_RING_CFG_ENABLED_PPDU_START_S) 3985 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \ 3986 do { \ 3987 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \ 3988 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \ 3989 } while (0) 3990 3991 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \ 3992 (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \ 3993 HTT_RX_RING_CFG_ENABLED_PPDU_END_S) 3994 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \ 3995 do { \ 3996 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \ 3997 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \ 3998 } while (0) 3999 4000 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \ 4001 (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \ 4002 HTT_RX_RING_CFG_ENABLED_MPDU_START_S) 4003 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \ 4004 do { \ 4005 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \ 4006 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \ 4007 } while (0) 4008 4009 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \ 4010 (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \ 4011 HTT_RX_RING_CFG_ENABLED_MPDU_END_S) 4012 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \ 4013 do { \ 4014 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \ 4015 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \ 4016 } while (0) 4017 4018 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \ 4019 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \ 4020 HTT_RX_RING_CFG_ENABLED_MSDU_START_S) 4021 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \ 4022 do { \ 4023 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \ 4024 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \ 4025 } while (0) 4026 4027 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \ 4028 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \ 4029 HTT_RX_RING_CFG_ENABLED_MSDU_END_S) 4030 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \ 4031 do { \ 4032 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \ 4033 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \ 4034 } while (0) 4035 4036 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \ 4037 (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \ 4038 HTT_RX_RING_CFG_ENABLED_RX_ATTN_S) 4039 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \ 4040 do { \ 4041 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \ 4042 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \ 4043 } while (0) 4044 4045 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \ 4046 (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \ 4047 HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S) 4048 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \ 4049 do { \ 4050 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \ 4051 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \ 4052 } while (0) 4053 4054 #define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \ 4055 (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \ 4056 HTT_RX_RING_CFG_ENABLED_UCAST_S) 4057 #define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \ 4058 do { \ 4059 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \ 4060 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \ 4061 } while (0) 4062 4063 #define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \ 4064 (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \ 4065 HTT_RX_RING_CFG_ENABLED_MCAST_S) 4066 #define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \ 4067 do { \ 4068 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \ 4069 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \ 4070 } while (0) 4071 #define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \ 4072 (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \ 4073 HTT_RX_RING_CFG_ENABLED_CTRL_S) 4074 #define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \ 4075 do { \ 4076 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \ 4077 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \ 4078 } while (0) 4079 #define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \ 4080 (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \ 4081 HTT_RX_RING_CFG_ENABLED_MGMT_S) 4082 #define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \ 4083 do { \ 4084 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \ 4085 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \ 4086 } while (0) 4087 #define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \ 4088 (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \ 4089 HTT_RX_RING_CFG_ENABLED_NULL_S) 4090 #define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \ 4091 do { \ 4092 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \ 4093 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \ 4094 } while (0) 4095 #define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \ 4096 (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \ 4097 HTT_RX_RING_CFG_ENABLED_PHY_S) 4098 #define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \ 4099 do { \ 4100 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \ 4101 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \ 4102 } while (0) 4103 4104 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \ 4105 (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \ 4106 HTT_RX_RING_CFG_OFFSET_802_11_HDR_S) 4107 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \ 4108 do { \ 4109 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \ 4110 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \ 4111 } while (0) 4112 4113 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \ 4114 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \ 4115 HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S) 4116 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \ 4117 do { \ 4118 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \ 4119 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \ 4120 } while (0) 4121 4122 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \ 4123 (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \ 4124 HTT_RX_RING_CFG_OFFSET_PPDU_START_S) 4125 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \ 4126 do { \ 4127 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \ 4128 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \ 4129 } while (0) 4130 4131 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \ 4132 (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \ 4133 HTT_RX_RING_CFG_OFFSET_PPDU_END_S) 4134 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \ 4135 do { \ 4136 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \ 4137 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \ 4138 } while (0) 4139 4140 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \ 4141 (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \ 4142 HTT_RX_RING_CFG_OFFSET_MPDU_START_S) 4143 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \ 4144 do { \ 4145 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \ 4146 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \ 4147 } while (0) 4148 4149 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \ 4150 (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \ 4151 HTT_RX_RING_CFG_OFFSET_MPDU_END_S) 4152 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \ 4153 do { \ 4154 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \ 4155 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \ 4156 } while (0) 4157 4158 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \ 4159 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \ 4160 HTT_RX_RING_CFG_OFFSET_MSDU_START_S) 4161 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \ 4162 do { \ 4163 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \ 4164 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \ 4165 } while (0) 4166 4167 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \ 4168 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \ 4169 HTT_RX_RING_CFG_OFFSET_MSDU_END_S) 4170 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \ 4171 do { \ 4172 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \ 4173 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \ 4174 } while (0) 4175 4176 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \ 4177 (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \ 4178 HTT_RX_RING_CFG_OFFSET_RX_ATTN_S) 4179 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \ 4180 do { \ 4181 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \ 4182 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \ 4183 } while (0) 4184 4185 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \ 4186 (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \ 4187 HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S) 4188 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \ 4189 do { \ 4190 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \ 4191 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \ 4192 } while (0) 4193 4194 /** 4195 * @brief host -> target FW statistics retrieve 4196 * 4197 * MSG_TYPE => HTT_H2T_MSG_TYPE_STATS_REQ 4198 * 4199 * @details 4200 * The following field definitions describe the format of the HTT host 4201 * to target FW stats retrieve message. The message specifies the type of 4202 * stats host wants to retrieve. 4203 * 4204 * |31 24|23 16|15 8|7 0| 4205 * |-----------------------------------------------------------| 4206 * | stats types request bitmask | msg type | 4207 * |-----------------------------------------------------------| 4208 * | stats types reset bitmask | reserved | 4209 * |-----------------------------------------------------------| 4210 * | stats type | config value | 4211 * |-----------------------------------------------------------| 4212 * | cookie LSBs | 4213 * |-----------------------------------------------------------| 4214 * | cookie MSBs | 4215 * |-----------------------------------------------------------| 4216 * Header fields: 4217 * - MSG_TYPE 4218 * Bits 7:0 4219 * Purpose: identifies this is a stats upload request message 4220 * Value: 0x3 (HTT_H2T_MSG_TYPE_STATS_REQ) 4221 * - UPLOAD_TYPES 4222 * Bits 31:8 4223 * Purpose: identifies which types of FW statistics to upload 4224 * Value: mask with bits set in positions defined by htt_dbg_stats_type 4225 * - RESET_TYPES 4226 * Bits 31:8 4227 * Purpose: identifies which types of FW statistics to reset 4228 * Value: mask with bits set in positions defined by htt_dbg_stats_type 4229 * - CFG_VAL 4230 * Bits 23:0 4231 * Purpose: give an opaque configuration value to the specified stats type 4232 * Value: stats-type specific configuration value 4233 * if stats type == tx PPDU log, then CONFIG_VAL has the format: 4234 * bits 7:0 - how many per-MPDU byte counts to include in a record 4235 * bits 15:8 - how many per-MPDU MSDU counts to include in a record 4236 * bits 23:16 - how many per-MSDU byte counts to include in a record 4237 * - CFG_STAT_TYPE 4238 * Bits 31:24 4239 * Purpose: specify which stats type (if any) the config value applies to 4240 * Value: htt_dbg_stats_type value, or 0xff if the message doesn't have 4241 * a valid configuration specification 4242 * - COOKIE_LSBS 4243 * Bits 31:0 4244 * Purpose: Provide a mechanism to match a target->host stats confirmation 4245 * message with its preceding host->target stats request message. 4246 * Value: LSBs of the opaque cookie specified by the host-side requestor 4247 * - COOKIE_MSBS 4248 * Bits 31:0 4249 * Purpose: Provide a mechanism to match a target->host stats confirmation 4250 * message with its preceding host->target stats request message. 4251 * Value: MSBs of the opaque cookie specified by the host-side requestor 4252 */ 4253 4254 #define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */ 4255 4256 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 4257 4258 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_M 0xffffff00 4259 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_S 8 4260 4261 #define HTT_H2T_STATS_REQ_RESET_TYPES_M 0xffffff00 4262 #define HTT_H2T_STATS_REQ_RESET_TYPES_S 8 4263 4264 #define HTT_H2T_STATS_REQ_CFG_VAL_M 0x00ffffff 4265 #define HTT_H2T_STATS_REQ_CFG_VAL_S 0 4266 4267 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M 0xff000000 4268 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S 24 4269 4270 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \ 4271 (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \ 4272 HTT_H2T_STATS_REQ_UPLOAD_TYPES_S) 4273 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \ 4274 do { \ 4275 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \ 4276 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \ 4277 } while (0) 4278 4279 #define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \ 4280 (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \ 4281 HTT_H2T_STATS_REQ_RESET_TYPES_S) 4282 #define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \ 4283 do { \ 4284 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \ 4285 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \ 4286 } while (0) 4287 4288 #define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \ 4289 (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \ 4290 HTT_H2T_STATS_REQ_CFG_VAL_S) 4291 #define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \ 4292 do { \ 4293 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \ 4294 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \ 4295 } while (0) 4296 4297 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \ 4298 (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \ 4299 HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S) 4300 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \ 4301 do { \ 4302 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \ 4303 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \ 4304 } while (0) 4305 4306 /** 4307 * @brief host -> target HTT out-of-band sync request 4308 * 4309 * MSG_TYPE => HTT_H2T_MSG_TYPE_SYNC 4310 * 4311 * @details 4312 * The HTT SYNC tells the target to suspend processing of subsequent 4313 * HTT host-to-target messages until some other target agent locally 4314 * informs the target HTT FW that the current sync counter is equal to 4315 * or greater than (in a modulo sense) the sync counter specified in 4316 * the SYNC message. 4317 * This allows other host-target components to synchronize their operation 4318 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 4319 * security key has been downloaded to and activated by the target. 4320 * In the absence of any explicit synchronization counter value 4321 * specification, the target HTT FW will use zero as the default current 4322 * sync value. 4323 * 4324 * |31 24|23 16|15 8|7 0| 4325 * |-----------------------------------------------------------| 4326 * | reserved | sync count | msg type | 4327 * |-----------------------------------------------------------| 4328 * Header fields: 4329 * - MSG_TYPE 4330 * Bits 7:0 4331 * Purpose: identifies this as a sync message 4332 * Value: 0x4 (HTT_H2T_MSG_TYPE_SYNC) 4333 * - SYNC_COUNT 4334 * Bits 15:8 4335 * Purpose: specifies what sync value the HTT FW will wait for from 4336 * an out-of-band specification to resume its operation 4337 * Value: in-band sync counter value to compare against the out-of-band 4338 * counter spec. 4339 * The HTT target FW will suspend its host->target message processing 4340 * as long as 4341 * 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128 4342 */ 4343 4344 #define HTT_H2T_SYNC_MSG_SZ 4 4345 4346 #define HTT_H2T_SYNC_COUNT_M 0x0000ff00 4347 #define HTT_H2T_SYNC_COUNT_S 8 4348 4349 #define HTT_H2T_SYNC_COUNT_GET(_var) \ 4350 (((_var) & HTT_H2T_SYNC_COUNT_M) >> \ 4351 HTT_H2T_SYNC_COUNT_S) 4352 #define HTT_H2T_SYNC_COUNT_SET(_var, _val) \ 4353 do { \ 4354 HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \ 4355 ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \ 4356 } while (0) 4357 4358 4359 /** 4360 * @brief host -> target HTT aggregation configuration 4361 * 4362 * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG 4363 */ 4364 #define HTT_AGGR_CFG_MSG_SZ 4 4365 4366 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M 0xff00 4367 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S 8 4368 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M 0x1f0000 4369 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S 16 4370 4371 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \ 4372 (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \ 4373 HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S) 4374 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \ 4375 do { \ 4376 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \ 4377 ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \ 4378 } while (0) 4379 4380 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ 4381 (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \ 4382 HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S) 4383 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ 4384 do { \ 4385 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \ 4386 ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \ 4387 } while (0) 4388 4389 4390 /** 4391 * @brief host -> target HTT configure max amsdu info per vdev 4392 * 4393 * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG_EX 4394 * 4395 * @details 4396 * The HTT AGGR CFG EX tells the target to configure max_amsdu info per vdev 4397 * 4398 * |31 21|20 16|15 8|7 0| 4399 * |-----------------------------------------------------------| 4400 * | reserved | vdev id | max amsdu | msg type | 4401 * |-----------------------------------------------------------| 4402 * Header fields: 4403 * - MSG_TYPE 4404 * Bits 7:0 4405 * Purpose: identifies this as a aggr cfg ex message 4406 * Value: 0xa (HTT_H2T_MSG_TYPE_AGGR_CFG_EX) 4407 * - MAX_NUM_AMSDU_SUBFRM 4408 * Bits 15:8 4409 * Purpose: max MSDUs per A-MSDU 4410 * - VDEV_ID 4411 * Bits 20:16 4412 * Purpose: ID of the vdev to which this limit is applied 4413 */ 4414 #define HTT_AGGR_CFG_EX_MSG_SZ 4 4415 4416 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M 0xff00 4417 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S 8 4418 #define HTT_AGGR_CFG_EX_VDEV_ID_M 0x1f0000 4419 #define HTT_AGGR_CFG_EX_VDEV_ID_S 16 4420 4421 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ 4422 (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \ 4423 HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S) 4424 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ 4425 do { \ 4426 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \ 4427 ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \ 4428 } while (0) 4429 4430 #define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \ 4431 (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \ 4432 HTT_AGGR_CFG_EX_VDEV_ID_S) 4433 #define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \ 4434 do { \ 4435 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \ 4436 ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \ 4437 } while (0) 4438 4439 /** 4440 * @brief HTT WDI_IPA Config Message 4441 * 4442 * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_CFG 4443 * 4444 * @details 4445 * The HTT WDI_IPA config message is created/sent by host at driver 4446 * init time. It contains information about data structures used on 4447 * WDI_IPA TX and RX path. 4448 * TX CE ring is used for pushing packet metadata from IPA uC 4449 * to WLAN FW 4450 * TX Completion ring is used for generating TX completions from 4451 * WLAN FW to IPA uC 4452 * RX Indication ring is used for indicating RX packets from FW 4453 * to IPA uC 4454 * RX Ring2 is used as either completion ring or as second 4455 * indication ring. when Ring2 is used as completion ring, IPA uC 4456 * puts completed RX packet meta data to Ring2. when Ring2 is used 4457 * as second indication ring, RX packets for LTE-WLAN aggregation are 4458 * indicated in Ring2, other RX packets (e.g. hotspot related) are 4459 * indicated in RX Indication ring. Please see WDI_IPA specification 4460 * for more details. 4461 * |31 24|23 16|15 8|7 0| 4462 * |----------------+----------------+----------------+----------------| 4463 * | tx pkt pool size | Rsvd | msg_type | 4464 * |-------------------------------------------------------------------| 4465 * | tx comp ring base (bits 31:0) | 4466 #if HTT_PADDR64 4467 * | tx comp ring base (bits 63:32) | 4468 #endif 4469 * |-------------------------------------------------------------------| 4470 * | tx comp ring size | 4471 * |-------------------------------------------------------------------| 4472 * | tx comp WR_IDX physical address (bits 31:0) | 4473 #if HTT_PADDR64 4474 * | tx comp WR_IDX physical address (bits 63:32) | 4475 #endif 4476 * |-------------------------------------------------------------------| 4477 * | tx CE WR_IDX physical address (bits 31:0) | 4478 #if HTT_PADDR64 4479 * | tx CE WR_IDX physical address (bits 63:32) | 4480 #endif 4481 * |-------------------------------------------------------------------| 4482 * | rx indication ring base (bits 31:0) | 4483 #if HTT_PADDR64 4484 * | rx indication ring base (bits 63:32) | 4485 #endif 4486 * |-------------------------------------------------------------------| 4487 * | rx indication ring size | 4488 * |-------------------------------------------------------------------| 4489 * | rx ind RD_IDX physical address (bits 31:0) | 4490 #if HTT_PADDR64 4491 * | rx ind RD_IDX physical address (bits 63:32) | 4492 #endif 4493 * |-------------------------------------------------------------------| 4494 * | rx ind WR_IDX physical address (bits 31:0) | 4495 #if HTT_PADDR64 4496 * | rx ind WR_IDX physical address (bits 63:32) | 4497 #endif 4498 * |-------------------------------------------------------------------| 4499 * |-------------------------------------------------------------------| 4500 * | rx ring2 base (bits 31:0) | 4501 #if HTT_PADDR64 4502 * | rx ring2 base (bits 63:32) | 4503 #endif 4504 * |-------------------------------------------------------------------| 4505 * | rx ring2 size | 4506 * |-------------------------------------------------------------------| 4507 * | rx ring2 RD_IDX physical address (bits 31:0) | 4508 #if HTT_PADDR64 4509 * | rx ring2 RD_IDX physical address (bits 63:32) | 4510 #endif 4511 * |-------------------------------------------------------------------| 4512 * | rx ring2 WR_IDX physical address (bits 31:0) | 4513 #if HTT_PADDR64 4514 * | rx ring2 WR_IDX physical address (bits 63:32) | 4515 #endif 4516 * |-------------------------------------------------------------------| 4517 * 4518 * Header fields: 4519 * Header fields: 4520 * - MSG_TYPE 4521 * Bits 7:0 4522 * Purpose: Identifies this as WDI_IPA config message 4523 * value: = 0x8 (HTT_H2T_MSG_TYPE_WDI_IPA_CFG) 4524 * - TX_PKT_POOL_SIZE 4525 * Bits 15:0 4526 * Purpose: Total number of TX packet buffer pool allocated by Host for 4527 * WDI_IPA TX path 4528 * For systems using 32-bit format for bus addresses: 4529 * - TX_COMP_RING_BASE_ADDR 4530 * Bits 31:0 4531 * Purpose: TX Completion Ring base address in DDR 4532 * - TX_COMP_RING_SIZE 4533 * Bits 31:0 4534 * Purpose: TX Completion Ring size (must be power of 2) 4535 * - TX_COMP_WR_IDX_ADDR 4536 * Bits 31:0 4537 * Purpose: IPA doorbell register address OR DDR address where WIFI FW 4538 * updates the Write Index for WDI_IPA TX completion ring 4539 * - TX_CE_WR_IDX_ADDR 4540 * Bits 31:0 4541 * Purpose: DDR address where IPA uC 4542 * updates the WR Index for TX CE ring 4543 * (needed for fusion platforms) 4544 * - RX_IND_RING_BASE_ADDR 4545 * Bits 31:0 4546 * Purpose: RX Indication Ring base address in DDR 4547 * - RX_IND_RING_SIZE 4548 * Bits 31:0 4549 * Purpose: RX Indication Ring size 4550 * - RX_IND_RD_IDX_ADDR 4551 * Bits 31:0 4552 * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA 4553 * RX indication ring 4554 * - RX_IND_WR_IDX_ADDR 4555 * Bits 31:0 4556 * Purpose: IPA doorbell register address OR DDR address where WIFI FW 4557 * updates the Write Index for WDI_IPA RX indication ring 4558 * - RX_RING2_BASE_ADDR 4559 * Bits 31:0 4560 * Purpose: Second RX Ring(Indication or completion)base address in DDR 4561 * - RX_RING2_SIZE 4562 * Bits 31:0 4563 * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) 4564 * - RX_RING2_RD_IDX_ADDR 4565 * Bits 31:0 4566 * Purpose: If Second RX ring is Indication ring, DDR address where 4567 * IPA uC updates the Read Index for Ring2. 4568 * If Second RX ring is completion ring, this is NOT used 4569 * - RX_RING2_WR_IDX_ADDR 4570 * Bits 31:0 4571 * Purpose: If Second RX ring is Indication ring, DDR address where 4572 * WIFI FW updates the Write Index for WDI_IPA RX ring2 4573 * If second RX ring is completion ring, DDR address where 4574 * IPA uC updates the Write Index for Ring 2. 4575 * For systems using 64-bit format for bus addresses: 4576 * - TX_COMP_RING_BASE_ADDR_LO 4577 * Bits 31:0 4578 * Purpose: Lower 4 bytes of TX Completion Ring base physical address in DDR 4579 * - TX_COMP_RING_BASE_ADDR_HI 4580 * Bits 31:0 4581 * Purpose: Higher 4 bytes of TX Completion Ring base physical address in DDR 4582 * - TX_COMP_RING_SIZE 4583 * Bits 31:0 4584 * Purpose: TX Completion Ring size (must be power of 2) 4585 * - TX_COMP_WR_IDX_ADDR_LO 4586 * Bits 31:0 4587 * Purpose: Lower 4 bytes of IPA doorbell register address OR 4588 * Lower 4 bytes of DDR address where WIFI FW 4589 * updates the Write Index for WDI_IPA TX completion ring 4590 * - TX_COMP_WR_IDX_ADDR_HI 4591 * Bits 31:0 4592 * Purpose: Higher 4 bytes of IPA doorbell register address OR 4593 * Higher 4 bytes of DDR address where WIFI FW 4594 * updates the Write Index for WDI_IPA TX completion ring 4595 * - TX_CE_WR_IDX_ADDR_LO 4596 * Bits 31:0 4597 * Purpose: Lower 4 bytes of DDR address where IPA uC 4598 * updates the WR Index for TX CE ring 4599 * (needed for fusion platforms) 4600 * - TX_CE_WR_IDX_ADDR_HI 4601 * Bits 31:0 4602 * Purpose: Higher 4 bytes of DDR address where IPA uC 4603 * updates the WR Index for TX CE ring 4604 * (needed for fusion platforms) 4605 * - RX_IND_RING_BASE_ADDR_LO 4606 * Bits 31:0 4607 * Purpose: Lower 4 bytes of RX Indication Ring base address in DDR 4608 * - RX_IND_RING_BASE_ADDR_HI 4609 * Bits 31:0 4610 * Purpose: Higher 4 bytes of RX Indication Ring base address in DDR 4611 * - RX_IND_RING_SIZE 4612 * Bits 31:0 4613 * Purpose: RX Indication Ring size 4614 * - RX_IND_RD_IDX_ADDR_LO 4615 * Bits 31:0 4616 * Purpose: Lower 4 bytes of DDR address where IPA uC updates the Read Index 4617 * for WDI_IPA RX indication ring 4618 * - RX_IND_RD_IDX_ADDR_HI 4619 * Bits 31:0 4620 * Purpose: Higher 4 bytes of DDR address where IPA uC updates the Read Index 4621 * for WDI_IPA RX indication ring 4622 * - RX_IND_WR_IDX_ADDR_LO 4623 * Bits 31:0 4624 * Purpose: Lower 4 bytes of IPA doorbell register address OR 4625 * Lower 4 bytes of DDR address where WIFI FW 4626 * updates the Write Index for WDI_IPA RX indication ring 4627 * - RX_IND_WR_IDX_ADDR_HI 4628 * Bits 31:0 4629 * Purpose: Higher 4 bytes of IPA doorbell register address OR 4630 * Higher 4 bytes of DDR address where WIFI FW 4631 * updates the Write Index for WDI_IPA RX indication ring 4632 * - RX_RING2_BASE_ADDR_LO 4633 * Bits 31:0 4634 * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion)base address in DDR 4635 * - RX_RING2_BASE_ADDR_HI 4636 * Bits 31:0 4637 * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion)base address in DDR 4638 * - RX_RING2_SIZE 4639 * Bits 31:0 4640 * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) 4641 * - RX_RING2_RD_IDX_ADDR_LO 4642 * Bits 31:0 4643 * Purpose: If Second RX ring is Indication ring, lower 4 bytes of 4644 * DDR address where IPA uC updates the Read Index for Ring2. 4645 * If Second RX ring is completion ring, this is NOT used 4646 * - RX_RING2_RD_IDX_ADDR_HI 4647 * Bits 31:0 4648 * Purpose: If Second RX ring is Indication ring, higher 4 bytes of 4649 * DDR address where IPA uC updates the Read Index for Ring2. 4650 * If Second RX ring is completion ring, this is NOT used 4651 * - RX_RING2_WR_IDX_ADDR_LO 4652 * Bits 31:0 4653 * Purpose: If Second RX ring is Indication ring, lower 4 bytes of 4654 * DDR address where WIFI FW updates the Write Index 4655 * for WDI_IPA RX ring2 4656 * If second RX ring is completion ring, lower 4 bytes of 4657 * DDR address where IPA uC updates the Write Index for Ring 2. 4658 * - RX_RING2_WR_IDX_ADDR_HI 4659 * Bits 31:0 4660 * Purpose: If Second RX ring is Indication ring, higher 4 bytes of 4661 * DDR address where WIFI FW updates the Write Index 4662 * for WDI_IPA RX ring2 4663 * If second RX ring is completion ring, higher 4 bytes of 4664 * DDR address where IPA uC updates the Write Index for Ring 2. 4665 */ 4666 4667 #if HTT_PADDR64 4668 #define HTT_WDI_IPA_CFG_SZ 88 /* bytes */ 4669 #else 4670 #define HTT_WDI_IPA_CFG_SZ 52 /* bytes */ 4671 #endif 4672 4673 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M 0xffff0000 4674 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S 16 4675 4676 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M 0xffffffff 4677 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S 0 4678 4679 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M 0xffffffff 4680 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S 0 4681 4682 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M 0xffffffff 4683 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S 0 4684 4685 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M 0xffffffff 4686 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S 0 4687 4688 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M 0xffffffff 4689 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S 0 4690 4691 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M 0xffffffff 4692 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S 0 4693 4694 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M 0xffffffff 4695 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S 0 4696 4697 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M 0xffffffff 4698 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S 0 4699 4700 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M 0xffffffff 4701 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S 0 4702 4703 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M 0xffffffff 4704 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S 0 4705 4706 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M 0xffffffff 4707 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S 0 4708 4709 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M 0xffffffff 4710 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S 0 4711 4712 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M 0xffffffff 4713 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S 0 4714 4715 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M 0xffffffff 4716 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S 0 4717 4718 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M 0xffffffff 4719 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S 0 4720 4721 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M 0xffffffff 4722 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S 0 4723 4724 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M 0xffffffff 4725 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S 0 4726 4727 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M 0xffffffff 4728 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S 0 4729 4730 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M 0xffffffff 4731 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S 0 4732 4733 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M 0xffffffff 4734 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S 0 4735 4736 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M 0xffffffff 4737 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S 0 4738 4739 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M 0xffffffff 4740 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S 0 4741 4742 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M 0xffffffff 4743 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S 0 4744 4745 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_M 0xffffffff 4746 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_S 0 4747 4748 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M 0xffffffff 4749 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S 0 4750 4751 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M 0xffffffff 4752 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S 0 4753 4754 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M 0xffffffff 4755 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S 0 4756 4757 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M 0xffffffff 4758 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S 0 4759 4760 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M 0xffffffff 4761 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S 0 4762 4763 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M 0xffffffff 4764 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S 0 4765 4766 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \ 4767 (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S) 4768 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \ 4769 do { \ 4770 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \ 4771 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \ 4772 } while (0) 4773 4774 /* for systems using 32-bit format for bus addr */ 4775 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \ 4776 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S) 4777 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \ 4778 do { \ 4779 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val); \ 4780 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \ 4781 } while (0) 4782 4783 /* for systems using 64-bit format for bus addr */ 4784 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_GET(_var) \ 4785 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S) 4786 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_SET(_var, _val) \ 4787 do { \ 4788 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val); \ 4789 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \ 4790 } while (0) 4791 4792 /* for systems using 64-bit format for bus addr */ 4793 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_GET(_var) \ 4794 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S) 4795 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_SET(_var, _val) \ 4796 do { \ 4797 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \ 4798 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \ 4799 } while (0) 4800 4801 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \ 4802 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S) 4803 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \ 4804 do { \ 4805 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \ 4806 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \ 4807 } while (0) 4808 4809 /* for systems using 32-bit format for bus addr */ 4810 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \ 4811 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S) 4812 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \ 4813 do { \ 4814 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \ 4815 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \ 4816 } while (0) 4817 4818 /* for systems using 64-bit format for bus addr */ 4819 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_GET(_var) \ 4820 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S) 4821 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_SET(_var, _val) \ 4822 do { \ 4823 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \ 4824 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \ 4825 } while (0) 4826 4827 /* for systems using 64-bit format for bus addr */ 4828 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_GET(_var) \ 4829 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S) 4830 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_SET(_var, _val) \ 4831 do { \ 4832 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \ 4833 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \ 4834 } while (0) 4835 4836 4837 /* for systems using 32-bit format for bus addr */ 4838 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \ 4839 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S) 4840 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \ 4841 do { \ 4842 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \ 4843 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \ 4844 } while (0) 4845 4846 /* for systems using 64-bit format for bus addr */ 4847 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_GET(_var) \ 4848 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S) 4849 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_SET(_var, _val) \ 4850 do { \ 4851 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \ 4852 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \ 4853 } while (0) 4854 4855 /* for systems using 64-bit format for bus addr */ 4856 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_GET(_var) \ 4857 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S) 4858 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_SET(_var, _val) \ 4859 do { \ 4860 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \ 4861 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \ 4862 } while (0) 4863 4864 /* for systems using 32-bit format for bus addr */ 4865 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \ 4866 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S) 4867 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \ 4868 do { \ 4869 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \ 4870 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \ 4871 } while (0) 4872 4873 /* for systems using 64-bit format for bus addr */ 4874 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_GET(_var) \ 4875 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S) 4876 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_SET(_var, _val) \ 4877 do { \ 4878 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \ 4879 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \ 4880 } while (0) 4881 4882 /* for systems using 64-bit format for bus addr */ 4883 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_GET(_var) \ 4884 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S) 4885 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_SET(_var, _val) \ 4886 do { \ 4887 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \ 4888 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \ 4889 } while (0) 4890 4891 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \ 4892 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S) 4893 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \ 4894 do { \ 4895 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \ 4896 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \ 4897 } while (0) 4898 4899 /* for systems using 32-bit format for bus addr */ 4900 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \ 4901 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S) 4902 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \ 4903 do { \ 4904 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \ 4905 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \ 4906 } while (0) 4907 4908 /* for systems using 64-bit format for bus addr */ 4909 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_GET(_var) \ 4910 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S) 4911 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_SET(_var, _val) \ 4912 do { \ 4913 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \ 4914 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \ 4915 } while (0) 4916 4917 /* for systems using 64-bit format for bus addr */ 4918 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_GET(_var) \ 4919 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S) 4920 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_SET(_var, _val) \ 4921 do { \ 4922 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \ 4923 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \ 4924 } while (0) 4925 4926 /* for systems using 32-bit format for bus addr */ 4927 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \ 4928 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S) 4929 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \ 4930 do { \ 4931 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \ 4932 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \ 4933 } while (0) 4934 4935 /* for systems using 64-bit format for bus addr */ 4936 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_GET(_var) \ 4937 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S) 4938 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_SET(_var, _val) \ 4939 do { \ 4940 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \ 4941 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \ 4942 } while (0) 4943 4944 /* for systems using 64-bit format for bus addr */ 4945 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_GET(_var) \ 4946 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S) 4947 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_SET(_var, _val) \ 4948 do { \ 4949 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \ 4950 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \ 4951 } while (0) 4952 4953 /* for systems using 32-bit format for bus addr */ 4954 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_GET(_var) \ 4955 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S) 4956 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_SET(_var, _val) \ 4957 do { \ 4958 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \ 4959 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \ 4960 } while (0) 4961 4962 /* for systems using 64-bit format for bus addr */ 4963 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_GET(_var) \ 4964 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S) 4965 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_SET(_var, _val) \ 4966 do { \ 4967 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \ 4968 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \ 4969 } while (0) 4970 4971 /* for systems using 64-bit format for bus addr */ 4972 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_GET(_var) \ 4973 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S) 4974 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_SET(_var, _val) \ 4975 do { \ 4976 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \ 4977 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \ 4978 } while (0) 4979 4980 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_GET(_var) \ 4981 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> HTT_WDI_IPA_CFG_RX_RING2_SIZE_S) 4982 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_SET(_var, _val) \ 4983 do { \ 4984 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \ 4985 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \ 4986 } while (0) 4987 4988 /* for systems using 32-bit format for bus addr */ 4989 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_GET(_var) \ 4990 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S) 4991 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_SET(_var, _val) \ 4992 do { \ 4993 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \ 4994 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \ 4995 } while (0) 4996 4997 /* for systems using 64-bit format for bus addr */ 4998 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_GET(_var) \ 4999 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S) 5000 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_SET(_var, _val) \ 5001 do { \ 5002 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \ 5003 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \ 5004 } while (0) 5005 5006 /* for systems using 64-bit format for bus addr */ 5007 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_GET(_var) \ 5008 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S) 5009 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_SET(_var, _val) \ 5010 do { \ 5011 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \ 5012 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \ 5013 } while (0) 5014 5015 /* for systems using 32-bit format for bus addr */ 5016 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_GET(_var) \ 5017 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S) 5018 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_SET(_var, _val) \ 5019 do { \ 5020 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \ 5021 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \ 5022 } while (0) 5023 5024 /* for systems using 64-bit format for bus addr */ 5025 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_GET(_var) \ 5026 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S) 5027 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_SET(_var, _val) \ 5028 do { \ 5029 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \ 5030 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \ 5031 } while (0) 5032 5033 /* for systems using 64-bit format for bus addr */ 5034 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_GET(_var) \ 5035 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S) 5036 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_SET(_var, _val) \ 5037 do { \ 5038 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \ 5039 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \ 5040 } while (0) 5041 5042 /* 5043 * TEMPLATE_HTT_WDI_IPA_CONFIG_T: 5044 * This macro defines a htt_wdi_ipa_configXXX_t in which any physical 5045 * addresses are stored in a XXX-bit field. 5046 * This macro is used to define both htt_wdi_ipa_config32_t and 5047 * htt_wdi_ipa_config64_t structs. 5048 */ 5049 #define TEMPLATE_HTT_WDI_IPA_CONFIG_T(_paddr_bits_, \ 5050 _paddr__tx_comp_ring_base_addr_, \ 5051 _paddr__tx_comp_wr_idx_addr_, \ 5052 _paddr__tx_ce_wr_idx_addr_, \ 5053 _paddr__rx_ind_ring_base_addr_, \ 5054 _paddr__rx_ind_rd_idx_addr_, \ 5055 _paddr__rx_ind_wr_idx_addr_, \ 5056 _paddr__rx_ring2_base_addr_,\ 5057 _paddr__rx_ring2_rd_idx_addr_,\ 5058 _paddr__rx_ring2_wr_idx_addr_) \ 5059 PREPACK struct htt_wdi_ipa_cfg ## _paddr_bits_ ## _t \ 5060 { \ 5061 /* DWORD 0: flags and meta-data */ \ 5062 A_UINT32 \ 5063 msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \ 5064 reserved: 8, \ 5065 tx_pkt_pool_size: 16;\ 5066 /* DWORD 1 */\ 5067 _paddr__tx_comp_ring_base_addr_;\ 5068 /* DWORD 2 (or 3)*/\ 5069 A_UINT32 tx_comp_ring_size;\ 5070 /* DWORD 3 (or 4)*/\ 5071 _paddr__tx_comp_wr_idx_addr_;\ 5072 /* DWORD 4 (or 6)*/\ 5073 _paddr__tx_ce_wr_idx_addr_;\ 5074 /* DWORD 5 (or 8)*/\ 5075 _paddr__rx_ind_ring_base_addr_;\ 5076 /* DWORD 6 (or 10)*/\ 5077 A_UINT32 rx_ind_ring_size;\ 5078 /* DWORD 7 (or 11)*/\ 5079 _paddr__rx_ind_rd_idx_addr_;\ 5080 /* DWORD 8 (or 13)*/\ 5081 _paddr__rx_ind_wr_idx_addr_;\ 5082 /* DWORD 9 (or 15)*/\ 5083 _paddr__rx_ring2_base_addr_;\ 5084 /* DWORD 10 (or 17) */\ 5085 A_UINT32 rx_ring2_size;\ 5086 /* DWORD 11 (or 18) */\ 5087 _paddr__rx_ring2_rd_idx_addr_;\ 5088 /* DWORD 12 (or 20) */\ 5089 _paddr__rx_ring2_wr_idx_addr_;\ 5090 } POSTPACK 5091 5092 /* define a htt_wdi_ipa_config32_t type */ 5093 TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), HTT_VAR_PADDR32(tx_comp_wr_idx_addr), HTT_VAR_PADDR32(tx_ce_wr_idx_addr), HTT_VAR_PADDR32(rx_ind_ring_base_addr), HTT_VAR_PADDR32(rx_ind_rd_idx_addr),HTT_VAR_PADDR32(rx_ind_wr_idx_addr), HTT_VAR_PADDR32(rx_ring2_base_addr), HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), HTT_VAR_PADDR32(rx_ring2_wr_idx_addr)); 5094 5095 /* define a htt_wdi_ipa_config64_t type */ 5096 TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_base_addr), HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr)); 5097 5098 #if HTT_PADDR64 5099 #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t 5100 #else 5101 #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t 5102 #endif 5103 5104 enum htt_wdi_ipa_op_code { 5105 HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0, 5106 HTT_WDI_IPA_OPCODE_TX_RESUME = 1, 5107 HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2, 5108 HTT_WDI_IPA_OPCODE_RX_RESUME = 3, 5109 HTT_WDI_IPA_OPCODE_DBG_STATS = 4, 5110 HTT_WDI_IPA_OPCODE_GET_SHARING_STATS = 5, 5111 HTT_WDI_IPA_OPCODE_SET_QUOTA = 6, 5112 HTT_WDI_IPA_OPCODE_IND_QUOTA = 7, 5113 /* keep this last */ 5114 HTT_WDI_IPA_OPCODE_MAX 5115 }; 5116 5117 /** 5118 * @brief HTT WDI_IPA Operation Request Message 5119 * 5120 * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ 5121 * 5122 * @details 5123 * HTT WDI_IPA Operation Request message is sent by host 5124 * to either suspend or resume WDI_IPA TX or RX path. 5125 * |31 24|23 16|15 8|7 0| 5126 * |----------------+----------------+----------------+----------------| 5127 * | op_code | Rsvd | msg_type | 5128 * |-------------------------------------------------------------------| 5129 * 5130 * Header fields: 5131 * - MSG_TYPE 5132 * Bits 7:0 5133 * Purpose: Identifies this as WDI_IPA Operation Request message 5134 * value: = 0x9 (HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ) 5135 * - OP_CODE 5136 * Bits 31:16 5137 * Purpose: Identifies operation host is requesting (e.g. TX suspend) 5138 * value: = enum htt_wdi_ipa_op_code 5139 */ 5140 5141 PREPACK struct htt_wdi_ipa_op_request_t 5142 { 5143 /* DWORD 0: flags and meta-data */ 5144 A_UINT32 5145 msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */ 5146 reserved: 8, 5147 op_code: 16; 5148 } POSTPACK; 5149 5150 #define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */ 5151 5152 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_M 0xffff0000 5153 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_S 16 5154 5155 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \ 5156 (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> HTT_WDI_IPA_OP_REQUEST_OP_CODE_S) 5157 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \ 5158 do { \ 5159 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \ 5160 ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \ 5161 } while (0) 5162 5163 /* 5164 * @brief host -> target HTT_MSI_SETUP message 5165 * 5166 * MSG_TYPE => HTT_H2T_MSG_TYPE_MSI_SETUP 5167 * 5168 * @details 5169 * After target is booted up, host can send MSI setup message so that 5170 * target sets up HW registers based on setup message. 5171 * 5172 * The message would appear as follows: 5173 * |31 24|23 16|15|14 8|7 0| 5174 * |---------------+-----------------+-----------------+-----------------| 5175 * | reserved | msi_type | pdev_id | msg_type | 5176 * |---------------------------------------------------------------------| 5177 * | msi_addr_lo | 5178 * |---------------------------------------------------------------------| 5179 * | msi_addr_hi | 5180 * |---------------------------------------------------------------------| 5181 * | msi_data | 5182 * |---------------------------------------------------------------------| 5183 * 5184 * The message is interpreted as follows: 5185 * dword0 - b'0:7 - msg_type: This will be set to 5186 * 0x1f (HTT_H2T_MSG_TYPE_MSI_SETUP) 5187 * b'8:15 - pdev_id: 5188 * 0 (for rings at SOC/UMAC level), 5189 * 1/2/3 mac id (for rings at LMAC level) 5190 * b'16:23 - msi_type: identify which msi registers need to be setup 5191 * more details can be got from enum htt_msi_setup_type 5192 * b'24:31 - reserved 5193 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 5194 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 5195 * dword10 - b'0:31 - ring_msi_data: MSI data configured by host 5196 */ 5197 PREPACK struct htt_msi_setup_t { 5198 A_UINT32 msg_type: 8, 5199 pdev_id: 8, 5200 msi_type: 8, 5201 reserved: 8; 5202 A_UINT32 msi_addr_lo; 5203 A_UINT32 msi_addr_hi; 5204 A_UINT32 msi_data; 5205 } POSTPACK; 5206 5207 enum htt_msi_setup_type { 5208 HTT_PPDU_END_MSI_SETUP_TYPE, 5209 5210 /* Insert new types here*/ 5211 }; 5212 5213 #define HTT_MSI_SETUP_SZ (sizeof(struct htt_msi_setup_t)) 5214 #define HTT_MSI_SETUP_PDEV_ID_M 0x0000ff00 5215 #define HTT_MSI_SETUP_PDEV_ID_S 8 5216 #define HTT_MSI_SETUP_PDEV_ID_GET(_var) \ 5217 (((_var) & HTT_MSI_SETUP_PDEV_ID_M) >> \ 5218 HTT_MSI_SETUP_PDEV_ID_S) 5219 #define HTT_MSI_SETUP_PDEV_ID_SET(_var, _val) \ 5220 do { \ 5221 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_PDEV_ID, _val); \ 5222 ((_var) |= ((_val) << HTT_MSI_SETUP_PDEV_ID_S)); \ 5223 } while (0) 5224 5225 #define HTT_MSI_SETUP_MSI_TYPE_M 0x00ff0000 5226 #define HTT_MSI_SETUP_MSI_TYPE_S 16 5227 #define HTT_MSI_SETUP_MSI_TYPE_GET(_var) \ 5228 (((_var) & HTT_MSI_SETUP_MSI_TYPE_M) >> \ 5229 HTT_MSI_SETUP_MSI_TYPE_S) 5230 #define HTT_MSI_SETUP_MSI_TYPE_SET(_var, _val) \ 5231 do { \ 5232 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_TYPE, _val); \ 5233 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_TYPE_S)); \ 5234 } while (0) 5235 5236 #define HTT_MSI_SETUP_MSI_ADDR_LO_M 0xffffffff 5237 #define HTT_MSI_SETUP_MSI_ADDR_LO_S 0 5238 #define HTT_MSI_SETUP_MSI_ADDR_LO_GET(_var) \ 5239 (((_var) & HTT_MSI_SETUP_MSI_ADDR_LO_M) >> \ 5240 HTT_MSI_SETUP_MSI_ADDR_LO_S) 5241 #define HTT_MSI_SETUP_MSI_ADDR_LO_SET(_var, _val) \ 5242 do { \ 5243 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_LO, _val); \ 5244 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_LO_S)); \ 5245 } while (0) 5246 5247 #define HTT_MSI_SETUP_MSI_ADDR_HI_M 0xffffffff 5248 #define HTT_MSI_SETUP_MSI_ADDR_HI_S 0 5249 #define HTT_MSI_SETUP_MSI_ADDR_HI_GET(_var) \ 5250 (((_var) & HTT_MSI_SETUP_MSI_ADDR_HI_M) >> \ 5251 HTT_MSI_SETUP_MSI_ADDR_HI_S) 5252 #define HTT_MSI_SETUP_MSI_ADDR_HI_SET(_var, _val) \ 5253 do { \ 5254 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_HI, _val); \ 5255 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_HI_S)); \ 5256 } while (0) 5257 5258 #define HTT_MSI_SETUP_MSI_DATA_M 0xffffffff 5259 #define HTT_MSI_SETUP_MSI_DATA_S 0 5260 #define HTT_MSI_SETUP_MSI_DATA_GET(_var) \ 5261 (((_var) & HTT_MSI_SETUP_MSI_DATA_M) >> \ 5262 HTT_MSI_SETUP_MSI_DATA_S) 5263 #define HTT_MSI_SETUP_MSI_DATA_SET(_var, _val) \ 5264 do { \ 5265 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_DATA, _val); \ 5266 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_DATA_S)); \ 5267 } while (0) 5268 5269 /* 5270 * @brief host -> target HTT_SRING_SETUP message 5271 * 5272 * MSG_TYPE => HTT_H2T_MSG_TYPE_SRING_SETUP 5273 * 5274 * @details 5275 * After target is booted up, Host can send SRING setup message for 5276 * each host facing LMAC SRING. Target setups up HW registers based 5277 * on setup message and confirms back to Host if response_required is set. 5278 * Host should wait for confirmation message before sending new SRING 5279 * setup message 5280 * 5281 * The message would appear as follows: 5282 * |31 24|23 21|20|19|18 16|15|14 8|7 0| 5283 * |--------------- +-----------------+-----------------+-----------------| 5284 * | ring_type | ring_id | pdev_id | msg_type | 5285 * |----------------------------------------------------------------------| 5286 * | ring_base_addr_lo | 5287 * |----------------------------------------------------------------------| 5288 * | ring_base_addr_hi | 5289 * |----------------------------------------------------------------------| 5290 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 5291 * |----------------------------------------------------------------------| 5292 * | ring_head_offset32_remote_addr_lo | 5293 * |----------------------------------------------------------------------| 5294 * | ring_head_offset32_remote_addr_hi | 5295 * |----------------------------------------------------------------------| 5296 * | ring_tail_offset32_remote_addr_lo | 5297 * |----------------------------------------------------------------------| 5298 * | ring_tail_offset32_remote_addr_hi | 5299 * |----------------------------------------------------------------------| 5300 * | ring_msi_addr_lo | 5301 * |----------------------------------------------------------------------| 5302 * | ring_msi_addr_hi | 5303 * |----------------------------------------------------------------------| 5304 * | ring_msi_data | 5305 * |----------------------------------------------------------------------| 5306 * | intr_timer_th |IM| intr_batch_counter_th | 5307 * |----------------------------------------------------------------------| 5308 * | reserved |ID|RR| PTCF| intr_low_threshold | 5309 * |----------------------------------------------------------------------| 5310 * | reserved |IPA drop thres hi|IPA drop thres lo| 5311 * |----------------------------------------------------------------------| 5312 * Where 5313 * IM = sw_intr_mode 5314 * RR = response_required 5315 * PTCF = prefetch_timer_cfg 5316 * IP = IPA drop flag 5317 * 5318 * The message is interpreted as follows: 5319 * dword0 - b'0:7 - msg_type: This will be set to 5320 * 0xb (HTT_H2T_MSG_TYPE_SRING_SETUP) 5321 * b'8:15 - pdev_id: 5322 * 0 (for rings at SOC/UMAC level), 5323 * 1/2/3 mac id (for rings at LMAC level) 5324 * b'16:23 - ring_id: identify which ring is to setup, 5325 * more details can be got from enum htt_srng_ring_id 5326 * b'24:31 - ring_type: identify type of host rings, 5327 * more details can be got from enum htt_srng_ring_type 5328 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 5329 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 5330 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 5331 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 5332 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 5333 * SW_TO_HW_RING. 5334 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 5335 * dword4 - b'0:31 - ring_head_offset32_remote_addr_lo: 5336 * Lower 32 bits of memory address of the remote variable 5337 * storing the 4-byte word offset that identifies the head 5338 * element within the ring. 5339 * (The head offset variable has type A_UINT32.) 5340 * Valid for HW_TO_SW and SW_TO_SW rings. 5341 * dword5 - b'0:31 - ring_head_offset32_remote_addr_hi: 5342 * Upper 32 bits of memory address of the remote variable 5343 * storing the 4-byte word offset that identifies the head 5344 * element within the ring. 5345 * (The head offset variable has type A_UINT32.) 5346 * Valid for HW_TO_SW and SW_TO_SW rings. 5347 * dword6 - b'0:31 - ring_tail_offset32_remote_addr_lo: 5348 * Lower 32 bits of memory address of the remote variable 5349 * storing the 4-byte word offset that identifies the tail 5350 * element within the ring. 5351 * (The tail offset variable has type A_UINT32.) 5352 * Valid for HW_TO_SW and SW_TO_SW rings. 5353 * dword7 - b'0:31 - ring_tail_offset32_remote_addr_hi: 5354 * Upper 32 bits of memory address of the remote variable 5355 * storing the 4-byte word offset that identifies the tail 5356 * element within the ring. 5357 * (The tail offset variable has type A_UINT32.) 5358 * Valid for HW_TO_SW and SW_TO_SW rings. 5359 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 5360 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5361 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 5362 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5363 * dword10 - b'0:31 - ring_msi_data: MSI data 5364 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 5365 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5366 * dword11 - b'0:14 - intr_batch_counter_th: 5367 * batch counter threshold is in units of 4-byte words. 5368 * HW internally maintains and increments batch count. 5369 * (see SRING spec for detail description). 5370 * When batch count reaches threshold value, an interrupt 5371 * is generated by HW. 5372 * b'15 - sw_intr_mode: 5373 * This configuration shall be static. 5374 * Only programmed at power up. 5375 * 0: generate pulse style sw interrupts 5376 * 1: generate level style sw interrupts 5377 * b'16:31 - intr_timer_th: 5378 * The timer init value when timer is idle or is 5379 * initialized to start downcounting. 5380 * In 8us units (to cover a range of 0 to 524 ms) 5381 * dword12 - b'0:15 - intr_low_threshold: 5382 * Used only by Consumer ring to generate ring_sw_int_p. 5383 * Ring entries low threshold water mark, that is used 5384 * in combination with the interrupt timer as well as 5385 * the the clearing of the level interrupt. 5386 * b'16:18 - prefetch_timer_cfg: 5387 * Used only by Consumer ring to set timer mode to 5388 * support Application prefetch handling. 5389 * The external tail offset/pointer will be updated 5390 * at following intervals: 5391 * 3'b000: (Prefetch feature disabled; used only for debug) 5392 * 3'b001: 1 usec 5393 * 3'b010: 4 usec 5394 * 3'b011: 8 usec (default) 5395 * 3'b100: 16 usec 5396 * Others: Reserved 5397 * b'19 - response_required: 5398 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 5399 * b'20 - ipa_drop_flag: 5400 Indicates that host will config ipa drop threshold percentage 5401 * b'21:31 - reserved: reserved for future use 5402 * dword13 - b'0:7 - ipa drop low threshold percentage: 5403 * b'8:15 - ipa drop high threshold percentage: 5404 * b'16:31 - Reserved 5405 */ 5406 PREPACK struct htt_sring_setup_t { 5407 A_UINT32 msg_type: 8, 5408 pdev_id: 8, 5409 ring_id: 8, 5410 ring_type: 8; 5411 A_UINT32 ring_base_addr_lo; 5412 A_UINT32 ring_base_addr_hi; 5413 A_UINT32 ring_size: 16, 5414 ring_entry_size: 8, 5415 ring_misc_cfg_flag: 8; 5416 A_UINT32 ring_head_offset32_remote_addr_lo; 5417 A_UINT32 ring_head_offset32_remote_addr_hi; 5418 A_UINT32 ring_tail_offset32_remote_addr_lo; 5419 A_UINT32 ring_tail_offset32_remote_addr_hi; 5420 A_UINT32 ring_msi_addr_lo; 5421 A_UINT32 ring_msi_addr_hi; 5422 A_UINT32 ring_msi_data; 5423 A_UINT32 intr_batch_counter_th: 15, 5424 sw_intr_mode: 1, 5425 intr_timer_th: 16; 5426 A_UINT32 intr_low_threshold: 16, 5427 prefetch_timer_cfg: 3, 5428 response_required: 1, 5429 ipa_drop_flag: 1, 5430 reserved1: 11; 5431 A_UINT32 ipa_drop_low_threshold: 8, 5432 ipa_drop_high_threshold: 8, 5433 reserved: 16; 5434 } POSTPACK; 5435 5436 enum htt_srng_ring_type { 5437 HTT_HW_TO_SW_RING = 0, 5438 HTT_SW_TO_HW_RING, 5439 HTT_SW_TO_SW_RING, 5440 /* Insert new ring types above this line */ 5441 }; 5442 5443 enum htt_srng_ring_id { 5444 HTT_RXDMA_HOST_BUF_RING = 0, /* Used by FW to feed remote buffers and update remote packets */ 5445 HTT_RXDMA_MONITOR_STATUS_RING, /* For getting all PPDU/MPDU/MSDU status deescriptors on host for monitor VAP or packet log purposes */ 5446 HTT_RXDMA_MONITOR_BUF_RING, /* For feeding free host buffers to RxDMA for monitor traffic upload */ 5447 HTT_RXDMA_MONITOR_DESC_RING, /* For providing free LINK_DESC to RXDMA for monitor traffic upload */ 5448 HTT_RXDMA_MONITOR_DEST_RING, /* Per MPDU indication to host for monitor traffic upload */ 5449 HTT_HOST1_TO_FW_RXBUF_RING, /* (mobile only) used by host to provide remote RX buffers */ 5450 HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */ 5451 HTT_RXDMA_NON_MONITOR_DEST_RING, /* Per MDPU indication to host for non-monitor RxDMA traffic upload */ 5452 HTT_RXDMA_HOST_BUF_RING2, /* Second ring used by FW to feed removed buffers and update removed packets */ 5453 HTT_TX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */ 5454 HTT_TX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ 5455 HTT_RX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */ 5456 HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ 5457 HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */ 5458 HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */ 5459 HTT_HOST4_TO_FW_RXBUF_RING, /* fourth ring used by host to provide buffers for MGMT packets */ 5460 /* Add Other SRING which can't be directly configured by host software above this line */ 5461 }; 5462 5463 #define HTT_SRING_SETUP_SZ (sizeof(struct htt_sring_setup_t)) 5464 5465 #define HTT_SRING_SETUP_PDEV_ID_M 0x0000ff00 5466 #define HTT_SRING_SETUP_PDEV_ID_S 8 5467 #define HTT_SRING_SETUP_PDEV_ID_GET(_var) \ 5468 (((_var) & HTT_SRING_SETUP_PDEV_ID_M) >> \ 5469 HTT_SRING_SETUP_PDEV_ID_S) 5470 #define HTT_SRING_SETUP_PDEV_ID_SET(_var, _val) \ 5471 do { \ 5472 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PDEV_ID, _val); \ 5473 ((_var) |= ((_val) << HTT_SRING_SETUP_PDEV_ID_S)); \ 5474 } while (0) 5475 5476 #define HTT_SRING_SETUP_RING_ID_M 0x00ff0000 5477 #define HTT_SRING_SETUP_RING_ID_S 16 5478 #define HTT_SRING_SETUP_RING_ID_GET(_var) \ 5479 (((_var) & HTT_SRING_SETUP_RING_ID_M) >> \ 5480 HTT_SRING_SETUP_RING_ID_S) 5481 #define HTT_SRING_SETUP_RING_ID_SET(_var, _val) \ 5482 do { \ 5483 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_ID, _val); \ 5484 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_ID_S)); \ 5485 } while (0) 5486 5487 #define HTT_SRING_SETUP_RING_TYPE_M 0xff000000 5488 #define HTT_SRING_SETUP_RING_TYPE_S 24 5489 #define HTT_SRING_SETUP_RING_TYPE_GET(_var) \ 5490 (((_var) & HTT_SRING_SETUP_RING_TYPE_M) >> \ 5491 HTT_SRING_SETUP_RING_TYPE_S) 5492 #define HTT_SRING_SETUP_RING_TYPE_SET(_var, _val) \ 5493 do { \ 5494 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_TYPE, _val); \ 5495 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_TYPE_S)); \ 5496 } while (0) 5497 5498 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_M 0xffffffff 5499 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_S 0 5500 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_GET(_var) \ 5501 (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_LO_M) >> \ 5502 HTT_SRING_SETUP_RING_BASE_ADDR_LO_S) 5503 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_SET(_var, _val) \ 5504 do { \ 5505 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_LO, _val); \ 5506 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_LO_S)); \ 5507 } while (0) 5508 5509 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_M 0xffffffff 5510 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_S 0 5511 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_GET(_var) \ 5512 (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_HI_M) >> \ 5513 HTT_SRING_SETUP_RING_BASE_ADDR_HI_S) 5514 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_SET(_var, _val) \ 5515 do { \ 5516 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_HI, _val); \ 5517 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_HI_S)); \ 5518 } while (0) 5519 5520 #define HTT_SRING_SETUP_RING_SIZE_M 0x0000ffff 5521 #define HTT_SRING_SETUP_RING_SIZE_S 0 5522 #define HTT_SRING_SETUP_RING_SIZE_GET(_var) \ 5523 (((_var) & HTT_SRING_SETUP_RING_SIZE_M) >> \ 5524 HTT_SRING_SETUP_RING_SIZE_S) 5525 #define HTT_SRING_SETUP_RING_SIZE_SET(_var, _val) \ 5526 do { \ 5527 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_SIZE, _val); \ 5528 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_SIZE_S)); \ 5529 } while (0) 5530 5531 #define HTT_SRING_SETUP_ENTRY_SIZE_M 0x00ff0000 5532 #define HTT_SRING_SETUP_ENTRY_SIZE_S 16 5533 #define HTT_SRING_SETUP_ENTRY_SIZE_GET(_var) \ 5534 (((_var) & HTT_SRING_SETUP_ENTRY_SIZE_M) >> \ 5535 HTT_SRING_SETUP_ENTRY_SIZE_S) 5536 #define HTT_SRING_SETUP_ENTRY_SIZE_SET(_var, _val) \ 5537 do { \ 5538 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_ENTRY_SIZE, _val); \ 5539 ((_var) |= ((_val) << HTT_SRING_SETUP_ENTRY_SIZE_S)); \ 5540 } while (0) 5541 5542 #define HTT_SRING_SETUP_MISC_CFG_FLAG_M 0xff000000 5543 #define HTT_SRING_SETUP_MISC_CFG_FLAG_S 24 5544 #define HTT_SRING_SETUP_MISC_CFG_FLAG_GET(_var) \ 5545 (((_var) & HTT_SRING_SETUP_MISC_CFG_FLAG_M) >> \ 5546 HTT_SRING_SETUP_MISC_CFG_FLAG_S) 5547 #define HTT_SRING_SETUP_MISC_CFG_FLAG_SET(_var, _val) \ 5548 do { \ 5549 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_MISC_CFG_FLAG, _val); \ 5550 ((_var) |= ((_val) << HTT_SRING_SETUP_MISC_CFG_FLAG_S)); \ 5551 } while (0) 5552 5553 /* This control bit is applicable to only Producer, which updates Ring ID field 5554 * of each descriptor before pushing into the ring. 5555 * 0: updates ring_id(default) 5556 * 1: ring_id updating disabled */ 5557 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M 0x01000000 5558 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S 24 5559 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_GET(_var) \ 5560 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M) >> \ 5561 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S) 5562 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_SET(_var, _val) \ 5563 do { \ 5564 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE, _val); \ 5565 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S)); \ 5566 } while (0) 5567 5568 /* This control bit is applicable to only Producer, which updates Loopcnt field 5569 * of each descriptor before pushing into the ring. 5570 * 0: updates Loopcnt(default) 5571 * 1: Loopcnt updating disabled */ 5572 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M 0x02000000 5573 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S 25 5574 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_GET(_var) \ 5575 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M) >> \ 5576 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S) 5577 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_SET(_var, _val) \ 5578 do { \ 5579 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE, _val); \ 5580 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S)); \ 5581 } while (0) 5582 5583 /* Secured access enable/disable bit. SRNG drives value of this register bit 5584 * into security_id port of GXI/AXI. */ 5585 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M 0x04000000 5586 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S 26 5587 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_GET(_var) \ 5588 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M) >> \ 5589 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S) 5590 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_SET(_var, _val) \ 5591 do { \ 5592 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY, _val); \ 5593 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S)); \ 5594 } while (0) 5595 5596 /* During MSI write operation, SRNG drives value of this register bit into 5597 * swap bit of GXI/AXI. */ 5598 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M 0x08000000 5599 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S 27 5600 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_GET(_var) \ 5601 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ 5602 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) 5603 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \ 5604 do { \ 5605 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \ 5606 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ 5607 } while (0) 5608 5609 /* During Pointer write operation, SRNG drives value of this register bit into 5610 * swap bit of GXI/AXI. */ 5611 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M 0x10000000 5612 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S 28 5613 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_GET(_var) \ 5614 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M) >> \ 5615 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S) 5616 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_SET(_var, _val) \ 5617 do { \ 5618 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP, _val); \ 5619 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S)); \ 5620 } while (0) 5621 5622 /* During any data or TLV write operation, SRNG drives value of this register 5623 * bit into swap bit of GXI/AXI. */ 5624 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M 0x20000000 5625 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S 29 5626 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_GET(_var) \ 5627 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M) >> \ 5628 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S) 5629 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_SET(_var, _val) \ 5630 do { \ 5631 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP, _val); \ 5632 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S)); \ 5633 } while (0) 5634 5635 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED1 0x40000000 5636 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED2 0x80000000 5637 5638 5639 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff 5640 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 5641 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ 5642 (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ 5643 HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S) 5644 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ 5645 do { \ 5646 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ 5647 ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ 5648 } while (0) 5649 5650 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff 5651 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 5652 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ 5653 (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ 5654 HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S) 5655 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ 5656 do { \ 5657 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ 5658 ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ 5659 } while (0) 5660 5661 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff 5662 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 5663 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ 5664 (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ 5665 HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S) 5666 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ 5667 do { \ 5668 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ 5669 ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ 5670 } while (0) 5671 5672 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff 5673 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 5674 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ 5675 (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ 5676 HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S) 5677 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ 5678 do { \ 5679 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ 5680 ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ 5681 } while (0) 5682 5683 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_M 0xffffffff 5684 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_S 0 5685 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_GET(_var) \ 5686 (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_LO_M) >> \ 5687 HTT_SRING_SETUP_RING_MSI_ADDR_LO_S) 5688 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_SET(_var, _val) \ 5689 do { \ 5690 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_LO, _val); \ 5691 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_LO_S)); \ 5692 } while (0) 5693 5694 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_M 0xffffffff 5695 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_S 0 5696 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_GET(_var) \ 5697 (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_HI_M) >> \ 5698 HTT_SRING_SETUP_RING_MSI_ADDR_HI_S) 5699 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_SET(_var, _val) \ 5700 do { \ 5701 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_HI, _val); \ 5702 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_HI_S)); \ 5703 } while (0) 5704 5705 #define HTT_SRING_SETUP_RING_MSI_DATA_M 0xffffffff 5706 #define HTT_SRING_SETUP_RING_MSI_DATA_S 0 5707 #define HTT_SRING_SETUP_RING_MSI_DATA_GET(_var) \ 5708 (((_var) & HTT_SRING_SETUP_RING_MSI_DATA_M) >> \ 5709 HTT_SRING_SETUP_RING_MSI_DATA_S) 5710 #define HTT_SRING_SETUP_RING_MSI_DATA_SET(_var, _val) \ 5711 do { \ 5712 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_DATA, _val); \ 5713 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_DATA_S)); \ 5714 } while (0) 5715 5716 5717 5718 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M 0x00007fff 5719 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S 0 5720 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_GET(_var) \ 5721 (((_var) & HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M) >> \ 5722 HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S) 5723 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_SET(_var, _val) \ 5724 do { \ 5725 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH, _val); \ 5726 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S)); \ 5727 } while (0) 5728 5729 #define HTT_SRING_SETUP_SW_INTR_MODE_M 0x00008000 5730 #define HTT_SRING_SETUP_SW_INTR_MODE_S 15 5731 #define HTT_SRING_SETUP_SW_INTR_MODE_GET(_var) \ 5732 (((_var) & HTT_SRING_SETUP_SW_INTR_MODE_M) >> \ 5733 HTT_SRING_SETUP_SW_INTR_MODE_S) 5734 #define HTT_SRING_SETUP_SW_INTR_MODE_SET(_var, _val) \ 5735 do { \ 5736 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_SW_INTR_MODE, _val); \ 5737 ((_var) |= ((_val) << HTT_SRING_SETUP_SW_INTR_MODE_S)); \ 5738 } while (0) 5739 5740 #define HTT_SRING_SETUP_INTR_TIMER_TH_M 0xffff0000 5741 #define HTT_SRING_SETUP_INTR_TIMER_TH_S 16 5742 #define HTT_SRING_SETUP_INTR_TIMER_TH_GET(_var) \ 5743 (((_var) & HTT_SRING_SETUP_INTR_TIMER_TH_M) >> \ 5744 HTT_SRING_SETUP_INTR_TIMER_TH_S) 5745 #define HTT_SRING_SETUP_INTR_TIMER_TH_SET(_var, _val) \ 5746 do { \ 5747 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_TIMER_TH, _val); \ 5748 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_TIMER_TH_S)); \ 5749 } while (0) 5750 5751 #define HTT_SRING_SETUP_INTR_LOW_TH_M 0x0000ffff 5752 #define HTT_SRING_SETUP_INTR_LOW_TH_S 0 5753 #define HTT_SRING_SETUP_INTR_LOW_TH_GET(_var) \ 5754 (((_var) & HTT_SRING_SETUP_INTR_LOW_TH_M) >> \ 5755 HTT_SRING_SETUP_INTR_LOW_TH_S) 5756 #define HTT_SRING_SETUP_INTR_LOW_TH_SET(_var, _val) \ 5757 do { \ 5758 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_LOW_TH, _val); \ 5759 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_LOW_TH_S)); \ 5760 } while (0) 5761 5762 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M 0x00070000 5763 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S 16 5764 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_GET(_var) \ 5765 (((_var) & HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M) >> \ 5766 HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S) 5767 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_SET(_var, _val) \ 5768 do { \ 5769 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PREFETCH_TIMER_CFG, _val); \ 5770 ((_var) |= ((_val) << HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S)); \ 5771 } while (0) 5772 5773 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_M 0x00080000 5774 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_S 19 5775 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_GET(_var) \ 5776 (((_var) & HTT_SRING_SETUP_RESPONSE_REQUIRED_M) >> \ 5777 HTT_SRING_SETUP_RESPONSE_REQUIRED_S) 5778 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_SET(_var, _val) \ 5779 do { \ 5780 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RESPONSE_REQUIRED, _val); \ 5781 ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \ 5782 } while (0) 5783 5784 5785 /** 5786 * @brief host -> target RX ring selection config message 5787 * 5788 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 5789 * 5790 * @details 5791 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 5792 * configure RXDMA rings. 5793 * The configuration is per ring based and includes both packet subtypes 5794 * and PPDU/MPDU TLVs. 5795 * 5796 * The message would appear as follows: 5797 * 5798 * |31 29|28|27|26|25|24|23|22|21 19|18 16|15 | 11| 10|9 8|7 0| 5799 * |-----+--+--+--+--+--+-----------------+----+---+---+---+---------------| 5800 * |rsvd1|ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 5801 * |--------------------------+-----+-----+--------------------------------| 5802 * | rsvd2 |RX|RXHDL| CLD | CLC | CLM | ring_buffer_size | 5803 * |-----------------------------------------------------------------------| 5804 * | packet_type_enable_flags_0 | 5805 * |-----------------------------------------------------------------------| 5806 * | packet_type_enable_flags_1 | 5807 * |-----------------------------------------------------------------------| 5808 * | packet_type_enable_flags_2 | 5809 * |-----------------------------------------------------------------------| 5810 * | packet_type_enable_flags_3 | 5811 * |-----------------------------------------------------------------------| 5812 * | tlv_filter_in_flags | 5813 * |--------------------------------------+--------------------------------| 5814 * | rx_header_offset | rx_packet_offset | 5815 * |--------------------------------------+--------------------------------| 5816 * | rx_mpdu_start_offset | rx_mpdu_end_offset | 5817 * |--------------------------------------+--------------------------------| 5818 * | rx_msdu_start_offset | rx_msdu_end_offset | 5819 * |--------------------------------------+--------------------------------| 5820 * | rsvd3 | rx_attention_offset | 5821 * |-----------------------------------------------------------------------| 5822 * | rsvd4 | mo| fp| rx_drop_threshold | 5823 * | |ndp|ndp| | 5824 * |-----------------------------------------------------------------------| 5825 * Where: 5826 * PS = pkt_swap 5827 * SS = status_swap 5828 * OV = rx_offsets_valid 5829 * DT = drop_thresh_valid 5830 * ED = packet type enable data flags fields present / valid 5831 * CLM = config_length_mgmt 5832 * CLC = config_length_ctrl 5833 * CLD = config_length_data 5834 * RXHDL = rx_hdr_len 5835 * RX = rxpcu_filter_enable_flag 5836 * The message is interpreted as follows: 5837 * dword0 - b'0:7 - msg_type: This will be set to 5838 * 0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG) 5839 * b'8:15 - pdev_id: 5840 * 0 (for rings at SOC/UMAC level), 5841 * 1/2/3 mac id (for rings at LMAC level) 5842 * b'16:23 - ring_id : Identify the ring to configure. 5843 * More details can be got from enum htt_srng_ring_id 5844 * b'24 - status_swap (SS): 1 is to swap status TLV - refer to 5845 * BUF_RING_CFG_0 defs within HW .h files, 5846 * e.g. wmac_top_reg_seq_hwioreg.h 5847 * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to 5848 * BUF_RING_CFG_0 defs within HW .h files, 5849 * e.g. wmac_top_reg_seq_hwioreg.h 5850 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 5851 * configuration fields are valid 5852 * b'27 - drop_thresh_valid (DT): flag to indicate if the 5853 * rx_drop_threshold field is valid 5854 * b'28 - rx_mon_global_en: Enable/Disable global register 5855 * configuration in Rx monitor module. 5856 * b'29 - packet_type_enable_data: flag to indicate whether 5857 * newer packet_type_enable_data_flags_* are valid or not 5858 * If not set, will use pkt_type_enable_flags for both status 5859 * and full pkt buffer configuration. 5860 * b'30:31 - rsvd1: reserved for future use 5861 * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, 5862 * in byte units. 5863 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5864 * b'16:18 - config_length_mgmt (MGMT): 5865 * Represents the length of mpdu bytes for mgmt pkt. 5866 * valid values: 5867 * 001 - 64bytes 5868 * 010 - 128bytes 5869 * 100 - 256bytes 5870 * 111 - Full mpdu bytes 5871 * b'19:21 - config_length_ctrl (CTRL): 5872 * Represents the length of mpdu bytes for ctrl pkt. 5873 * valid values: 5874 * 001 - 64bytes 5875 * 010 - 128bytes 5876 * 100 - 256bytes 5877 * 111 - Full mpdu bytes 5878 * b'22:24 - config_length_data (DATA): 5879 * Represents the length of mpdu bytes for data pkt. 5880 * valid values: 5881 * 001 - 64bytes 5882 * 010 - 128bytes 5883 * 100 - 256bytes 5884 * 111 - Full mpdu bytes 5885 * b'25:26 - rx_hdr_len: 5886 * Specifies the number of bytes of recvd packet to copy 5887 * into the rx_hdr tlv. 5888 * supported values for now by host: 5889 * 01 - 64bytes 5890 * 10 - 128bytes 5891 * 11 - 256bytes 5892 * default - 128 bytes 5893 * b'27 - rxpcu_filter_enable_flag 5894 * For Scan Radio Host CPU utilization is very high. 5895 * In order to reduce CPU utilization we need to filter out 5896 * certain configured MAC frames. 5897 * To filter out configured MAC address frames, RxPCU should 5898 * be zero which means allow all frames for MD at RxOLE 5899 * host wil fiter out frames. 5900 * RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out) 5901 * b'28:31 - rsvd2: Reserved for future use 5902 * dword2 - b'0:31 - packet_type_enable_flags_0: 5903 * Enable MGMT packet from 0b0000 to 0b1001 5904 * bits from low to high: FP, MD, MO - 3 bits 5905 * FP: Filter_Pass 5906 * MD: Monitor_Direct 5907 * MO: Monitor_Other 5908 * 10 mgmt subtypes * 3 bits -> 30 bits 5909 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 5910 * dword3 - b'0:31 - packet_type_enable_flags_1: 5911 * Enable MGMT packet from 0b1010 to 0b1111 5912 * bits from low to high: FP, MD, MO - 3 bits 5913 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 5914 * dword4 - b'0:31 - packet_type_enable_flags_2: 5915 * Enable CTRL packet from 0b0000 to 0b1001 5916 * bits from low to high: FP, MD, MO - 3 bits 5917 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 5918 * dword5 - b'0:31 - packet_type_enable_flags_3: 5919 * Enable CTRL packet from 0b1010 to 0b1111, 5920 * MCAST_DATA, UCAST_DATA, NULL_DATA 5921 * bits from low to high: FP, MD, MO - 3 bits 5922 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 5923 * dword6 - b'0:31 - tlv_filter_in_flags: 5924 * Filter in Attention/MPDU/PPDU/Header/User tlvs 5925 * Refer to CFG_TLV_FILTER_IN_FLAG defs 5926 * dword7 - b'0:15 - rx_packet_offset: rx_packet_offset in byte units 5927 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5928 * A value of 0 will be considered as ignore this config. 5929 * Refer to BUF_RING_CFG_1 defs within HW .h files, 5930 * e.g. wmac_top_reg_seq_hwioreg.h 5931 * - b'16:31 - rx_header_offset: rx_header_offset in byte units 5932 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5933 * A value of 0 will be considered as ignore this config. 5934 * Refer to BUF_RING_CFG_1 defs within HW .h files, 5935 * e.g. wmac_top_reg_seq_hwioreg.h 5936 * dword8 - b'0:15 - rx_mpdu_end_offset: rx_mpdu_end_offset in byte units 5937 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5938 * A value of 0 will be considered as ignore this config. 5939 * Refer to BUF_RING_CFG_2 defs within HW .h files, 5940 * e.g. wmac_top_reg_seq_hwioreg.h 5941 * - b'16:31 - rx_mpdu_start_offset: rx_mpdu_start_offset in byte units 5942 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5943 * A value of 0 will be considered as ignore this config. 5944 * Refer to BUF_RING_CFG_2 defs within HW .h files, 5945 * e.g. wmac_top_reg_seq_hwioreg.h 5946 * dword9 - b'0:15 - rx_msdu_end_offset: rx_msdu_end_offset in byte units 5947 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5948 * A value of 0 will be considered as ignore this config. 5949 * Refer to BUF_RING_CFG_3 defs within HW .h files, 5950 * e.g. wmac_top_reg_seq_hwioreg.h 5951 * - b'16:31 - rx_msdu_start_offset: rx_msdu_start_offset in byte units 5952 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5953 * A value of 0 will be considered as ignore this config. 5954 * Refer to BUF_RING_CFG_3 defs within HW .h files, 5955 * e.g. wmac_top_reg_seq_hwioreg.h 5956 * dword10- b'0:15 - rx_attention_offset: rx_attention_offset in byte units 5957 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5958 * A value of 0 will be considered as ignore this config. 5959 * Refer to BUF_RING_CFG_4 defs within HW .h files, 5960 * e.g. wmac_top_reg_seq_hwioreg.h 5961 * - b'16:31 - rsvd3 for future use 5962 * dword11- b'9:0 - rx_drop_threshold: Threshold configured in monitor mode 5963 * to source rings. Consumer drops packets if the available 5964 * words in the ring falls below the configured threshold 5965 * value. 5966 * - b'10 - fp_ndp: Flag to indicate FP NDP status tlv is subscribed 5967 * by host. 1 -> subscribed 5968 * - b'11 - mo_ndp: Flag to indicate MO NDP status tlv is subscribed 5969 * by host. 1 -> subscribed 5970 * - b'12 - fp_phy_err: Flag to indicate FP PHY status tlv is 5971 * subscribed by host. 1 -> subscribed 5972 * - b'13:14 - fp_phy_err_buf_src: This indicates the source ring 5973 * selection for the FP PHY ERR status tlv. 5974 * 0 - wbm2rxdma_buf_source_ring 5975 * 1 - fw2rxdma_buf_source_ring 5976 * 2 - sw2rxdma_buf_source_ring 5977 * 3 - no_buffer_ring 5978 * - b'15:16 - fp_phy_err_buf_dest: This indicates the destination ring 5979 * selection for the FP PHY ERR status tlv. 5980 * 0 - rxdma_release_ring 5981 * 1 - rxdma2fw_ring 5982 * 2 - rxdma2sw_ring 5983 * 3 - rxdma2reo_ring 5984 * - b'17:19 - pkt_type_en_msdu_or_mpdu_logging 5985 * b'17 - Enables MSDU/MPDU logging for frames of MGMT type 5986 * b'18 - Enables MSDU/MPDU logging for frames of CTRL type 5987 * b'19 - Enables MSDU/MPDU logging for frames of DATA type 5988 * - b'20 - dma_mpdu_mgmt: 1: MPDU level logging 5989 * 0: MSDU level logging 5990 * - b'21 - dma_mpdu_ctrl: 1: MPDU level logging 5991 * 0: MSDU level logging 5992 * - b'22 - dma_mpdu_data: 1: MPDU level logging 5993 * 0: MSDU level logging 5994 * - b'23 - word_mask_compaction: enable/disable word mask for 5995 * mpdu/msdu start/end tlvs 5996 * - b'24 - rbm_override_enable: enabling/disabling return buffer 5997 * manager override 5998 * - b'25:28 - rbm_override_val: return buffer manager override value 5999 * dword12- b'0:31 - phy_err_mask: This field is to select the fp phy errors 6000 * which have to be posted to host from phy. 6001 * Corresponding to errors defined in 6002 * phyrx_abort_request_reason enums 0 to 31. 6003 * Refer to RXPCU register definition header files for the 6004 * phyrx_abort_request_reason enum definition. 6005 * dword13- b'0:31 - phy_err_mask_cont: This field is to select the fp phy 6006 * errors which have to be posted to host from phy. 6007 * Corresponding to errors defined in 6008 * phyrx_abort_request_reason enums 32 to 63. 6009 * Refer to RXPCU register definition header files for the 6010 * phyrx_abort_request_reason enum definition. 6011 * dword14- b'0:15 - rx_mpdu_start_word_mask: word mask for rx mpdu start, 6012 * applicable if word mask enabled 6013 * - b'16:18 - rx_mpdu_end_word_mask: word mask value for rx mpdu end, 6014 * applicable if word mask enabled 6015 * - b'19:31 - rsvd7 6016 * dword15- b'0:16 - rx_msdu_end_word_mask 6017 * - b'17:31 - rsvd5 6018 * dword17- b'0 - en_rx_tlv_pkt_offset: 6019 * 0: RX_PKT TLV logging at offset 0 for the subsequent 6020 * buffer 6021 * 1: RX_PKT TLV logging at specified offset for the 6022 * subsequent buffer 6023 * b`15:1 - rx_pkt_tlv_offset: Qword offset for rx_packet TLVs. 6024 * dword18- b'0:19 - rx_mpdu_start_wmask_v2 - wmask address for rx mpdu start 6025 * b'20-27 - rx_mpdu_end_wmask_v2 - wmask addr for rx mpdu end tlv addr 6026 * b'28-31 - reserved 6027 * dword19- b'0-19 - rx_msdu_end_wmask_v2 6028 * b'20-31 - reserved 6029 * dword20- b'0:19 - rx_ppdu_end_user_stats_wmask_v2 6030 * offset for ppdu_end_user_stats tlv 6031 * b'20-31 - reserved 6032 * dword21- b'0-31 - packet_type_enable_fpmo_flags_0 - filter bmap for each 6033 * mode mgmt/ctrl type/subtype for fpmo mode 6034 * dword22- b'0-31 - packet_type_enable_fpmo_flags_1 - filter bmap for each 6035 * mode ctrl/data type/subtype for fpmo mode 6036 * dword23- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full 6037 * pkt buffer each mode MGMT type/subtype 6038 * dword24- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full 6039 * pkt buffer each mode MGMT type/subtype 6040 * dword25- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full 6041 * pkt buffer each mode CTRL type/subtype 6042 * dword26- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full 6043 * pkt buffer each mode CTRL/DATA type/subtype 6044 * dword27- b'0-31 - packet_type_enable_data_fpmo_flags_0 - filter bmap for 6045 * full pkt buffer each mode mgmt/ctrl type/subtype for 6046 * fpmo mode 6047 * dword28- b'0-31 - packet_type_enable_data_fpmo_flags_1 - filter bmap for 6048 * full pkt buffer each mode ctrl/data type/subtype for 6049 * fpmo mode 6050 */ 6051 PREPACK struct htt_rx_ring_selection_cfg_t { 6052 A_UINT32 msg_type: 8, 6053 pdev_id: 8, 6054 ring_id: 8, 6055 status_swap: 1, 6056 pkt_swap: 1, 6057 rx_offsets_valid: 1, 6058 drop_thresh_valid: 1, 6059 rx_mon_global_en: 1, 6060 packet_type_enable_data: 1, 6061 rsvd1: 2; 6062 A_UINT32 ring_buffer_size: 16, 6063 config_length_mgmt:3, 6064 config_length_ctrl:3, 6065 config_length_data:3, 6066 rx_hdr_len: 2, 6067 rxpcu_filter_enable_flag:1, 6068 rsvd2: 4; 6069 A_UINT32 packet_type_enable_flags_0; 6070 A_UINT32 packet_type_enable_flags_1; 6071 A_UINT32 packet_type_enable_flags_2; 6072 A_UINT32 packet_type_enable_flags_3; 6073 A_UINT32 tlv_filter_in_flags; 6074 A_UINT32 rx_packet_offset: 16, 6075 rx_header_offset: 16; 6076 A_UINT32 rx_mpdu_end_offset: 16, 6077 rx_mpdu_start_offset: 16; 6078 A_UINT32 rx_msdu_end_offset: 16, 6079 rx_msdu_start_offset: 16; 6080 A_UINT32 rx_attn_offset: 16, 6081 rsvd3: 16; 6082 A_UINT32 rx_drop_threshold: 10, 6083 fp_ndp: 1, 6084 mo_ndp: 1, 6085 fp_phy_err: 1, 6086 fp_phy_err_buf_src: 2, 6087 fp_phy_err_buf_dest: 2, 6088 pkt_type_enable_msdu_or_mpdu_logging:3, 6089 dma_mpdu_mgmt: 1, 6090 dma_mpdu_ctrl: 1, 6091 dma_mpdu_data: 1, 6092 word_mask_compaction_enable:1, 6093 rbm_override_enable: 1, 6094 rbm_override_val: 4, 6095 rsvd4: 3; 6096 A_UINT32 phy_err_mask; 6097 A_UINT32 phy_err_mask_cont; 6098 A_UINT32 rx_mpdu_start_word_mask:16, 6099 rx_mpdu_end_word_mask: 3, 6100 rsvd7: 13; 6101 A_UINT32 rx_msdu_end_word_mask: 17, 6102 rsvd5: 15; 6103 A_UINT32 en_rx_tlv_pkt_offset: 1, 6104 rx_pkt_tlv_offset: 15, 6105 rsvd6: 16; 6106 A_UINT32 rx_mpdu_start_word_mask_v2: 20, 6107 rx_mpdu_end_word_mask_v2: 8, 6108 rsvd8: 4; 6109 A_UINT32 rx_msdu_end_word_mask_v2: 20, 6110 rsvd9: 12; 6111 A_UINT32 rx_ppdu_end_usr_stats_word_mask_v2: 20, 6112 rsvd10: 12; 6113 A_UINT32 packet_type_enable_fpmo_flags0; 6114 A_UINT32 packet_type_enable_fpmo_flags1; 6115 A_UINT32 packet_type_enable_data_flags_0; 6116 A_UINT32 packet_type_enable_data_flags_1; 6117 A_UINT32 packet_type_enable_data_flags_2; 6118 A_UINT32 packet_type_enable_data_flags_3; 6119 A_UINT32 packet_type_enable_data_fpmo_flags0; 6120 A_UINT32 packet_type_enable_data_fpmo_flags1; 6121 } POSTPACK; 6122 6123 #define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t)) 6124 6125 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M 0x0000ff00 6126 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_S 8 6127 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_GET(_var) \ 6128 (((_var) & HTT_RX_RING_SELECTION_CFG_PDEV_ID_M) >> \ 6129 HTT_RX_RING_SELECTION_CFG_PDEV_ID_S) 6130 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_SET(_var, _val) \ 6131 do { \ 6132 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PDEV_ID, _val); \ 6133 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PDEV_ID_S)); \ 6134 } while (0) 6135 6136 #define HTT_RX_RING_SELECTION_CFG_RING_ID_M 0x00ff0000 6137 #define HTT_RX_RING_SELECTION_CFG_RING_ID_S 16 6138 #define HTT_RX_RING_SELECTION_CFG_RING_ID_GET(_var) \ 6139 (((_var) & HTT_RX_RING_SELECTION_CFG_RING_ID_M) >> \ 6140 HTT_RX_RING_SELECTION_CFG_RING_ID_S) 6141 #define HTT_RX_RING_SELECTION_CFG_RING_ID_SET(_var, _val) \ 6142 do { \ 6143 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_ID, _val); \ 6144 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_ID_S)); \ 6145 } while (0) 6146 6147 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M 0x01000000 6148 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S 24 6149 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_GET(_var) \ 6150 (((_var) & HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M) >> \ 6151 HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S) 6152 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SET(_var, _val) \ 6153 do { \ 6154 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP, _val); \ 6155 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S)); \ 6156 } while (0) 6157 6158 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M 0x02000000 6159 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S 25 6160 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_GET(_var) \ 6161 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M) >> \ 6162 HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S) 6163 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SET(_var, _val) \ 6164 do { \ 6165 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP, _val); \ 6166 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \ 6167 } while (0) 6168 6169 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M 0x04000000 6170 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S 26 6171 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_GET(_var) \ 6172 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M) >> \ 6173 HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S) 6174 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_SET(_var, _val) \ 6175 do { \ 6176 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID, _val); \ 6177 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)); \ 6178 } while (0) 6179 6180 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M 0x08000000 6181 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S 27 6182 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_GET(_var) \ 6183 (((_var) & HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M) >> \ 6184 HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S) 6185 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_SET(_var, _val) \ 6186 do { \ 6187 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID, _val); \ 6188 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)); \ 6189 } while (0) 6190 6191 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M 0x10000000 6192 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S 28 6193 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_GET(_var) \ 6194 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M) >> \ 6195 HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S) 6196 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_SET(_var, _val) \ 6197 do { \ 6198 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN, _val); \ 6199 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S)); \ 6200 } while (0) 6201 6202 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_M 0x20000000 6203 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S 29 6204 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_GET(_var) \ 6205 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_M) >> \ 6206 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S) 6207 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_SET(_var, _val) \ 6208 do { \ 6209 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA, _val); \ 6210 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)); \ 6211 } while (0) 6212 6213 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff 6214 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0 6215 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \ 6216 (((_var) & HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M) >> \ 6217 HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S) 6218 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_SET(_var, _val) \ 6219 do { \ 6220 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE, _val); \ 6221 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S)); \ 6222 } while (0) 6223 6224 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M 0x00070000 6225 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S 16 6226 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_GET(_var) \ 6227 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M) >> \ 6228 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S) 6229 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \ 6230 do { \ 6231 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT, _val); \ 6232 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S)); \ 6233 } while (0) 6234 6235 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M 0x00380000 6236 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S 19 6237 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_GET(_var) \ 6238 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M) >> \ 6239 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S) 6240 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \ 6241 do { \ 6242 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL, _val); \ 6243 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S)); \ 6244 } while (0) 6245 6246 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M 0x01C00000 6247 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S 22 6248 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_GET(_var) \ 6249 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M) >> \ 6250 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S) 6251 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \ 6252 do { \ 6253 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA, _val); \ 6254 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S)); \ 6255 } while (0) 6256 6257 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M 0x06000000 6258 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S 25 6259 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_GET(_var) \ 6260 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \ 6261 HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) 6262 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_SET(_var, _val) \ 6263 do { \ 6264 HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN, _val); \ 6265 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\ 6266 } while(0) 6267 6268 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000 6269 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S 27 6270 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_GET(_var) \ 6271 (((_var) & HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M) >> \ 6272 HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S) 6273 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_SET(_var, _val) \ 6274 do { \ 6275 HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER, _val); \ 6276 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S));\ 6277 } while(0) 6278 6279 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M 0xffffffff 6280 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S 0 6281 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_GET(_var) \ 6282 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M) >> \ 6283 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S) 6284 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_SET(_var, _val) \ 6285 do { \ 6286 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0, _val); \ 6287 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S)); \ 6288 } while (0) 6289 6290 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M 0xffffffff 6291 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S 0 6292 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_GET(_var) \ 6293 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M) >> \ 6294 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S) 6295 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_SET(_var, _val) \ 6296 do { \ 6297 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1, _val); \ 6298 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S)); \ 6299 } while (0) 6300 6301 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M 0xffffffff 6302 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S 0 6303 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_GET(_var) \ 6304 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M) >> \ 6305 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S) 6306 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_SET(_var, _val) \ 6307 do { \ 6308 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2, _val); \ 6309 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S)); \ 6310 } while (0) 6311 6312 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M 0xffffffff 6313 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S 0 6314 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_GET(_var) \ 6315 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M) >> \ 6316 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S) 6317 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_SET(_var, _val) \ 6318 do { \ 6319 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3, _val); \ 6320 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S)); \ 6321 } while (0) 6322 6323 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M 0xffffffff 6324 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S 0 6325 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_GET(_var) \ 6326 (((_var) & HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M) >> \ 6327 HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S) 6328 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_SET(_var, _val) \ 6329 do { \ 6330 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG, _val); \ 6331 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \ 6332 } while (0) 6333 6334 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M 0x0000ffff 6335 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S 0 6336 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_GET(_var) \ 6337 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M) >> \ 6338 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S) 6339 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_SET(_var, _val) \ 6340 do { \ 6341 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET, _val); \ 6342 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)); \ 6343 } while (0) 6344 6345 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M 0xffff0000 6346 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S 16 6347 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_GET(_var) \ 6348 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M) >> \ 6349 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S) 6350 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_SET(_var, _val) \ 6351 do { \ 6352 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET, _val); \ 6353 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)); \ 6354 } while (0) 6355 6356 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M 0x0000ffff 6357 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S 0 6358 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_GET(_var) \ 6359 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M) >> \ 6360 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S) 6361 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_SET(_var, _val) \ 6362 do { \ 6363 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET, _val); \ 6364 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)); \ 6365 } while (0) 6366 6367 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M 0xffff0000 6368 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S 16 6369 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_GET(_var) \ 6370 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M) >> \ 6371 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S) 6372 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_SET(_var, _val) \ 6373 do { \ 6374 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET, _val); \ 6375 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)); \ 6376 } while (0) 6377 6378 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M 0x0000ffff 6379 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S 0 6380 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_GET(_var) \ 6381 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M) >> \ 6382 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S) 6383 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_SET(_var, _val) \ 6384 do { \ 6385 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET, _val); \ 6386 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)); \ 6387 } while (0) 6388 6389 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M 0xffff0000 6390 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S 16 6391 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_GET(_var) \ 6392 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M) >> \ 6393 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S) 6394 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_SET(_var, _val) \ 6395 do { \ 6396 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET, _val); \ 6397 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)); \ 6398 } while (0) 6399 6400 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M 0x0000ffff 6401 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S 0 6402 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_GET(_var) \ 6403 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M) >> \ 6404 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S) 6405 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_SET(_var, _val) \ 6406 do { \ 6407 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET, _val); \ 6408 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)); \ 6409 } while (0) 6410 6411 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M 0x000003ff 6412 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S 0 6413 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_GET(_var) \ 6414 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M) >> \ 6415 HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S) 6416 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(_var, _val) \ 6417 do { \ 6418 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD, _val); \ 6419 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)); \ 6420 } while (0) 6421 6422 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_M 0x00000400 6423 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_S 10 6424 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_GET(_var) \ 6425 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_NDP_M) >> \ 6426 HTT_RX_RING_SELECTION_CFG_FP_NDP_S) 6427 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_SET(_var, _val) \ 6428 do { \ 6429 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_NDP, _val); \ 6430 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_NDP_S)); \ 6431 } while (0) 6432 6433 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_M 0x00000800 6434 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_S 11 6435 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_GET(_var) \ 6436 (((_var) & HTT_RX_RING_SELECTION_CFG_MO_NDP_M) >> \ 6437 HTT_RX_RING_SELECTION_CFG_MO_NDP_S) 6438 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_SET(_var, _val) \ 6439 do { \ 6440 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_MO_NDP, _val); \ 6441 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_MO_NDP_S)); \ 6442 } while (0) 6443 6444 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M 0x00001000 6445 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S 12 6446 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_GET(_var) \ 6447 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M) >> \ 6448 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S) 6449 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_SET(_var, _val) \ 6450 do { \ 6451 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR, _val); \ 6452 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S)); \ 6453 } while (0) 6454 6455 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M 0x00006000 6456 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S 13 6457 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_GET(_var) \ 6458 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M) >> \ 6459 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S) 6460 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_SET(_var, _val) \ 6461 do { \ 6462 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC, _val); \ 6463 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S)); \ 6464 } while (0) 6465 6466 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M 0x00018000 6467 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S 15 6468 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_GET(_var) \ 6469 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M) >> \ 6470 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S) 6471 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_SET(_var, _val) \ 6472 do { \ 6473 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST, _val); \ 6474 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S)); \ 6475 } while (0) 6476 6477 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M 0x000E0000 6478 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S 17 6479 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_GET(_var) \ 6480 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M) >> \ 6481 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S) 6482 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_SET(_var, _val) \ 6483 do { \ 6484 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING, _val); \ 6485 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S)); \ 6486 } while (0) 6487 6488 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M 0x00100000 6489 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S 20 6490 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_GET(_var) \ 6491 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M) >> \ 6492 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S) 6493 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_SET(_var, _val) \ 6494 do { \ 6495 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT, _val); \ 6496 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S)); \ 6497 } while (0) 6498 6499 6500 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M 0x00200000 6501 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S 21 6502 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_GET(_var) \ 6503 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M) >> \ 6504 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S) 6505 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_SET(_var, _val) \ 6506 do { \ 6507 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL, _val); \ 6508 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S)); \ 6509 } while (0) 6510 6511 6512 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M 0x00400000 6513 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S 22 6514 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_GET(_var) \ 6515 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M) >> \ 6516 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S) 6517 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_SET(_var, _val) \ 6518 do { \ 6519 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA, _val); \ 6520 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S)); \ 6521 } while (0) 6522 6523 6524 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00800000 6525 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S 23 6526 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ 6527 (((_var) & HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ 6528 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S) 6529 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ 6530 do { \ 6531 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ 6532 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ 6533 } while (0) 6534 6535 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M 0x01000000 6536 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S 24 6537 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_GET(_var) \ 6538 (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M) >> \ 6539 HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S) 6540 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_SET(_var, _val) \ 6541 do { \ 6542 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE, _val);\ 6543 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S)); \ 6544 } while (0) 6545 6546 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M 0x1E000000 6547 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S 25 6548 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_GET(_var) \ 6549 (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M) >> \ 6550 HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S) 6551 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_SET(_var, _val) \ 6552 do { \ 6553 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE, _val);\ 6554 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S));\ 6555 } while (0) 6556 6557 6558 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M 0xffffffff 6559 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S 0 6560 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_GET(_var) \ 6561 (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M) >> \ 6562 HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S) 6563 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_SET(_var, _val) \ 6564 do { \ 6565 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK, _val); \ 6566 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S)); \ 6567 } while (0) 6568 6569 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M 0xffffffff 6570 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S 0 6571 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_GET(_var) \ 6572 (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M) >> \ 6573 HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S) 6574 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_SET(_var, _val) \ 6575 do { \ 6576 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT, _val); \ 6577 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S)); \ 6578 } while (0) 6579 6580 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M 0x0000FFFF 6581 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S 0 6582 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_GET(_var) \ 6583 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M)>> \ 6584 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S) 6585 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(_var, _val) \ 6586 do { \ 6587 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK, _val);\ 6588 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S)); \ 6589 } while (0) 6590 6591 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M 0x00070000 6592 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S 16 6593 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_GET(_var) \ 6594 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M)>> \ 6595 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S) 6596 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(_var, _val) \ 6597 do { \ 6598 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK, _val);\ 6599 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S)); \ 6600 } while (0) 6601 6602 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M 0x0001FFFF 6603 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S 0 6604 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_GET(_var) \ 6605 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M)>> \ 6606 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S) 6607 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(_var, _val) \ 6608 do { \ 6609 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK, _val);\ 6610 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S)); \ 6611 } while (0) 6612 6613 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M 0x00000001 6614 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S 0 6615 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_GET(_var) \ 6616 (((_var) & HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M)>> \ 6617 HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S) 6618 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_SET(_var, _val) \ 6619 do { \ 6620 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET, _val); \ 6621 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S)); \ 6622 } while (0) 6623 6624 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M 0x0000FFFE 6625 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S 1 6626 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_GET(_var) \ 6627 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M)>> \ 6628 HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S) 6629 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_SET(_var, _val) \ 6630 do { \ 6631 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET, _val); \ 6632 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S)); \ 6633 } while (0) 6634 6635 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M 0x000FFFFF 6636 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S 0 6637 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_GET(_var) \ 6638 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M)>> \ 6639 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S) 6640 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_SET(_var, _val) \ 6641 do { \ 6642 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2, _val);\ 6643 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S)); \ 6644 } while (0) 6645 6646 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M 0x0FF00000 6647 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S 20 6648 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_GET(_var) \ 6649 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M)>> \ 6650 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S) 6651 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_SET(_var, _val) \ 6652 do { \ 6653 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2, _val);\ 6654 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S)); \ 6655 } while (0) 6656 6657 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M 0x000FFFFF 6658 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S 0 6659 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_GET(_var) \ 6660 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M)>> \ 6661 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S) 6662 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_SET(_var, _val) \ 6663 do { \ 6664 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2, _val);\ 6665 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S)); \ 6666 } while (0) 6667 6668 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M 0x000FFFFF 6669 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S 0 6670 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_GET(_var) \ 6671 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M)>> \ 6672 HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S) 6673 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_SET(_var, _val) \ 6674 do { \ 6675 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2, _val);\ 6676 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S)); \ 6677 } while (0) 6678 6679 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M 0xFFFFFFFF 6680 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S 0 6681 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_GET(_var) \ 6682 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M)>> \ 6683 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S) 6684 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_SET(_var, _val) \ 6685 do { \ 6686 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0, _val); \ 6687 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S)); \ 6688 } while (0) 6689 6690 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M 0xFFFFFFFF 6691 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S 0 6692 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_GET(_var) \ 6693 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M)>> \ 6694 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S) 6695 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_SET(_var, _val) \ 6696 do { \ 6697 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1, _val); \ 6698 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)); \ 6699 } while (0) 6700 6701 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_M 0xffffffff 6702 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S 0 6703 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_GET(_var) \ 6704 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_M) >> \ 6705 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S) 6706 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_SET(_var, _val) \ 6707 do { \ 6708 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0, _val); \ 6709 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S)); \ 6710 } while (0) 6711 6712 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_M 0xffffffff 6713 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S 0 6714 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_GET(_var) \ 6715 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_M) >> \ 6716 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S) 6717 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_SET(_var, _val) \ 6718 do { \ 6719 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1, _val); \ 6720 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S)); \ 6721 } while (0) 6722 6723 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_M 0xffffffff 6724 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S 0 6725 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_GET(_var) \ 6726 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_M) >> \ 6727 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S) 6728 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_SET(_var, _val) \ 6729 do { \ 6730 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2, _val); \ 6731 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S)); \ 6732 } while (0) 6733 6734 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_M 0xffffffff 6735 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S 0 6736 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_GET(_var) \ 6737 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_M) >> \ 6738 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S) 6739 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_SET(_var, _val) \ 6740 do { \ 6741 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3, _val); \ 6742 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S)); \ 6743 } while (0) 6744 6745 6746 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_M 0xFFFFFFFF 6747 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S 0 6748 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_GET(_var) \ 6749 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_M)>> \ 6750 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S) 6751 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_SET(_var, _val) \ 6752 do { \ 6753 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0, _val); \ 6754 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S)); \ 6755 } while (0) 6756 6757 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_M 0xFFFFFFFF 6758 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S 0 6759 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_GET(_var) \ 6760 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_M)>> \ 6761 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S) 6762 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_SET(_var, _val) \ 6763 do { \ 6764 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1, _val); \ 6765 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S)); \ 6766 } while (0) 6767 6768 6769 /* 6770 * Subtype based MGMT frames enable bits. 6771 * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other 6772 */ 6773 /* association request */ 6774 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_M 0x00000001 6775 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_S 0 6776 6777 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_M 0x00000002 6778 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_S 1 6779 6780 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_M 0x00000004 6781 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_S 2 6782 6783 /* association response */ 6784 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_M 0x00000008 6785 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_S 3 6786 6787 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_M 0x00000010 6788 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_S 4 6789 6790 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_M 0x00000020 6791 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_S 5 6792 6793 /* Reassociation request */ 6794 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_M 0x00000040 6795 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_S 6 6796 6797 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_M 0x00000080 6798 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_S 7 6799 6800 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_M 0x00000100 6801 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_S 8 6802 6803 /* Reassociation response */ 6804 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_M 0x00000200 6805 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_S 9 6806 6807 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_M 0x00000400 6808 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_S 10 6809 6810 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_M 0x00000800 6811 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_S 11 6812 6813 /* Probe request */ 6814 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_M 0x00001000 6815 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_S 12 6816 6817 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_M 0x00002000 6818 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_S 13 6819 6820 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_M 0x00004000 6821 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_S 14 6822 6823 /* Probe response */ 6824 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_M 0x00008000 6825 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_S 15 6826 6827 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_M 0x00010000 6828 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_S 16 6829 6830 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_M 0x00020000 6831 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_S 17 6832 6833 /* Timing Advertisement */ 6834 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_M 0x00040000 6835 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_S 18 6836 6837 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_M 0x00080000 6838 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_S 19 6839 6840 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_M 0x00100000 6841 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_S 20 6842 6843 /* Reserved */ 6844 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_M 0x00200000 6845 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_S 21 6846 6847 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_M 0x00400000 6848 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_S 22 6849 6850 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_M 0x00800000 6851 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_S 23 6852 6853 /* Beacon */ 6854 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000000 6855 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_S 24 6856 6857 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000000 6858 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_S 25 6859 6860 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x04000000 6861 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_S 26 6862 6863 /* ATIM */ 6864 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x08000000 6865 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_S 27 6866 6867 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x10000000 6868 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_S 28 6869 6870 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x20000000 6871 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_S 29 6872 6873 /* Disassociation */ 6874 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_M 0x00000001 6875 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_S 0 6876 6877 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_M 0x00000002 6878 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_S 1 6879 6880 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_M 0x00000004 6881 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_S 2 6882 6883 /* Authentication */ 6884 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_M 0x00000008 6885 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_S 3 6886 6887 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_M 0x00000010 6888 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_S 4 6889 6890 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_M 0x00000020 6891 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_S 5 6892 6893 /* Deauthentication */ 6894 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_M 0x00000040 6895 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_S 6 6896 6897 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_M 0x00000080 6898 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_S 7 6899 6900 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_M 0x00000100 6901 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_S 8 6902 6903 /* Action */ 6904 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_M 0x00000200 6905 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_S 9 6906 6907 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_M 0x00000400 6908 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_S 10 6909 6910 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_M 0x00000800 6911 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_S 11 6912 6913 /* Action No Ack */ 6914 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_M 0x00001000 6915 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_S 12 6916 6917 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_M 0x00002000 6918 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_S 13 6919 6920 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_M 0x00004000 6921 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_S 14 6922 6923 /* Reserved */ 6924 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_M 0x00008000 6925 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_S 15 6926 6927 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_M 0x00010000 6928 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_S 16 6929 6930 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_M 0x00020000 6931 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_S 17 6932 6933 /* 6934 * Subtype based CTRL frames enable bits. 6935 * FP: Filter_Pass, MD: Monitor_Direct, MO: Monitor_Other 6936 */ 6937 /* Reserved */ 6938 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_M 0x00000001 6939 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_S 0 6940 6941 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_M 0x00000002 6942 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_S 1 6943 6944 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_M 0x00000004 6945 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_S 2 6946 6947 /* Reserved */ 6948 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_M 0x00000008 6949 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_S 3 6950 6951 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_M 0x00000010 6952 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_S 4 6953 6954 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_M 0x00000020 6955 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_S 5 6956 6957 /* Reserved */ 6958 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_M 0x00000040 6959 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_S 6 6960 6961 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_M 0x00000080 6962 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_S 7 6963 6964 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_M 0x00000100 6965 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_S 8 6966 6967 /* Reserved */ 6968 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_M 0x00000200 6969 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_S 9 6970 6971 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_M 0x00000400 6972 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_S 10 6973 6974 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_M 0x00000800 6975 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_S 11 6976 6977 /* Reserved */ 6978 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_M 0x00001000 6979 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_S 12 6980 6981 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_M 0x00002000 6982 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_S 13 6983 6984 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_M 0x00004000 6985 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_S 14 6986 6987 /* Reserved */ 6988 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_M 0x00008000 6989 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_S 15 6990 6991 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_M 0x00010000 6992 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_S 16 6993 6994 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_M 0x00020000 6995 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_S 17 6996 6997 /* Reserved */ 6998 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_M 0x00040000 6999 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_S 18 7000 7001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_M 0x00080000 7002 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_S 19 7003 7004 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_M 0x00100000 7005 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_S 20 7006 7007 /* Control Wrapper */ 7008 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_M 0x00200000 7009 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_S 21 7010 7011 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_M 0x00400000 7012 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_S 22 7013 7014 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_M 0x00800000 7015 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_S 23 7016 7017 /* Block Ack Request */ 7018 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_M 0x01000000 7019 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_S 24 7020 7021 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_M 0x02000000 7022 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_S 25 7023 7024 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_M 0x04000000 7025 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_S 26 7026 7027 /* Block Ack*/ 7028 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_M 0x08000000 7029 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_S 27 7030 7031 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_M 0x10000000 7032 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_S 28 7033 7034 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_M 0x20000000 7035 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_S 29 7036 7037 /* PS-POLL */ 7038 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_M 0x00000001 7039 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_S 0 7040 7041 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_M 0x00000002 7042 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_S 1 7043 7044 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_M 0x00000004 7045 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_S 2 7046 7047 /* RTS */ 7048 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_M 0x00000008 7049 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_S 3 7050 7051 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_M 0x00000010 7052 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_S 4 7053 7054 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_M 0x00000020 7055 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_S 5 7056 7057 /* CTS */ 7058 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_M 0x00000040 7059 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_S 6 7060 7061 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_M 0x00000080 7062 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_S 7 7063 7064 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_M 0x00000100 7065 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_S 8 7066 7067 /* ACK */ 7068 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_M 0x00000200 7069 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_S 9 7070 7071 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_M 0x00000400 7072 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_S 10 7073 7074 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_M 0x00000800 7075 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_S 11 7076 7077 /* CF-END */ 7078 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_M 0x00001000 7079 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_S 12 7080 7081 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_M 0x00002000 7082 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_S 13 7083 7084 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_M 0x00004000 7085 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_S 14 7086 7087 /* CF-END + CF-ACK */ 7088 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_M 0x00008000 7089 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_S 15 7090 7091 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_M 0x00010000 7092 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_S 16 7093 7094 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_M 0x00020000 7095 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_S 17 7096 7097 /* Multicast data */ 7098 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_M 0x00040000 7099 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_S 18 7100 7101 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_M 0x00080000 7102 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_S 19 7103 7104 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_M 0x00100000 7105 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_S 20 7106 7107 /* Unicast data */ 7108 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_M 0x00200000 7109 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_S 21 7110 7111 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_M 0x00400000 7112 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_S 22 7113 7114 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_M 0x00800000 7115 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_S 23 7116 7117 /* NULL data */ 7118 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_M 0x01000000 7119 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_S 24 7120 7121 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_M 0x02000000 7122 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_S 25 7123 7124 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_M 0x04000000 7125 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_S 26 7126 7127 /* FPMO mode flags */ 7128 /* MGMT */ 7129 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_M 0x00000001 7130 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_S 0 7131 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_M 0x00000002 7132 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_S 1 7133 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_M 0x00000004 7134 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_S 2 7135 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_M 0x00000008 7136 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_S 3 7137 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_M 0x00000010 7138 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_S 4 7139 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_M 0x00000020 7140 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_S 5 7141 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_M 0x00000040 7142 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_S 6 7143 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_M 0x00000080 7144 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_S 7 7145 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_M 0x00000100 7146 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_S 8 7147 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_M 0x00000200 7148 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_S 9 7149 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_M 0x00000400 7150 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_S 10 7151 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_M 0x00000800 7152 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_S 11 7153 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_M 0x00001000 7154 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_S 12 7155 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_M 0x00002000 7156 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_S 13 7157 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_M 0x00004000 7158 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_S 14 7159 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_M 0x00008000 7160 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_S 15 7161 7162 /* CTRL */ 7163 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_M 0x00010000 7164 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_S 16 7165 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_M 0x00020000 7166 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_S 17 7167 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_M 0x00040000 7168 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_S 18 7169 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_M 0x00080000 7170 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_S 19 7171 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_M 0x00100000 7172 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_S 20 7173 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_M 0x00200000 7174 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_S 21 7175 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_M 0x00400000 7176 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_S 22 7177 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_M 0x00800000 7178 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_S 23 7179 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_M 0x01000000 7180 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_S 24 7181 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_M 0x02000000 7182 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_S 25 7183 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_M 0x04000000 7184 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_S 26 7185 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_M 0x08000000 7186 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_S 27 7187 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_M 0x10000000 7188 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_S 28 7189 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_M 0x20000000 7190 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_S 29 7191 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_M 0x40000000 7192 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_S 30 7193 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_M 0x80000000 7194 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_S 31 7195 7196 /* DATA */ 7197 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_M 0x00000001 7198 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_S 0 7199 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_M 0x00000002 7200 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_S 1 7201 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_M 0x00000004 7202 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_S 2 7203 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_M 0x00000008 7204 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_S 3 7205 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_M 0x00000010 7206 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_S 4 7207 7208 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET(word, httsym, value) \ 7209 do { \ 7210 HTT_CHECK_SET_VAL(httsym, value); \ 7211 (word) |= (value) << httsym##_S; \ 7212 } while (0) 7213 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET(word, httsym) \ 7214 (((word) & httsym##_M) >> httsym##_S) 7215 7216 #define htt_rx_ring_pkt_enable_subtype_set( \ 7217 word, flag, mode, type, subtype, val) \ 7218 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET( \ 7219 word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype, val) 7220 7221 #define htt_rx_ring_pkt_enable_subtype_get( \ 7222 word, flag, mode, type, subtype) \ 7223 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET( \ 7224 word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype) 7225 7226 /* Definition to filter in TLVs */ 7227 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_M 0x00000001 7228 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_S 0 7229 7230 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_M 0x00000002 7231 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_S 1 7232 7233 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_M 0x00000004 7234 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_S 2 7235 7236 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_M 0x00000008 7237 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_S 3 7238 7239 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_M 0x00000010 7240 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_S 4 7241 7242 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_M 0x00000020 7243 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_S 5 7244 7245 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_M 0x00000040 7246 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_S 6 7247 7248 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_M 0x00000080 7249 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_S 7 7250 7251 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_M 0x00000100 7252 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_S 8 7253 7254 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_M 0x00000200 7255 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_S 9 7256 7257 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_M 0x00000400 7258 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_S 10 7259 7260 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_M 0x00000800 7261 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_S 11 7262 7263 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_M 0x00001000 7264 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_S 12 7265 7266 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_M 0x00002000 7267 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_S 13 7268 7269 #define HTT_RX_RING_TLV_ENABLE_SET(word, httsym, enable) \ 7270 do { \ 7271 HTT_CHECK_SET_VAL(httsym, enable); \ 7272 (word) |= (enable) << httsym##_S; \ 7273 } while (0) 7274 #define HTT_RX_RING_TLV_ENABLE_GET(word, httsym) \ 7275 (((word) & httsym##_M) >> httsym##_S) 7276 7277 #define htt_rx_ring_tlv_filter_in_enable_set(word, tlv, enable) \ 7278 HTT_RX_RING_TLV_ENABLE_SET( \ 7279 word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv, enable) 7280 7281 #define htt_rx_ring_tlv_filter_in_enable_get(word, tlv) \ 7282 HTT_RX_RING_TLV_ENABLE_GET( \ 7283 word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv) 7284 7285 /** 7286 * @brief host -> target TX monitor config message 7287 * 7288 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_MONITOR_CFG 7289 * 7290 * @details 7291 * HTT_H2T_MSG_TYPE_TX_MONITOR_CFG message is sent by host to 7292 * configure RXDMA rings. 7293 * The configuration is per ring based and includes both packet types 7294 * and PPDU/MPDU TLVs. 7295 * 7296 * The message would appear as follows: 7297 * 7298 * |31 28|27|26|25|24|23 22|21|20|19|18 16|15|14|13|12|11|10|9|8|7|6|5|4|3|2 0| 7299 * |-----+--+--+--+--+-----+--+--+--+-----+--+--+--+--+--+--+-+-+-+-+-+-+-+----| 7300 * |rsvd1|MF|TM|PS|SS| ring_id | pdev_id | msg_type | 7301 * |--------------+--------+--------+-----+------------------------------------| 7302 * | rsvd2 | DATA | CTRL | MGMT| ring_buffer_size | 7303 * |-----------------------------------------+--+--+--+--+--+-+-+-+-+-+-+-+----| 7304 * | | M| M| M| M| M|M|M|M|M|M|M|M| | 7305 * | | S| S| S| P| P|P|S|S|S|P|P|P| | 7306 * | | E| E| E| E| E|E|S|S|S|S|S|S| | 7307 * | rsvd3 | D| C| M| D| C|M|D|C|M|D|C|M| E | 7308 * |---------------------------------------------------------------------------| 7309 * | tlv_filter_mask_in0 | 7310 * |---------------------------------------------------------------------------| 7311 * | tlv_filter_mask_in1 | 7312 * |---------------------------------------------------------------------------| 7313 * | tlv_filter_mask_in2 | 7314 * |---------------------------------------------------------------------------| 7315 * | tlv_filter_mask_in3 | 7316 * |--------------------+-----------------+---------------------+--------------| 7317 * | tx_msdu_start_wm | tx_queue_ext_wm | tx_peer_entry_wm |tx_fes_stup_wm| 7318 * |---------------------------------------------------------------------------| 7319 * | pcu_ppdu_setup_word_mask | 7320 * |-----------------------+--+--+--+-----+---------------------+--------------| 7321 * | rsvd4 | D| C| M| PT | rxpcu_usrsetp_wm |tx_mpdu_srt_wm| 7322 * |---------------------------------------------------------------------------| 7323 * 7324 * Where: 7325 * MF = MAC address filtering enable 7326 * TM = tx monitor global enable 7327 * PS = pkt_swap 7328 * SS = status_swap 7329 * The message is interpreted as follows: 7330 * dword0 - b'0:7 - msg_type: This will be set to 7331 * 0x1b (HTT_H2T_MSG_TYPE_TX_MONITOR_CFG) 7332 * b'8:15 - pdev_id: 7333 * 0 (for rings at SOC level), 7334 * 1/2/3 mac id (for rings at LMAC level) 7335 * b'16:23 - ring_id : Identify the ring to configure. 7336 * More details can be got from enum htt_srng_ring_id 7337 * b'24 - status_swap (SS): 1 is to swap status TLV - refer to 7338 * BUF_RING_CFG_0 defs within HW .h files, 7339 * e.g. wmac_top_reg_seq_hwioreg.h 7340 * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to 7341 * BUF_RING_CFG_0 defs within HW .h files, 7342 * e.g. wmac_top_reg_seq_hwioreg.h 7343 * b'26 - tx_mon_global_en: Enable/Disable global register 7344 * configuration in Tx monitor module. 7345 * b'27 - mac_addr_filter_en: 7346 * Enable/Disable Mac Address based filter. 7347 * b'28:31 - rsvd1: reserved for future use 7348 * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, 7349 * in byte units. 7350 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 7351 * b'16:18 - config_length_mgmt(MGMT) for MGMT: Each bit set represent 7352 * 64, 128, 256. 7353 * If all 3 bits are set config length is > 256. 7354 * if val is '0', then ignore this field. 7355 * b'19:21 - config_length_ctrl(CTRL) for CTRL: Each bit set represent 7356 * 64, 128, 256. 7357 * If all 3 bits are set config length is > 256. 7358 * if val is '0', then ignore this field. 7359 * b'22:24 - config_length_data(DATA) for DATA: Each bit set represent 7360 * 64, 128, 256. 7361 * If all 3 bits are set config length is > 256. 7362 * If val is '0', then ignore this field. 7363 * - b'25:31 - rsvd2: Reserved for future use 7364 * dword2 - b'0:2 - packet_type_enable_flags(E): MGMT, CTRL, DATA 7365 * b'3 - filter_in_tx_mpdu_start_mgmt(MPSM): 7366 * If packet_type_enable_flags is '1' for MGMT type, 7367 * monitor will ignore this bit and allow this TLV. 7368 * If packet_type_enable_flags is '0' for MGMT type, 7369 * monitor will use this bit to enable/disable logging 7370 * of this TLV. 7371 * b'4 - filter_in_tx_mpdu_start_ctrl(MPSC) 7372 * If packet_type_enable_flags is '1' for CTRL type, 7373 * monitor will ignore this bit and allow this TLV. 7374 * If packet_type_enable_flags is '0' for CTRL type, 7375 * monitor will use this bit to enable/disable logging 7376 * of this TLV. 7377 * b'5 - filter_in_tx_mpdu_start_data(MPSD) 7378 * If packet_type_enable_flags is '1' for DATA type, 7379 * monitor will ignore this bit and allow this TLV. 7380 * If packet_type_enable_flags is '0' for DATA type, 7381 * monitor will use this bit to enable/disable logging 7382 * of this TLV. 7383 * b'6 - filter_in_tx_msdu_start_mgmt(MSSM) 7384 * If packet_type_enable_flags is '1' for MGMT type, 7385 * monitor will ignore this bit and allow this TLV. 7386 * If packet_type_enable_flags is '0' for MGMT type, 7387 * monitor will use this bit to enable/disable logging 7388 * of this TLV. 7389 * b'7 - filter_in_tx_msdu_start_ctrl(MSSC) 7390 * If packet_type_enable_flags is '1' for CTRL type, 7391 * monitor will ignore this bit and allow this TLV. 7392 * If packet_type_enable_flags is '0' for CTRL type, 7393 * monitor will use this bit to enable/disable logging 7394 * of this TLV. 7395 * b'8 - filter_in_tx_msdu_start_data(MSSD) 7396 * If packet_type_enable_flags is '1' for DATA type, 7397 * monitor will ignore this bit and allow this TLV. 7398 * If packet_type_enable_flags is '0' for DATA type, 7399 * monitor will use this bit to enable/disable logging 7400 * of this TLV. 7401 * b'9 - filter_in_tx_mpdu_end_mgmt(MPEM) 7402 * If packet_type_enable_flags is '1' for MGMT type, 7403 * monitor will ignore this bit and allow this TLV. 7404 * If packet_type_enable_flags is '0' for MGMT type, 7405 * monitor will use this bit to enable/disable logging 7406 * of this TLV. 7407 * If filter_in_TX_MPDU_START = 1 it is recommended 7408 * to set this bit. 7409 * b'10 - filter_in_tx_mpdu_end_ctrl(MPEC) 7410 * If packet_type_enable_flags is '1' for CTRL type, 7411 * monitor will ignore this bit and allow this TLV. 7412 * If packet_type_enable_flags is '0' for CTRL type, 7413 * monitor will use this bit to enable/disable logging 7414 * of this TLV. 7415 * If filter_in_TX_MPDU_START = 1 it is recommended 7416 * to set this bit. 7417 * b'11 - filter_in_tx_mpdu_end_data(MPED) 7418 * If packet_type_enable_flags is '1' for DATA type, 7419 * monitor will ignore this bit and allow this TLV. 7420 * If packet_type_enable_flags is '0' for DATA type, 7421 * monitor will use this bit to enable/disable logging 7422 * of this TLV. 7423 * If filter_in_TX_MPDU_START = 1 it is recommended 7424 * to set this bit. 7425 * b'12 - filter_in_tx_msdu_end_mgmt(MSEM) 7426 * If packet_type_enable_flags is '1' for MGMT type, 7427 * monitor will ignore this bit and allow this TLV. 7428 * If packet_type_enable_flags is '0' for MGMT type, 7429 * monitor will use this bit to enable/disable logging 7430 * of this TLV. 7431 * If filter_in_TX_MSDU_START = 1 it is recommended 7432 * to set this bit. 7433 * b'13 - filter_in_tx_msdu_end_ctrl(MSEC) 7434 * If packet_type_enable_flags is '1' for CTRL type, 7435 * monitor will ignore this bit and allow this TLV. 7436 * If packet_type_enable_flags is '0' for CTRL type, 7437 * monitor will use this bit to enable/disable logging 7438 * of this TLV. 7439 * If filter_in_TX_MSDU_START = 1 it is recommended 7440 * to set this bit. 7441 * b'14 - filter_in_tx_msdu_end_data(MSED) 7442 * If packet_type_enable_flags is '1' for DATA type, 7443 * monitor will ignore this bit and allow this TLV. 7444 * If packet_type_enable_flags is '0' for DATA type, 7445 * monitor will use this bit to enable/disable logging 7446 * of this TLV. 7447 * If filter_in_TX_MSDU_START = 1 it is recommended 7448 * to set this bit. 7449 * b'15:31 - rsvd3: Reserved for future use 7450 * dword3 - b'0:31 - tlv_filter_mask_in0: 7451 * dword4 - b'0:31 - tlv_filter_mask_in1: 7452 * dword5 - b'0:31 - tlv_filter_mask_in2: 7453 * dword6 - b'0:31 - tlv_filter_mask_in3: 7454 * dword7 - b'0:7 - tx_fes_setup_word_mask: 7455 * - b'8:15 - tx_peer_entry_word_mask: 7456 * - b'16:23 - tx_queue_ext_word_mask: 7457 * - b'24:31 - tx_msdu_start_word_mask: 7458 * dword8 - b'0:31 - pcu_ppdu_setup_word_mask: 7459 * dword9 - b'0:7 - tx_mpdu_start_word_mask: 7460 * - b'8:15 - rxpcu_user_setup_word_mask: 7461 * - b'16:18 - pkt_type_enable_msdu_or_mpdu_logging (PT): 7462 * MGMT, CTRL, DATA 7463 * - b'19 - dma_mpdu_mgmt(M): For MGMT 7464 * 0 -> MSDU level logging is enabled 7465 * (valid only if bit is set in 7466 * pkt_type_enable_msdu_or_mpdu_logging) 7467 * 1 -> MPDU level logging is enabled 7468 * (valid only if bit is set in 7469 * pkt_type_enable_msdu_or_mpdu_logging) 7470 * - b'20 - dma_mpdu_ctrl(C) : For CTRL 7471 * 0 -> MSDU level logging is enabled 7472 * (valid only if bit is set in 7473 * pkt_type_enable_msdu_or_mpdu_logging) 7474 * 1 -> MPDU level logging is enabled 7475 * (valid only if bit is set in 7476 * pkt_type_enable_msdu_or_mpdu_logging) 7477 * - b'21 - dma_mpdu_data(D) : For DATA 7478 * 0 -> MSDU level logging is enabled 7479 * (valid only if bit is set in 7480 * pkt_type_enable_msdu_or_mpdu_logging) 7481 * 1 -> MPDU level logging is enabled 7482 * (valid only if bit is set in 7483 * pkt_type_enable_msdu_or_mpdu_logging) 7484 * - b'22:31 - rsvd4 for future use 7485 */ 7486 PREPACK struct htt_tx_monitor_cfg_t { 7487 A_UINT32 msg_type: 8, 7488 pdev_id: 8, 7489 ring_id: 8, 7490 status_swap: 1, 7491 pkt_swap: 1, 7492 tx_mon_global_en: 1, 7493 mac_addr_filter_en: 1, 7494 rsvd1: 4; 7495 A_UINT32 ring_buffer_size: 16, 7496 config_length_mgmt: 3, 7497 config_length_ctrl: 3, 7498 config_length_data: 3, 7499 rsvd2: 7; 7500 A_UINT32 pkt_type_enable_flags: 3, 7501 filter_in_tx_mpdu_start_mgmt: 1, 7502 filter_in_tx_mpdu_start_ctrl: 1, 7503 filter_in_tx_mpdu_start_data: 1, 7504 filter_in_tx_msdu_start_mgmt: 1, 7505 filter_in_tx_msdu_start_ctrl: 1, 7506 filter_in_tx_msdu_start_data: 1, 7507 filter_in_tx_mpdu_end_mgmt: 1, 7508 filter_in_tx_mpdu_end_ctrl: 1, 7509 filter_in_tx_mpdu_end_data: 1, 7510 filter_in_tx_msdu_end_mgmt: 1, 7511 filter_in_tx_msdu_end_ctrl: 1, 7512 filter_in_tx_msdu_end_data: 1, 7513 word_mask_compaction_enable: 1, 7514 rsvd3: 16; 7515 A_UINT32 tlv_filter_mask_in0; 7516 A_UINT32 tlv_filter_mask_in1; 7517 A_UINT32 tlv_filter_mask_in2; 7518 A_UINT32 tlv_filter_mask_in3; 7519 A_UINT32 tx_fes_setup_word_mask: 8, 7520 tx_peer_entry_word_mask: 8, 7521 tx_queue_ext_word_mask: 8, 7522 tx_msdu_start_word_mask: 8; 7523 A_UINT32 pcu_ppdu_setup_word_mask; 7524 A_UINT32 tx_mpdu_start_word_mask: 8, 7525 rxpcu_user_setup_word_mask: 8, 7526 pkt_type_enable_msdu_or_mpdu_logging: 3, 7527 dma_mpdu_mgmt: 1, 7528 dma_mpdu_ctrl: 1, 7529 dma_mpdu_data: 1, 7530 rsvd4: 10; 7531 A_UINT32 tx_queue_ext_v2_word_mask: 12, 7532 tx_peer_entry_v2_word_mask: 12, 7533 rsvd5: 8; 7534 A_UINT32 fes_status_end_word_mask: 16, 7535 response_end_status_word_mask: 16; 7536 A_UINT32 fes_status_prot_word_mask: 11, 7537 rsvd6: 21; 7538 } POSTPACK; 7539 7540 #define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t)) 7541 7542 #define HTT_TX_MONITOR_CFG_PDEV_ID_M 0x0000ff00 7543 #define HTT_TX_MONITOR_CFG_PDEV_ID_S 8 7544 #define HTT_TX_MONITOR_CFG_PDEV_ID_GET(_var) \ 7545 (((_var) & HTT_TX_MONITOR_CFG_PDEV_ID_M) >> \ 7546 HTT_TX_MONITOR_CFG_PDEV_ID_S) 7547 #define HTT_TX_MONITOR_CFG_PDEV_ID_SET(_var, _val) \ 7548 do { \ 7549 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDEV_ID, _val); \ 7550 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDEV_ID_S)); \ 7551 } while (0) 7552 7553 #define HTT_TX_MONITOR_CFG_RING_ID_M 0x00ff0000 7554 #define HTT_TX_MONITOR_CFG_RING_ID_S 16 7555 #define HTT_TX_MONITOR_CFG_RING_ID_GET(_var) \ 7556 (((_var) & HTT_TX_MONITOR_CFG_RING_ID_M) >> \ 7557 HTT_TX_MONITOR_CFG_RING_ID_S) 7558 #define HTT_TX_MONITOR_CFG_RING_ID_SET(_var, _val) \ 7559 do { \ 7560 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_ID, _val); \ 7561 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_ID_S)); \ 7562 } while (0) 7563 7564 #define HTT_TX_MONITOR_CFG_STATUS_SWAP_M 0x01000000 7565 #define HTT_TX_MONITOR_CFG_STATUS_SWAP_S 24 7566 #define HTT_TX_MONITOR_CFG_STATUS_TLV_GET(_var) \ 7567 (((_var) & HTT_TX_MONITOR_CFG_STATUS_SWAP_M) >> \ 7568 HTT_TX_MONITOR_CFG_STATUS_SWAP_S) 7569 #define HTT_TX_MONITOR_CFG_STATUS_TLV_SET(_var, _val) \ 7570 do { \ 7571 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_STATUS_SWAP, _val); \ 7572 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_STATUS_SWAP_S)); \ 7573 } while (0) 7574 7575 #define HTT_TX_MONITOR_CFG_PKT_SWAP_M 0x02000000 7576 #define HTT_TX_MONITOR_CFG_PKT_SWAP_S 25 7577 #define HTT_TX_MONITOR_CFG_PKT_TLV_GET(_var) \ 7578 (((_var) & HTT_TX_MONITOR_CFG_PKT_SWAP_M) >> \ 7579 HTT_TX_MONITOR_CFG_PKT_SWAP_S) 7580 #define HTT_TX_MONITOR_CFG_PKT_TLV_SET(_var, _val) \ 7581 do { \ 7582 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_SWAP, _val); \ 7583 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_SWAP_S)); \ 7584 } while (0) 7585 7586 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M 0x04000000 7587 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S 26 7588 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_GET(_var) \ 7589 (((_var) & HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M) >> \ 7590 HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S) 7591 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_SET(_var, _val) \ 7592 do { \ 7593 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN, _val); \ 7594 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S)); \ 7595 } while (0) 7596 7597 #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_M 0x08000000 7598 #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S 27 7599 #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_GET(_var) \ 7600 (((_var) & HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_M) >> \ 7601 HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S) 7602 #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_SET(_var, _val) \ 7603 do { \ 7604 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN, _val); \ 7605 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S)); \ 7606 } while (0) 7607 7608 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff 7609 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0 7610 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \ 7611 (((_var) & HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M) >> \ 7612 HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S) 7613 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_SET(_var, _val) \ 7614 do { \ 7615 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE, _val); \ 7616 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S)); \ 7617 } while (0) 7618 7619 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M 0x00070000 7620 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S 16 7621 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_GET(_var) \ 7622 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M) >> \ 7623 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S) 7624 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \ 7625 do { \ 7626 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT, _val); \ 7627 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)); \ 7628 } while (0) 7629 7630 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M 0x00380000 7631 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S 19 7632 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_GET(_var) \ 7633 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M) >> \ 7634 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S) 7635 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \ 7636 do { \ 7637 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL, _val); \ 7638 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S)); \ 7639 } while (0) 7640 7641 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M 0x01C00000 7642 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S 22 7643 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_GET(_var) \ 7644 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M) >> \ 7645 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S) 7646 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \ 7647 do { \ 7648 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA, _val); \ 7649 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S)); \ 7650 } while (0) 7651 7652 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M 0x00000007 7653 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S 0 7654 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_GET(_var) \ 7655 (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M) >> \ 7656 HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S) 7657 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_SET(_var, _val) \ 7658 do { \ 7659 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS, _val); \ 7660 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S)); \ 7661 } while (0) 7662 7663 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M 0x00000008 7664 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S 3 7665 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_GET(_var) \ 7666 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M) >> \ 7667 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S) 7668 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_SET(_var, _val) \ 7669 do { \ 7670 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT, _val); \ 7671 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S)); \ 7672 } while (0) 7673 7674 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M 0x00000010 7675 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S 4 7676 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_GET(_var) \ 7677 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M) >> \ 7678 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S) 7679 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_SET(_var, _val) \ 7680 do { \ 7681 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL, _val); \ 7682 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S)); \ 7683 } while (0) 7684 7685 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M 0x00000020 7686 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S 5 7687 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_GET(_var) \ 7688 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M) >> \ 7689 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S) 7690 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_SET(_var, _val) \ 7691 do { \ 7692 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA, _val); \ 7693 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S)); \ 7694 } while (0) 7695 7696 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M 0x00000040 7697 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S 6 7698 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_GET(_var) \ 7699 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M) >> \ 7700 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S) 7701 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_SET(_var, _val) \ 7702 do { \ 7703 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT, _val); \ 7704 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S)); \ 7705 } while (0) 7706 7707 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M 0x00000080 7708 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S 7 7709 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_GET(_var) \ 7710 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M) >> \ 7711 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S) 7712 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_SET(_var, _val) \ 7713 do { \ 7714 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL, _val); \ 7715 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S)); \ 7716 } while (0) 7717 7718 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M 0x00000100 7719 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S 8 7720 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_GET(_var) \ 7721 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M) >> \ 7722 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S) 7723 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_SET(_var, _val) \ 7724 do { \ 7725 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA, _val); \ 7726 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S)); \ 7727 } while (0) 7728 7729 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M 0x00000200 7730 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S 9 7731 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_GET(_var) \ 7732 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M) >> \ 7733 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S) 7734 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_SET(_var, _val) \ 7735 do { \ 7736 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT, _val); \ 7737 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S)); \ 7738 } while (0) 7739 7740 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M 0x00000400 7741 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S 10 7742 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_GET(_var) \ 7743 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M) >> \ 7744 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S) 7745 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_SET(_var, _val) \ 7746 do { \ 7747 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL, _val); \ 7748 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S)); \ 7749 } while (0) 7750 7751 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M 0x00000800 7752 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S 11 7753 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_GET(_var) \ 7754 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M) >> \ 7755 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S) 7756 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_SET(_var, _val) \ 7757 do { \ 7758 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA, _val); \ 7759 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S)); \ 7760 } while (0) 7761 7762 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M 0x00001000 7763 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S 12 7764 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_GET(_var) \ 7765 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M) >> \ 7766 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S) 7767 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_SET(_var, _val) \ 7768 do { \ 7769 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT, _val); \ 7770 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S)); \ 7771 } while (0) 7772 7773 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M 0x00002000 7774 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S 13 7775 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_GET(_var) \ 7776 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M) >> \ 7777 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S) 7778 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_SET(_var, _val) \ 7779 do { \ 7780 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL, _val); \ 7781 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S)); \ 7782 } while (0) 7783 7784 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M 0x00004000 7785 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S 14 7786 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_GET(_var) \ 7787 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M) >> \ 7788 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S) 7789 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_SET(_var, _val) \ 7790 do { \ 7791 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA, _val); \ 7792 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S)); \ 7793 } while (0) 7794 7795 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00008000 7796 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S 15 7797 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ 7798 (((_var) & HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ 7799 HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S) 7800 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ 7801 do { \ 7802 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ 7803 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ 7804 } while (0) 7805 7806 7807 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M 0xffffffff 7808 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S 0 7809 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_GET(_var) \ 7810 (((_var) & HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M) >> \ 7811 HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S) 7812 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_SET(_var, _val) \ 7813 do { \ 7814 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TLV_FILTER_MASK, _val); \ 7815 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S)); \ 7816 } while (0) 7817 7818 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M 0x000000ff 7819 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S 0 7820 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_GET(_var) \ 7821 (((_var) & HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M) >> \ 7822 HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S) 7823 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_SET(_var, _val) \ 7824 do { \ 7825 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK, _val); \ 7826 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S)); \ 7827 } while (0) 7828 7829 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M 0x0000ff00 7830 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S 8 7831 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_GET(_var) \ 7832 (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M) >> \ 7833 HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S) 7834 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_SET(_var, _val) \ 7835 do { \ 7836 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK, _val); \ 7837 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S)); \ 7838 } while (0) 7839 7840 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M 0x00ff0000 7841 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S 16 7842 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_GET(_var) \ 7843 (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M) >> \ 7844 HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S) 7845 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_SET(_var, _val) \ 7846 do { \ 7847 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK, _val); \ 7848 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S)); \ 7849 } while (0) 7850 7851 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M 0xff000000 7852 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S 24 7853 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_GET(_var) \ 7854 (((_var) & HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M) >> \ 7855 HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S) 7856 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_SET(_var, _val) \ 7857 do { \ 7858 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK, _val); \ 7859 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S)); \ 7860 } while (0) 7861 7862 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M 0xffffffff 7863 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S 0 7864 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_GET(_var) \ 7865 (((_var) & HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M) >> \ 7866 HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S) 7867 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_SET(_var, _val) \ 7868 do { \ 7869 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK, _val); \ 7870 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S)); \ 7871 } while (0) 7872 7873 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M 0x000000ff 7874 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S 0 7875 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_GET(_var) \ 7876 (((_var) & HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M) >> \ 7877 HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S) 7878 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_SET(_var, _val) \ 7879 do { \ 7880 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK, _val); \ 7881 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S)); \ 7882 } while (0) 7883 7884 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M 0x0000ff00 7885 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S 8 7886 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_GET(_var) \ 7887 (((_var) & HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M) >> \ 7888 HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S) 7889 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_SET(_var, _val) \ 7890 do { \ 7891 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK, _val); \ 7892 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S)); \ 7893 } while (0) 7894 7895 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M 0x00070000 7896 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S 16 7897 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_GET(_var) \ 7898 (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M) >> \ 7899 HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S) 7900 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_SET(_var, _val) \ 7901 do { \ 7902 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK, _val); \ 7903 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S)); \ 7904 } while (0) 7905 7906 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M 0x00080000 7907 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S 19 7908 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_GET(_var) \ 7909 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M) >> \ 7910 HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S) 7911 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_SET(_var, _val) \ 7912 do { \ 7913 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT, _val); \ 7914 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S)); \ 7915 } while (0) 7916 7917 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M 0x00100000 7918 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S 20 7919 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_GET(_var) \ 7920 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M) >> \ 7921 HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S) 7922 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_SET(_var, _val) \ 7923 do { \ 7924 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL, _val); \ 7925 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S)); \ 7926 } while (0) 7927 7928 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M 0x00200000 7929 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S 21 7930 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_GET(_var) \ 7931 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M) >> \ 7932 HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S) 7933 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_SET(_var, _val) \ 7934 do { \ 7935 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_DATA, _val); \ 7936 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S)); \ 7937 } while (0) 7938 7939 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M 0x00000fff 7940 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S 0 7941 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_GET(_var) \ 7942 (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M) >> \ 7943 HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S) 7944 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_SET(_var, _val) \ 7945 do { \ 7946 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK, _val); \ 7947 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)); \ 7948 } while (0) 7949 7950 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M 0x00fff000 7951 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S 12 7952 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_GET(_var) \ 7953 (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M) >> \ 7954 HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S) 7955 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_SET(_var, _val) \ 7956 do { \ 7957 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK, _val); \ 7958 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)); \ 7959 } while (0) 7960 7961 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M 0x0000ffff 7962 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S 0 7963 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_GET(_var) \ 7964 (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M) >> \ 7965 HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S) 7966 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_SET(_var, _val) \ 7967 do { \ 7968 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK, _val); \ 7969 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)); \ 7970 } while (0) 7971 7972 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M 0xffff0000 7973 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S 16 7974 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_GET(_var) \ 7975 (((_var) & HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M) >> \ 7976 HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S) 7977 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_SET(_var, _val) \ 7978 do { \ 7979 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK, _val); \ 7980 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)); \ 7981 } while (0) 7982 7983 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M 0x000007ff 7984 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S 0 7985 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_GET(_var) \ 7986 (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M) >> \ 7987 HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S) 7988 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_SET(_var, _val) \ 7989 do { \ 7990 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK, _val); \ 7991 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \ 7992 } while (0) 7993 7994 /* 7995 * pkt_type_enable_flags 7996 */ 7997 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_M 0x00000001 7998 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_S 0 7999 8000 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_M 0x00000002 8001 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_S 1 8002 8003 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_M 0x00000004 8004 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_S 2 8005 8006 /* 8007 * PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING 8008 */ 8009 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_M 0x00010000 8010 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_S 16 8011 8012 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_M 0x00020000 8013 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_S 17 8014 8015 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_M 0x00040000 8016 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_S 18 8017 8018 #define HTT_TX_MONITOR_CFG_PKT_TYPE_SET(word, httsym, value) \ 8019 do { \ 8020 HTT_CHECK_SET_VAL(httsym, value); \ 8021 (word) |= (value) << httsym##_S; \ 8022 } while (0) 8023 #define HTT_TX_MONITOR_CFG_PKT_TYPE_GET(word, httsym) \ 8024 (((word) & httsym##_M) >> httsym##_S) 8025 8026 /* mode -> ENABLE_FLAGS, ENABLE_MSDU_OR_MPDU_LOGGING 8027 * type -> MGMT, CTRL, DATA*/ 8028 8029 #define htt_tx_ring_pkt_type_set( \ 8030 word, mode, type, val) \ 8031 HTT_TX_MONITOR_CFG_PKT_TYPE_SET( \ 8032 word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type, val) 8033 8034 #define htt_tx_ring_pkt_type_get( \ 8035 word, mode, type) \ 8036 HTT_TX_MONITOR_CFG_PKT_TYPE_GET( \ 8037 word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type) 8038 8039 /* Definition to filter in TLVs */ 8040 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_M 0x00000001 8041 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_S 0 8042 8043 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_M 0x00000002 8044 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_S 1 8045 8046 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_M 0x00000004 8047 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_S 2 8048 8049 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_M 0x00000008 8050 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_S 3 8051 8052 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_M 0x00000010 8053 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_S 4 8054 8055 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_M 0x00000020 8056 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_S 5 8057 8058 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_M 0x00000040 8059 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_S 6 8060 8061 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_M 0x00000080 8062 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_S 7 8063 8064 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_M 0x00000100 8065 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_S 8 8066 8067 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_M 0x00000200 8068 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_S 9 8069 8070 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_M 0x00000400 8071 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_S 10 8072 8073 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_M 0x00000800 8074 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_S 11 8075 8076 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_M 0x00001000 8077 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_S 12 8078 8079 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_M 0x00002000 8080 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_S 13 8081 8082 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_M 0x00004000 8083 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_S 14 8084 8085 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_M 0x00008000 8086 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_S 15 8087 8088 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_M 0x00010000 8089 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_S 16 8090 8091 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_M 0x00020000 8092 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_S 17 8093 8094 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_M 0x00040000 8095 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_S 18 8096 8097 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_M 0x00080000 8098 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_S 19 8099 8100 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_M 0x00100000 8101 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_S 20 8102 8103 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_M 0x00200000 8104 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_S 21 8105 8106 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_M 0x00400000 8107 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_S 22 8108 8109 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_M 0x00800000 8110 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_S 23 8111 8112 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_M 0x01000000 8113 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_S 24 8114 8115 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_M 0x02000000 8116 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_S 25 8117 8118 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_M 0x04000000 8119 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_S 26 8120 8121 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_M 0x08000000 8122 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_S 27 8123 8124 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_M 0x10000000 8125 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_S 28 8126 8127 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_M 0x20000000 8128 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_S 29 8129 8130 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_M 0x40000000 8131 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_S 30 8132 8133 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_M 0x80000000 8134 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_S 31 8135 8136 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET(word, httsym, enable) \ 8137 do { \ 8138 HTT_CHECK_SET_VAL(httsym, enable); \ 8139 (word) |= (enable) << httsym##_S; \ 8140 } while (0) 8141 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET(word, httsym) \ 8142 (((word) & httsym##_M) >> httsym##_S) 8143 8144 #define htt_tx_monitor_tlv_filter_in0_enable_set(word, tlv, enable) \ 8145 HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET( \ 8146 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv, enable) 8147 8148 #define htt_tx_monitor_tlv_filter_in0_enable_get(word, tlv) \ 8149 HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET( \ 8150 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv) 8151 8152 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_M 0x00000001 8153 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_S 0 8154 8155 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_M 0x00000002 8156 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_S 1 8157 8158 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_M 0x00000004 8159 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_S 2 8160 8161 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_M 0x00000008 8162 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_S 3 8163 8164 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_M 0x00000010 8165 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_S 4 8166 8167 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_M 0x00000020 8168 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_S 5 8169 8170 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_M 0x00000040 8171 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_S 6 8172 8173 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_M 0x00000080 8174 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_S 7 8175 8176 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_M 0x00000100 8177 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_S 8 8178 8179 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_M 0x00000200 8180 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_S 9 8181 8182 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_M 0x00000400 8183 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_S 10 8184 8185 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_M 0x00000800 8186 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_S 11 8187 8188 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_M 0x00001000 8189 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_S 12 8190 8191 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_M 0x00002000 8192 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_S 13 8193 8194 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_M 0x00004000 8195 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_S 14 8196 8197 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_M 0x00008000 8198 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_S 15 8199 8200 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_M 0x00010000 8201 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_S 16 8202 8203 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_M 0x00020000 8204 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_S 17 8205 8206 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_M 0x00040000 8207 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_S 18 8208 8209 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_M 0x00080000 8210 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_S 19 8211 8212 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_M 0x00100000 8213 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_S 20 8214 8215 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_M 0x00200000 8216 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_S 21 8217 8218 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_M 0x00400000 8219 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_S 22 8220 8221 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_M 0x00800000 8222 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_S 23 8223 8224 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_M 0x01000000 8225 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_S 24 8226 8227 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_M 0x02000000 8228 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_S 25 8229 8230 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_M 0x04000000 8231 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_S 26 8232 8233 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_M 0x08000000 8234 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_S 27 8235 8236 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_M 0x10000000 8237 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_S 28 8238 8239 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_M 0x20000000 8240 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_S 29 8241 8242 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_M 0x40000000 8243 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_S 30 8244 8245 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_M 0x80000000 8246 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_S 31 8247 8248 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET(word, httsym, enable) \ 8249 do { \ 8250 HTT_CHECK_SET_VAL(httsym, enable); \ 8251 (word) |= (enable) << httsym##_S; \ 8252 } while (0) 8253 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET(word, httsym) \ 8254 (((word) & httsym##_M) >> httsym##_S) 8255 8256 #define htt_tx_monitor_tlv_filter_in1_enable_set(word, tlv, enable) \ 8257 HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET( \ 8258 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv, enable) 8259 8260 #define htt_tx_monitor_tlv_filter_in1_enable_get(word, tlv) \ 8261 HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET( \ 8262 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv) 8263 8264 8265 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_M 0x00000001 8266 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_S 0 8267 8268 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_M 0x00000002 8269 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_S 1 8270 8271 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_M 0x00000004 8272 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_S 2 8273 8274 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_M 0x00000008 8275 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_S 3 8276 8277 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_M 0x00000010 8278 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_S 4 8279 8280 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_M 0x00000020 8281 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_S 5 8282 8283 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_M 0x00000040 8284 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_S 6 8285 8286 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_M 0x00000080 8287 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_S 7 8288 8289 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_M 0x00000100 8290 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_S 8 8291 8292 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_M 0x00000200 8293 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_S 9 8294 8295 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_M 0x00000400 8296 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_S 10 8297 8298 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_M 0x00000800 8299 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_S 11 8300 8301 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_M 0x00001000 8302 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_S 12 8303 8304 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_M 0x00002000 8305 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_S 13 8306 8307 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_M 0x00004000 8308 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_S 14 8309 8310 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_M 0x00008000 8311 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_S 15 8312 8313 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_M 0x00010000 8314 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_S 16 8315 8316 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_M 0x00020000 8317 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_S 17 8318 8319 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_M 0x00040000 8320 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_S 18 8321 8322 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_M 0x00080000 8323 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_S 19 8324 8325 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_M 0x00100000 8326 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_S 20 8327 8328 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_M 0x00200000 8329 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_S 21 8330 8331 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_M 0x00400000 8332 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_S 22 8333 8334 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_M 0x00800000 8335 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_S 23 8336 8337 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_M 0x01000000 8338 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_S 24 8339 8340 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_M 0x02000000 8341 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_S 25 8342 8343 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_M 0x04000000 8344 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_S 26 8345 8346 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_M 0x08000000 8347 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_S 27 8348 8349 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_M 0x10000000 8350 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_S 28 8351 8352 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_M 0x20000000 8353 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_S 29 8354 8355 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_M 0x40000000 8356 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_S 30 8357 8358 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_M 0x80000000 8359 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_S 31 8360 8361 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET(word, httsym, enable) \ 8362 do { \ 8363 HTT_CHECK_SET_VAL(httsym, enable); \ 8364 (word) |= (enable) << httsym##_S; \ 8365 } while (0) 8366 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET(word, httsym) \ 8367 (((word) & httsym##_M) >> httsym##_S) 8368 8369 #define htt_tx_monitor_tlv_filter_in2_enable_set(word, tlv, enable) \ 8370 HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET( \ 8371 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv, enable) 8372 8373 #define htt_tx_monitor_tlv_filter_in2_enable_get(word, tlv) \ 8374 HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET( \ 8375 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv) 8376 8377 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_M 0x00000001 8378 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_S 0 8379 8380 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_M 0x00000002 8381 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_S 1 8382 8383 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_M 0x00000004 8384 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_S 2 8385 8386 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_M 0x00000008 8387 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_S 3 8388 8389 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_M 0x00000010 8390 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_S 4 8391 8392 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_M 0x00000020 8393 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_S 5 8394 8395 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_M 0x00000040 8396 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_S 6 8397 8398 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_M 0x00000080 8399 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_S 7 8400 8401 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_M 0x00000100 8402 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_S 8 8403 8404 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_M 0x00000200 8405 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_S 9 8406 8407 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_M 0x00000400 8408 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_S 10 8409 8410 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_M 0x00000800 8411 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_S 11 8412 8413 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_M 0x00001000 8414 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_S 12 8415 8416 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_M 0x00002000 8417 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_S 13 8418 8419 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_M 0x00004000 8420 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_S 14 8421 8422 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_M 0x00008000 8423 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_S 15 8424 8425 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_M 0x00010000 8426 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_S 16 8427 8428 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_M 0x00020000 8429 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_S 17 8430 8431 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_M 0x00040000 8432 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_S 18 8433 8434 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_M 0x00080000 8435 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_S 19 8436 8437 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_M 0x00100000 8438 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_S 20 8439 8440 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_M 0x00200000 8441 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_S 21 8442 8443 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET(word, httsym, enable) \ 8444 do { \ 8445 HTT_CHECK_SET_VAL(httsym, enable); \ 8446 (word) |= (enable) << httsym##_S; \ 8447 } while (0) 8448 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET(word, httsym) \ 8449 (((word) & httsym##_M) >> httsym##_S) 8450 8451 #define htt_tx_monitor_tlv_filter_in3_enable_set(word, tlv, enable) \ 8452 HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET( \ 8453 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv, enable) 8454 8455 #define htt_tx_monitor_tlv_filter_in3_enable_get(word, tlv) \ 8456 HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET( \ 8457 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv) 8458 8459 /** 8460 * @brief host --> target Receive Flow Steering configuration message definition 8461 * 8462 * MSG_TYPE => HTT_H2T_MSG_TYPE_RFS_CONFIG 8463 * 8464 * host --> target Receive Flow Steering configuration message definition. 8465 * Host must send this message before sending HTT_H2T_MSG_TYPE_RX_RING_CFG. 8466 * The reason for this is we want RFS to be configured and ready before MAC 8467 * remote ring is enabled via HTT_H2T_MSG_TYPE_RX_RING_CFG. 8468 * 8469 * |31 24|23 16|15 9|8|7 0| 8470 * |----------------+----------------+----------------+----------------| 8471 * | reserved |E| msg type | 8472 * |-------------------------------------------------------------------| 8473 * Where E = RFS enable flag 8474 * 8475 * The RFS_CONFIG message consists of a single 4-byte word. 8476 * 8477 * Header fields: 8478 * - MSG_TYPE 8479 * Bits 7:0 8480 * Purpose: identifies this as a RFS config msg 8481 * Value: 0xf (HTT_H2T_MSG_TYPE_RFS_CONFIG) 8482 * - RFS_CONFIG 8483 * Bit 8 8484 * Purpose: Tells target whether to enable (1) or disable (0) 8485 * flow steering feature when sending rx indication messages to host 8486 */ 8487 #define HTT_H2T_RFS_CONFIG_M 0x100 8488 #define HTT_H2T_RFS_CONFIG_S 8 8489 #define HTT_RX_RFS_CONFIG_GET(_var) \ 8490 (((_var) & HTT_H2T_RFS_CONFIG_M) >> \ 8491 HTT_H2T_RFS_CONFIG_S) 8492 #define HTT_RX_RFS_CONFIG_SET(_var, _val) \ 8493 do { \ 8494 HTT_CHECK_SET_VAL(HTT_H2T_RFS_CONFIG, _val); \ 8495 ((_var) |= ((_val) << HTT_H2T_RFS_CONFIG_S)); \ 8496 } while (0) 8497 8498 #define HTT_RFS_CFG_REQ_BYTES 4 8499 8500 8501 /** 8502 * @brief host -> target FW extended statistics request 8503 * 8504 * MSG_TYPE => HTT_H2T_MSG_TYPE_EXT_STATS_REQ 8505 * 8506 * @details 8507 * The following field definitions describe the format of the HTT host 8508 * to target FW extended stats retrieve message. 8509 * The message specifies the type of stats the host wants to retrieve. 8510 * 8511 * |31 24|23 16|15 8|7 0| 8512 * |-----------------------------------------------------------| 8513 * | reserved | stats type | pdev_mask | msg type | 8514 * |-----------------------------------------------------------| 8515 * | config param [0] | 8516 * |-----------------------------------------------------------| 8517 * | config param [1] | 8518 * |-----------------------------------------------------------| 8519 * | config param [2] | 8520 * |-----------------------------------------------------------| 8521 * | config param [3] | 8522 * |-----------------------------------------------------------| 8523 * | reserved | 8524 * |-----------------------------------------------------------| 8525 * | cookie LSBs | 8526 * |-----------------------------------------------------------| 8527 * | cookie MSBs | 8528 * |-----------------------------------------------------------| 8529 * Header fields: 8530 * - MSG_TYPE 8531 * Bits 7:0 8532 * Purpose: identifies this is a extended stats upload request message 8533 * Value: 0x10 (HTT_H2T_MSG_TYPE_EXT_STATS_REQ) 8534 * - PDEV_MASK 8535 * Bits 8:15 8536 * Purpose: identifies the mask of PDEVs to retrieve stats from 8537 * Value: This is a overloaded field, refer to usage and interpretation of 8538 * PDEV in interface document. 8539 * Bit 8 : Reserved for SOC stats 8540 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 8541 * Indicates MACID_MASK in DBS 8542 * - STATS_TYPE 8543 * Bits 23:16 8544 * Purpose: identifies which FW statistics to upload 8545 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 8546 * - Reserved 8547 * Bits 31:24 8548 * - CONFIG_PARAM [0] 8549 * Bits 31:0 8550 * Purpose: give an opaque configuration value to the specified stats type 8551 * Value: stats-type specific configuration value 8552 * Refer to htt_stats.h for interpretation for each stats sub_type 8553 * - CONFIG_PARAM [1] 8554 * Bits 31:0 8555 * Purpose: give an opaque configuration value to the specified stats type 8556 * Value: stats-type specific configuration value 8557 * Refer to htt_stats.h for interpretation for each stats sub_type 8558 * - CONFIG_PARAM [2] 8559 * Bits 31:0 8560 * Purpose: give an opaque configuration value to the specified stats type 8561 * Value: stats-type specific configuration value 8562 * Refer to htt_stats.h for interpretation for each stats sub_type 8563 * - CONFIG_PARAM [3] 8564 * Bits 31:0 8565 * Purpose: give an opaque configuration value to the specified stats type 8566 * Value: stats-type specific configuration value 8567 * Refer to htt_stats.h for interpretation for each stats sub_type 8568 * - Reserved [31:0] for future use. 8569 * - COOKIE_LSBS 8570 * Bits 31:0 8571 * Purpose: Provide a mechanism to match a target->host stats confirmation 8572 * message with its preceding host->target stats request message. 8573 * Value: LSBs of the opaque cookie specified by the host-side requestor 8574 * - COOKIE_MSBS 8575 * Bits 31:0 8576 * Purpose: Provide a mechanism to match a target->host stats confirmation 8577 * message with its preceding host->target stats request message. 8578 * Value: MSBs of the opaque cookie specified by the host-side requestor 8579 */ 8580 8581 #define HTT_H2T_EXT_STATS_REQ_MSG_SZ 32 /* bytes */ 8582 8583 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M 0x0000ff00 8584 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S 8 8585 8586 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M 0x00ff0000 8587 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S 16 8588 8589 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M 0xffffffff 8590 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S 0 8591 8592 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_GET(_var) \ 8593 (((_var) & HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M) >> \ 8594 HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S) 8595 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_SET(_var, _val) \ 8596 do { \ 8597 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_PDEV_MASK, _val); \ 8598 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S)); \ 8599 } while (0) 8600 8601 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_GET(_var) \ 8602 (((_var) & HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M) >> \ 8603 HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S) 8604 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_SET(_var, _val) \ 8605 do { \ 8606 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_STATS_TYPE, _val); \ 8607 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S)); \ 8608 } while (0) 8609 8610 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_GET(_var) \ 8611 (((_var) & HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M) >> \ 8612 HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S) 8613 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_SET(_var, _val) \ 8614 do { \ 8615 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM, _val); \ 8616 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S)); \ 8617 } while (0) 8618 8619 /** 8620 * @brief host -> target FW streaming statistics request 8621 * 8622 * MSG_TYPE => HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ 8623 * 8624 * @details 8625 * The following field definitions describe the format of the HTT host 8626 * to target message that requests the target to start or stop producing 8627 * ongoing stats of the specified type. 8628 * 8629 * |31|30 |23 16|15 8|7 0| 8630 * |-----------------------------------------------------------| 8631 * |EN| reserved | stats type | reserved | msg type | 8632 * |-----------------------------------------------------------| 8633 * | config param [0] | 8634 * |-----------------------------------------------------------| 8635 * | config param [1] | 8636 * |-----------------------------------------------------------| 8637 * | config param [2] | 8638 * |-----------------------------------------------------------| 8639 * | config param [3] | 8640 * |-----------------------------------------------------------| 8641 * Where: 8642 * - EN is an enable/disable flag 8643 * Header fields: 8644 * - MSG_TYPE 8645 * Bits 7:0 8646 * Purpose: identifies this is a streaming stats upload request message 8647 * Value: 0x20 (HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ) 8648 * - STATS_TYPE 8649 * Bits 23:16 8650 * Purpose: identifies which FW statistics to upload 8651 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 8652 * Only the htt_dbg_ext_stats_type values identified as streaming 8653 * stats are valid to specify in this STEAMING_STATS_REQ message. 8654 * - ENABLE 8655 * Bit 31 8656 * Purpose: enable/disable the target's ongoing stats of the specified type 8657 * Value: 8658 * 0 - disable ongoing production of the specified stats type 8659 * 1 - enable ongoing production of the specified stats type 8660 * - CONFIG_PARAM [0] 8661 * Bits 31:0 8662 * Purpose: give an opaque configuration value to the specified stats type 8663 * Value: stats-type specific configuration value 8664 * Refer to htt_stats.h for interpretation for each stats sub_type 8665 * - CONFIG_PARAM [1] 8666 * Bits 31:0 8667 * Purpose: give an opaque configuration value to the specified stats type 8668 * Value: stats-type specific configuration value 8669 * Refer to htt_stats.h for interpretation for each stats sub_type 8670 * - CONFIG_PARAM [2] 8671 * Bits 31:0 8672 * Purpose: give an opaque configuration value to the specified stats type 8673 * Value: stats-type specific configuration value 8674 * Refer to htt_stats.h for interpretation for each stats sub_type 8675 * - CONFIG_PARAM [3] 8676 * Bits 31:0 8677 * Purpose: give an opaque configuration value to the specified stats type 8678 * Value: stats-type specific configuration value 8679 * Refer to htt_stats.h for interpretation for each stats sub_type 8680 */ 8681 8682 #define HTT_H2T_STREAMING_STATS_REQ_MSG_SZ 20 /* bytes */ 8683 8684 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M 0x00ff0000 8685 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S 16 8686 8687 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_M 0x80000000 8688 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_S 31 8689 8690 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_GET(_var) \ 8691 (((_var) & HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M) >> \ 8692 HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S) 8693 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_SET(_var, _val) \ 8694 do { \ 8695 HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE, _val); \ 8696 ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S)); \ 8697 } while (0) 8698 8699 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_GET(_var) \ 8700 (((_var) & HTT_H2T_STREAMING_STATS_REQ_ENABLE_M) >> \ 8701 HTT_H2T_STREAMING_STATS_REQ_ENABLE_S) 8702 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_SET(_var, _val) \ 8703 do { \ 8704 HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_ENABLE, _val); \ 8705 ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_ENABLE_S)); \ 8706 } while (0) 8707 8708 /** 8709 * @brief host -> target FW PPDU_STATS request message 8710 * 8711 * MSG_TYPE => HTT_H2T_MSG_TYPE_PPDU_STATS_CFG 8712 * 8713 * @details 8714 * The following field definitions describe the format of the HTT host 8715 * to target FW for PPDU_STATS_CFG msg. 8716 * The message allows the host to configure the PPDU_STATS_IND messages 8717 * produced by the target. 8718 * 8719 * |31 24|23 16|15 8|7 0| 8720 * |-----------------------------------------------------------| 8721 * | REQ bit mask | pdev_mask | msg type | 8722 * |-----------------------------------------------------------| 8723 * Header fields: 8724 * - MSG_TYPE 8725 * Bits 7:0 8726 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 8727 * Value: 0x11 (HTT_H2T_MSG_TYPE_PPDU_STATS_CFG) 8728 * - PDEV_MASK 8729 * Bits 8:15 8730 * Purpose: identifies which pdevs this PPDU stats configuration applies to 8731 * Value: This is a overloaded field, refer to usage and interpretation of 8732 * PDEV in interface document. 8733 * Bit 8 : Reserved for SOC stats 8734 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 8735 * Indicates MACID_MASK in DBS 8736 * - REQ_TLV_BIT_MASK 8737 * Bits 16:31 8738 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 8739 * needs to be included in the target's PPDU_STATS_IND messages. 8740 * Value: refer htt_ppdu_stats_tlv_tag_t 8741 * 8742 */ 8743 #define HTT_H2T_PPDU_STATS_CFG_MSG_SZ 4 /* bytes */ 8744 8745 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M 0x0000ff00 8746 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S 8 8747 8748 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M 0xffff0000 8749 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S 16 8750 8751 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_GET(_var) \ 8752 (((_var) & HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M) >> \ 8753 HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S) 8754 8755 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_SET(_var, _val) \ 8756 do { \ 8757 HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_PDEV_MASK, _val); \ 8758 ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S)); \ 8759 } while (0) 8760 8761 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_GET(_var) \ 8762 (((_var) & HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M) >> \ 8763 HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S) 8764 8765 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_SET(_var, _val) \ 8766 do { \ 8767 HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK, _val); \ 8768 ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S)); \ 8769 } while (0) 8770 8771 /** 8772 * @brief Host-->target HTT RX FSE setup message 8773 * 8774 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG 8775 * 8776 * @details 8777 * Through this message, the host will provide details of the flow tables 8778 * in host DDR along with hash keys. 8779 * This message can be sent per SOC or per PDEV, which is differentiated 8780 * by pdev id values. 8781 * The host will allocate flow search table and sends table size, 8782 * physical DMA address of flow table, and hash keys to firmware to 8783 * program into the RXOLE FSE HW block. 8784 * 8785 * The following field definitions describe the format of the RX FSE setup 8786 * message sent from the host to target 8787 * 8788 * Header fields: 8789 * dword0 - b'7:0 - msg_type: This will be set to 8790 * 0x12 (HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG) 8791 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 8792 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that 8793 * pdev's LMAC ring. 8794 * b'31:16 - reserved : Reserved for future use 8795 * dword1 - b'19:0 - number of records: This field indicates the number of 8796 * entries in the flow table. For example: 8k number of 8797 * records is equivalent to 8798 * 8 * 1024 * sizeof(RX_FLOW_SEARCH_ENTRY_STRUCT) 8799 * b'27:20 - max search: This field specifies the skid length to FSE 8800 * parser HW module whenever match is not found at the 8801 * exact index pointed by hash. 8802 * b'29:28 - ip_da_sa: This indicates which IPV4-IPV6 RFC to be used. 8803 * Refer htt_ip_da_sa_prefix below for more details. 8804 * b'31:30 - reserved: Reserved for future use 8805 * dword2 - b'31:0 - base address lo: Lower 4 bytes base address of flow 8806 * table allocated by host in DDR 8807 * dword3 - b'31:0 - base address hi: Higher 4 bytes of base address of flow 8808 * table allocated by host in DDR 8809 * dword4:13 - b'31:0 - Toeplitz: 315 bits of Toeplitz keys for flow table 8810 * entry hashing 8811 * 8812 * 8813 * |31 30|29 28|27|26|25 20|19 16|15 8|7 0| 8814 * |---------------------------------------------------------------| 8815 * | reserved | pdev_id | MSG_TYPE | 8816 * |---------------------------------------------------------------| 8817 * |resvd|IPDSA| max_search | Number of records | 8818 * |---------------------------------------------------------------| 8819 * | base address lo | 8820 * |---------------------------------------------------------------| 8821 * | base address high | 8822 * |---------------------------------------------------------------| 8823 * | toeplitz key 31_0 | 8824 * |---------------------------------------------------------------| 8825 * | toeplitz key 63_32 | 8826 * |---------------------------------------------------------------| 8827 * | toeplitz key 95_64 | 8828 * |---------------------------------------------------------------| 8829 * | toeplitz key 127_96 | 8830 * |---------------------------------------------------------------| 8831 * | toeplitz key 159_128 | 8832 * |---------------------------------------------------------------| 8833 * | toeplitz key 191_160 | 8834 * |---------------------------------------------------------------| 8835 * | toeplitz key 223_192 | 8836 * |---------------------------------------------------------------| 8837 * | toeplitz key 255_224 | 8838 * |---------------------------------------------------------------| 8839 * | toeplitz key 287_256 | 8840 * |---------------------------------------------------------------| 8841 * | reserved | toeplitz key 314_288(26:0 bits) | 8842 * |---------------------------------------------------------------| 8843 * where: 8844 * IPDSA = ip_da_sa 8845 */ 8846 8847 /** 8848 * @brief: htt_ip_da_sa_prefix 8849 * 0x0 -> Prefix is 0x20010db8_00000000_00000000 8850 * IPv6 addresses beginning with 0x20010db8 are reserved for 8851 * documentation per RFC3849 8852 * 0x1 -> Prefix is 0x00000000_00000000_0000ffff RFC4291 IPv4-mapped IPv6 8853 * 0x2 -> Prefix is 0x0 RFC4291 IPv4-compatible IPv6 8854 * 0x3 -> Prefix is 0x0064ff9b_00000000_00000000 RFC6052 well-known prefix 8855 */ 8856 8857 enum htt_ip_da_sa_prefix { 8858 HTT_RX_IPV6_20010db8, 8859 HTT_RX_IPV4_MAPPED_IPV6, 8860 HTT_RX_IPV4_COMPATIBLE_IPV6, 8861 HTT_RX_IPV6_64FF9B, 8862 }; 8863 8864 8865 /** 8866 * @brief Host-->target HTT RX FISA configure and enable 8867 * 8868 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FISA_CFG 8869 * 8870 * @details 8871 * The host will send this command down to configure and enable the FISA 8872 * operational params. 8873 * Configure RXOLE_RXOLE_R0_FISA_CTRL and RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH 8874 * register. 8875 * Should configure both the MACs. 8876 * 8877 * dword0 - b'7:0 - msg_type: 8878 * This will be set to 0x15 (HTT_H2T_MSG_TYPE_RX_FISA_CFG) 8879 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 8880 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that 8881 * pdev's LMAC ring. 8882 * b'31:16 - reserved : Reserved for future use 8883 * 8884 * dword1 - b'0 - enable: Global FISA Enable, 0-FISA Disable, 1-Enable 8885 * b'1 - IPSEC_SKIP_SEARCH: Flow search will be skipped for IP_SEC 8886 * packets. 1 flow search will be skipped 8887 * b'2 - NON_TCP_SKIP_SEARCH: Flow search will be skipped for Non 8888 * tcp,udp packets 8889 * b'3 - ADD_IPV4_FIXED_HDR_LEN: Add IPV4 Fixed HDR to length 8890 * calculation 8891 * b'4 - ADD_IPV6_FIXED_HDR_LEN: Add IPV6 Fixed HDR to length 8892 * calculation 8893 * b'5 - ADD_TCP_FIXED_HDR_LEN: Add TCP Fixed HDR to length 8894 * calculation 8895 * b'6 - ADD_UDP_HDR_LEN: Add UDP HDR to length calculation 8896 * b'7 - CHKSUM_CUM_IP_LEN_EN: IPV4 hdr Checksum over cumulative IP 8897 * length 8898 * 0 L4 checksum will be provided in the RX_MSDU_END tlv 8899 * 1 IPV4 hdr checksum after adjusting for cumulative IP 8900 * length 8901 * b'8 - DISABLE_TID_CHECK: 1- Disable TID check for MPDU Sequence 8902 * num jump 8903 * b'9 - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence 8904 * num jump 8905 * b'10 - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos 8906 * data type switch has happened for MPDU Sequence num jump 8907 * b'11 - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type 8908 * for MPDU Sequence num jump 8909 * b'12 - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands 8910 * for decrypt errors 8911 * b'13 - DISABLE_MSDU_DROP_CHECK: 1- Ignore checking of msdu drop 8912 * while aggregating a msdu 8913 * b'17:14 - LIMIT, Aggregtion limit for number of MSDUs. 8914 * The aggregation is done until (number of MSDUs aggregated 8915 * < LIMIT + 1) 8916 * b'31:18 - Reserved 8917 * 8918 * fisa_control_value - 32bit value FW can write to register 8919 * 8920 * dword2 - b'31:0 - FISA_TIMEOUT_THRESH, Timeout threshold for aggregation 8921 * Threshold value for FISA timeout (units are microseconds). 8922 * When the global timestamp exceeds this threshold, FISA 8923 * aggregation will be restarted. 8924 * A value of 0 means timeout is disabled. 8925 * Compare the threshold register with timestamp field in 8926 * flow entry to generate timeout for the flow. 8927 * 8928 * |31 18 |17 16|15 8|7 0| 8929 * |-------------------------------------------------------------| 8930 * | reserved | pdev_mask | msg type | 8931 * |-------------------------------------------------------------| 8932 * | reserved | FISA_CTRL | 8933 * |-------------------------------------------------------------| 8934 * | FISA_TIMEOUT_THRESH | 8935 * |-------------------------------------------------------------| 8936 */ 8937 PREPACK struct htt_h2t_msg_type_fisa_config_t { 8938 A_UINT32 msg_type:8, 8939 pdev_id:8, 8940 reserved0:16; 8941 8942 /** 8943 * @brief fisa_control - RXOLE_RXOLE_R0_FISA_CTRL FISA control register 8944 * [17:0] 8945 */ 8946 union { 8947 /* 8948 * fisa_control_bits structure is deprecated. 8949 * Please use fisa_control_bits_v2 going forward. 8950 */ 8951 struct { 8952 A_UINT32 fisa_enable: 1, 8953 ipsec_skip_search: 1, 8954 nontcp_skip_search: 1, 8955 add_ipv4_fixed_hdr_len: 1, 8956 add_ipv6_fixed_hdr_len: 1, 8957 add_tcp_fixed_hdr_len: 1, 8958 add_udp_hdr_len: 1, 8959 chksum_cum_ip_len_en: 1, 8960 disable_tid_check: 1, 8961 disable_ta_check: 1, 8962 disable_qos_check: 1, 8963 disable_raw_check: 1, 8964 disable_decrypt_err_check: 1, 8965 disable_msdu_drop_check: 1, 8966 fisa_aggr_limit: 4, 8967 reserved: 14; 8968 } fisa_control_bits; 8969 struct { 8970 A_UINT32 fisa_enable: 1, 8971 fisa_aggr_limit: 6, 8972 reserved: 25; 8973 } fisa_control_bits_v2; 8974 8975 A_UINT32 fisa_control_value; 8976 } u_fisa_control; 8977 8978 /** 8979 * @brief fisa_timeout_threshold - RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH FISA 8980 * timeout threshold for aggregation. Unit in usec. 8981 * [31:0] 8982 */ 8983 A_UINT32 fisa_timeout_threshold; 8984 } POSTPACK; 8985 8986 8987 /* DWord 0: pdev-ID */ 8988 #define HTT_RX_FISA_CONFIG_PDEV_ID_M 0x0000ff00 8989 #define HTT_RX_FISA_CONFIG_PDEV_ID_S 8 8990 #define HTT_RX_FISA_CONFIG_PDEV_ID_GET(_var) \ 8991 (((_var) & HTT_RX_FISA_CONFIG_PDEV_ID_M) >> \ 8992 HTT_RX_FISA_CONFIG_PDEV_ID_S) 8993 #define HTT_RX_FISA_CONFIG_PDEV_ID_SET(_var, _val) \ 8994 do { \ 8995 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_PDEV_ID, _val); \ 8996 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_PDEV_ID_S)); \ 8997 } while (0) 8998 8999 /* Dword 1: fisa_control_value fisa config */ 9000 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_M 0x00000001 9001 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_S 0 9002 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_GET(_var) \ 9003 (((_var) & HTT_RX_FISA_CONFIG_FISA_ENABLE_M) >> \ 9004 HTT_RX_FISA_CONFIG_FISA_ENABLE_S) 9005 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_SET(_var, _val) \ 9006 do { \ 9007 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_ENABLE, _val); \ 9008 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_ENABLE_S)); \ 9009 } while (0) 9010 9011 /* Dword 1: fisa_control_value ipsec_skip_search */ 9012 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M 0x00000002 9013 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S 1 9014 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_GET(_var) \ 9015 (((_var) & HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M) >> \ 9016 HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S) 9017 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_SET(_var, _val) \ 9018 do { \ 9019 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH, _val); \ 9020 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)); \ 9021 } while (0) 9022 9023 /* Dword 1: fisa_control_value non_tcp_skip_search */ 9024 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M 0x00000004 9025 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S 2 9026 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_GET(_var) \ 9027 (((_var) & HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M) >> \ 9028 HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S) 9029 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_SET(_var, _val) \ 9030 do { \ 9031 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH, _val); \ 9032 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)); \ 9033 } while (0) 9034 9035 /* Dword 1: fisa_control_value add_ipv4_fixed_hdr */ 9036 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M 0x00000008 9037 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S 3 9038 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_GET(_var) \ 9039 (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M) >> \ 9040 HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S) 9041 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_SET(_var, _val) \ 9042 do { \ 9043 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN, _val); \ 9044 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)); \ 9045 } while (0) 9046 9047 /* Dword 1: fisa_control_value add_ipv6_fixed_hdr */ 9048 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M 0x00000010 9049 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S 4 9050 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_GET(_var) \ 9051 (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M) >> \ 9052 HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S) 9053 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_SET(_var, _val) \ 9054 do { \ 9055 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN, _val); \ 9056 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)); \ 9057 } while (0) 9058 9059 /* Dword 1: fisa_control_value tcp_fixed_hdr_len */ 9060 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M 0x00000020 9061 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S 5 9062 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_GET(_var) \ 9063 (((_var) & HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M) >> \ 9064 HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S) 9065 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_SET(_var, _val) \ 9066 do { \ 9067 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN, _val); \ 9068 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)); \ 9069 } while (0) 9070 9071 /* Dword 1: fisa_control_value add_udp_hdr_len */ 9072 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M 0x00000040 9073 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S 6 9074 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_GET(_var) \ 9075 (((_var) & HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M) >> \ 9076 HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S) 9077 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_SET(_var, _val) \ 9078 do { \ 9079 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN, _val); \ 9080 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)); \ 9081 } while (0) 9082 9083 /* Dword 1: fisa_control_value chksum_cum_ip_len_en */ 9084 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M 0x00000080 9085 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S 7 9086 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_GET(_var) \ 9087 (((_var) & HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M) >> \ 9088 HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S) 9089 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_SET(_var, _val) \ 9090 do { \ 9091 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN, _val); \ 9092 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)); \ 9093 } while (0) 9094 9095 /* Dword 1: fisa_control_value disable_tid_check */ 9096 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M 0x00000100 9097 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S 8 9098 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_GET(_var) \ 9099 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M) >> \ 9100 HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S) 9101 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_SET(_var, _val) \ 9102 do { \ 9103 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK, _val); \ 9104 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)); \ 9105 } while (0) 9106 9107 /* Dword 1: fisa_control_value disable_ta_check */ 9108 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M 0x00000200 9109 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S 9 9110 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_GET(_var) \ 9111 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M) >> \ 9112 HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S) 9113 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_SET(_var, _val) \ 9114 do { \ 9115 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK, _val); \ 9116 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)); \ 9117 } while (0) 9118 9119 /* Dword 1: fisa_control_value disable_qos_check */ 9120 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M 0x00000400 9121 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S 10 9122 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_GET(_var) \ 9123 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M) >> \ 9124 HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S) 9125 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_SET(_var, _val) \ 9126 do { \ 9127 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK, _val); \ 9128 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)); \ 9129 } while (0) 9130 9131 /* Dword 1: fisa_control_value disable_raw_check */ 9132 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M 0x00000800 9133 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S 11 9134 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_GET(_var) \ 9135 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M) >> \ 9136 HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S) 9137 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_SET(_var, _val) \ 9138 do { \ 9139 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK, _val); \ 9140 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)); \ 9141 } while (0) 9142 9143 /* Dword 1: fisa_control_value disable_decrypt_err_check */ 9144 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M 0x00001000 9145 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S 12 9146 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_GET(_var) \ 9147 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M) >> \ 9148 HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S) 9149 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_SET(_var, _val) \ 9150 do { \ 9151 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK, _val); \ 9152 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)); \ 9153 } while (0) 9154 9155 /* Dword 1: fisa_control_value disable_msdu_drop_check */ 9156 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M 0x00002000 9157 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S 13 9158 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_GET(_var) \ 9159 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M) >> \ 9160 HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S) 9161 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_SET(_var, _val) \ 9162 do { \ 9163 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK, _val); \ 9164 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)); \ 9165 } while (0) 9166 9167 /* Dword 1: fisa_control_value fisa_aggr_limit */ 9168 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M 0x0003c000 9169 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S 14 9170 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_GET(_var) \ 9171 (((_var) & HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M) >> \ 9172 HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S) 9173 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_SET(_var, _val) \ 9174 do { \ 9175 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT, _val); \ 9176 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)); \ 9177 } while (0) 9178 9179 /* Dword 1: fisa_control_value fisa config */ 9180 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M 0x00000001 9181 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S 0 9182 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_GET(_var) \ 9183 (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M) >> \ 9184 HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S) 9185 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_SET(_var, _val) \ 9186 do { \ 9187 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_ENABLE, _val); \ 9188 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S)); \ 9189 } while (0) 9190 9191 /* Dword 1: fisa_control_value fisa_aggr_limit */ 9192 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000007e 9193 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S 1 9194 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_GET(_var) \ 9195 (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M) >> \ 9196 HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S) 9197 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_SET(_var, _val) \ 9198 do { \ 9199 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT, _val); \ 9200 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S)); \ 9201 } while (0) 9202 9203 PREPACK struct htt_h2t_msg_rx_fse_setup_t { 9204 A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */ 9205 pdev_id:8, 9206 reserved0:16; 9207 A_UINT32 num_records:20, 9208 max_search:8, 9209 ip_da_sa:2, /* htt_ip_da_sa_prefix enumeration */ 9210 reserved1:2; 9211 A_UINT32 base_addr_lo; 9212 A_UINT32 base_addr_hi; 9213 A_UINT32 toeplitz31_0; 9214 A_UINT32 toeplitz63_32; 9215 A_UINT32 toeplitz95_64; 9216 A_UINT32 toeplitz127_96; 9217 A_UINT32 toeplitz159_128; 9218 A_UINT32 toeplitz191_160; 9219 A_UINT32 toeplitz223_192; 9220 A_UINT32 toeplitz255_224; 9221 A_UINT32 toeplitz287_256; 9222 A_UINT32 toeplitz314_288:27, 9223 reserved2:5; 9224 } POSTPACK; 9225 9226 #define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t)) 9227 #define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t)) 9228 #define HTT_RX_FISA_CONFIG_SZ (sizeof(struct htt_h2t_msg_type_fisa_config_t)) 9229 9230 #define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff 9231 #define HTT_RX_FSE_SETUP_HASH_314_288_S 0 9232 9233 /* DWORD 0: Pdev ID */ 9234 #define HTT_RX_FSE_SETUP_PDEV_ID_M 0x0000ff00 9235 #define HTT_RX_FSE_SETUP_PDEV_ID_S 8 9236 #define HTT_RX_FSE_SETUP_PDEV_ID_GET(_var) \ 9237 (((_var) & HTT_RX_FSE_SETUP_PDEV_ID_M) >> \ 9238 HTT_RX_FSE_SETUP_PDEV_ID_S) 9239 #define HTT_RX_FSE_SETUP_PDEV_ID_SET(_var, _val) \ 9240 do { \ 9241 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_PDEV_ID, _val); \ 9242 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_PDEV_ID_S)); \ 9243 } while (0) 9244 9245 /* DWORD 1:num of records */ 9246 #define HTT_RX_FSE_SETUP_NUM_REC_M 0x000fffff 9247 #define HTT_RX_FSE_SETUP_NUM_REC_S 0 9248 #define HTT_RX_FSE_SETUP_NUM_REC_GET(_var) \ 9249 (((_var) & HTT_RX_FSE_SETUP_NUM_REC_M) >> \ 9250 HTT_RX_FSE_SETUP_NUM_REC_S) 9251 #define HTT_RX_FSE_SETUP_NUM_REC_SET(_var, _val) \ 9252 do { \ 9253 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_NUM_REC, _val); \ 9254 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_NUM_REC_S)); \ 9255 } while (0) 9256 9257 /* DWORD 1:max_search */ 9258 #define HTT_RX_FSE_SETUP_MAX_SEARCH_M 0x0ff00000 9259 #define HTT_RX_FSE_SETUP_MAX_SEARCH_S 20 9260 #define HTT_RX_FSE_SETUP_MAX_SEARCH_GET(_var) \ 9261 (((_var) & HTT_RX_FSE_SETUP_MAX_SEARCH_M) >> \ 9262 HTT_RX_FSE_SETUP_MAX_SEARCH_S) 9263 #define HTT_RX_FSE_SETUP_MAX_SEARCH_SET(_var, _val) \ 9264 do { \ 9265 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_MAX_SEARCH, _val); \ 9266 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_MAX_SEARCH_S)); \ 9267 } while (0) 9268 9269 /* DWORD 1:ip_da_sa prefix */ 9270 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M 0x30000000 9271 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S 28 9272 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_GET(_var) \ 9273 (((_var) & HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M) >> \ 9274 HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S) 9275 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_SET(_var, _val) \ 9276 do { \ 9277 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX, _val); \ 9278 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)); \ 9279 } while (0) 9280 9281 /* DWORD 2: Base Address LO */ 9282 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_M 0xffffffff 9283 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_S 0 9284 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_GET(_var) \ 9285 (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_LO_M) >> \ 9286 HTT_RX_FSE_SETUP_BASE_ADDR_LO_S) 9287 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_SET(_var, _val) \ 9288 do { \ 9289 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_LO, _val); \ 9290 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)); \ 9291 } while (0) 9292 9293 /* DWORD 3: Base Address High */ 9294 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_M 0xffffffff 9295 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_S 0 9296 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_GET(_var) \ 9297 (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_HI_M) >> \ 9298 HTT_RX_FSE_SETUP_BASE_ADDR_HI_S) 9299 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_SET(_var, _val) \ 9300 do { \ 9301 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_HI, _val); \ 9302 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)); \ 9303 } while (0) 9304 9305 /* DWORD 4-12: Hash Value */ 9306 #define HTT_RX_FSE_SETUP_HASH_VALUE_M 0xffffffff 9307 #define HTT_RX_FSE_SETUP_HASH_VALUE_S 0 9308 #define HTT_RX_FSE_SETUP_HASH_VALUE_GET(_var) \ 9309 (((_var) & HTT_RX_FSE_SETUP_HASH_VALUE_M) >> \ 9310 HTT_RX_FSE_SETUP_HASH_VALUE_S) 9311 #define HTT_RX_FSE_SETUP_HASH_VALUE_SET(_var, _val) \ 9312 do { \ 9313 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_VALUE, _val); \ 9314 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_VALUE_S)); \ 9315 } while (0) 9316 9317 /* DWORD 13: Hash Value 314:288 bits */ 9318 #define HTT_RX_FSE_SETUP_HASH_314_288_GET(_var) \ 9319 (((_var) & HTT_RX_FSE_SETUP_HASH_314_288_M) >> \ 9320 HTT_RX_FSE_SETUP_HASH_314_288_S) 9321 #define HTT_RX_FSE_SETUP_HASH_314_288_SET(_var, _val) \ 9322 do { \ 9323 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_314_288, _val); \ 9324 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_314_288_S)); \ 9325 } while (0) 9326 9327 /** 9328 * @brief Host-->target HTT RX FSE operation message 9329 * 9330 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG 9331 * 9332 * @details 9333 * The host will send this Flow Search Engine (FSE) operation message for 9334 * every flow add/delete operation. 9335 * The FSE operation includes FSE full cache invalidation or individual entry 9336 * invalidation. 9337 * This message can be sent per SOC or per PDEV which is differentiated 9338 * by pdev id values. 9339 * 9340 * |31 16|15 8|7 1|0| 9341 * |-------------------------------------------------------------| 9342 * | reserved | pdev_id | MSG_TYPE | 9343 * |-------------------------------------------------------------| 9344 * | reserved | operation |I| 9345 * |-------------------------------------------------------------| 9346 * | ip_src_addr_31_0 | 9347 * |-------------------------------------------------------------| 9348 * | ip_src_addr_63_32 | 9349 * |-------------------------------------------------------------| 9350 * | ip_src_addr_95_64 | 9351 * |-------------------------------------------------------------| 9352 * | ip_src_addr_127_96 | 9353 * |-------------------------------------------------------------| 9354 * | ip_dst_addr_31_0 | 9355 * |-------------------------------------------------------------| 9356 * | ip_dst_addr_63_32 | 9357 * |-------------------------------------------------------------| 9358 * | ip_dst_addr_95_64 | 9359 * |-------------------------------------------------------------| 9360 * | ip_dst_addr_127_96 | 9361 * |-------------------------------------------------------------| 9362 * | l4_dst_port | l4_src_port | 9363 * | (32-bit SPI incase of IPsec) | 9364 * |-------------------------------------------------------------| 9365 * | reserved | l4_proto | 9366 * |-------------------------------------------------------------| 9367 * 9368 * where I is 1-bit ipsec_valid. 9369 * 9370 * The following field definitions describe the format of the RX FSE operation 9371 * message sent from the host to target for every add/delete flow entry to flow 9372 * table. 9373 * 9374 * Header fields: 9375 * dword0 - b'7:0 - msg_type: This will be set to 9376 * 0x13 (HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG) 9377 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9378 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9379 * specified pdev's LMAC ring. 9380 * b'31:16 - reserved : Reserved for future use 9381 * dword1 - b'0 - ipsec_valid: This indicates protocol IP or IPsec 9382 * (Internet Protocol Security). 9383 * IPsec describes the framework for providing security at 9384 * IP layer. IPsec is defined for both versions of IP: 9385 * IPV4 and IPV6. 9386 * Please refer to htt_rx_flow_proto enumeration below for 9387 * more info. 9388 * ipsec_valid = 1 for IPSEC packets 9389 * ipsec_valid = 0 for IP Packets 9390 * b'7:1 - operation: This indicates types of FSE operation. 9391 * Refer to htt_rx_fse_operation enumeration: 9392 * 0 - No Cache Invalidation required 9393 * 1 - Cache invalidate only one entry given by IP 9394 * src/dest address at DWORD[2:9] 9395 * 2 - Complete FSE Cache Invalidation 9396 * 3 - FSE Disable 9397 * 4 - FSE Enable 9398 * b'31:8 - reserved: Reserved for future use 9399 * dword2:9-b'31:0 - IP src/dest: IPV4/IPV6 source and destination address 9400 * for per flow addition/deletion 9401 * For IPV4 src/dest addresses, the first A_UINT32 is used 9402 * and the subsequent 3 A_UINT32 will be padding bytes. 9403 * For IPV6 src/dest Addresses, all A_UINT32 are used. 9404 * dword10 -b'31:0 - L4 src port (15:0): 16-bit Source Port numbers range 9405 * from 0 to 65535 but only 0 to 1023 are designated as 9406 * well-known ports. Refer to [RFC1700] for more details. 9407 * This field is valid only if 9408 * (valid_ip_proto(l4_proto) && (ipsec_valid == 0)) 9409 * - L4 dest port (31:16): 16-bit Destination Port numbers 9410 * range from 0 to 65535 but only 0 to 1023 are designated 9411 * as well-known ports. Refer to [RFC1700] for more details. 9412 * This field is valid only if 9413 * (valid_ip_proto(l4_proto) && (ipsec_valid == 0)) 9414 * - SPI (31:0): Security Parameters Index is an 9415 * identification tag added to the header while using IPsec 9416 * for tunneling the IP traffici. 9417 * Valid only if IPSec_valid bit (in DWORD1) is set to 1. 9418 * dword11 -b'7:0 - l4_proto: This carries L4 protocol numbers, which are 9419 * Assigned Internet Protocol Numbers. 9420 * l4_proto numbers for standard protocol like UDP/TCP 9421 * protocol at l4 layer, e.g. l4_proto = 6 for TCP, 9422 * l4_proto = 17 for UDP etc. 9423 * b'31:8 - reserved: Reserved for future use. 9424 * 9425 */ 9426 9427 PREPACK struct htt_h2t_msg_rx_fse_operation_t { 9428 A_UINT32 msg_type:8, 9429 pdev_id:8, 9430 reserved0:16; 9431 A_UINT32 ipsec_valid:1, 9432 operation:7, 9433 reserved1:24; 9434 A_UINT32 ip_src_addr_31_0; 9435 A_UINT32 ip_src_addr_63_32; 9436 A_UINT32 ip_src_addr_95_64; 9437 A_UINT32 ip_src_addr_127_96; 9438 A_UINT32 ip_dest_addr_31_0; 9439 A_UINT32 ip_dest_addr_63_32; 9440 A_UINT32 ip_dest_addr_95_64; 9441 A_UINT32 ip_dest_addr_127_96; 9442 union { 9443 A_UINT32 spi; 9444 struct { 9445 A_UINT32 l4_src_port:16, 9446 l4_dest_port:16; 9447 } ip; 9448 } u; 9449 A_UINT32 l4_proto:8, 9450 reserved:24; 9451 } POSTPACK; 9452 9453 /** 9454 * @brief Host-->target HTT RX Full monitor mode register configuration message 9455 * 9456 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE 9457 * 9458 * @details 9459 * The host will send this Full monitor mode register configuration message. 9460 * This message can be sent per SOC or per PDEV which is differentiated 9461 * by pdev id values. 9462 * 9463 * |31 16|15 11|10 8|7 3|2|1|0| 9464 * |-------------------------------------------------------------| 9465 * | reserved | pdev_id | MSG_TYPE | 9466 * |-------------------------------------------------------------| 9467 * | reserved |Release Ring |N|Z|E| 9468 * |-------------------------------------------------------------| 9469 * 9470 * where E is 1-bit full monitor mode enable/disable. 9471 * Z is 1-bit additional descriptor for zero mpdu enable/disable 9472 * N is 1-bit additional descriptor for non zero mdpu enable/disable 9473 * 9474 * The following field definitions describe the format of the full monitor 9475 * mode configuration message sent from the host to target for each pdev. 9476 * 9477 * Header fields: 9478 * dword0 - b'7:0 - msg_type: This will be set to 9479 * 0x17 (HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE) 9480 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9481 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9482 * specified pdev's LMAC ring. 9483 * b'31:16 - reserved : Reserved for future use. 9484 * dword1 - b'0 - full_monitor_mode enable: This indicates that the full 9485 * monitor mode rxdma register is to be enabled or disabled. 9486 * b'1 - addnl_descs_zero_mpdus_end: This indicates that the 9487 * additional descriptors at ppdu end for zero mpdus 9488 * enabled or disabled. 9489 * b'2 - addnl_descs_non_zero_mpdus_end: This indicates that the 9490 * additional descriptors at ppdu end for non zero mpdus 9491 * enabled or disabled. 9492 * b'10:3 - release_ring: This indicates the destination ring 9493 * selection for the descriptor at the end of PPDU 9494 * 0 - REO ring select 9495 * 1 - FW ring select 9496 * 2 - SW ring select 9497 * 3 - Release ring select 9498 * Refer to htt_rx_full_mon_release_ring. 9499 * b'31:11 - reserved for future use 9500 */ 9501 PREPACK struct htt_h2t_msg_rx_full_monitor_mode_t { 9502 A_UINT32 msg_type:8, 9503 pdev_id:8, 9504 reserved0:16; 9505 A_UINT32 full_monitor_mode_enable:1, 9506 addnl_descs_zero_mpdus_end:1, 9507 addnl_descs_non_zero_mpdus_end:1, 9508 release_ring:8, 9509 reserved1:21; 9510 } POSTPACK; 9511 9512 /** 9513 * Enumeration for full monitor mode destination ring select 9514 * 0 - REO destination ring select 9515 * 1 - FW destination ring select 9516 * 2 - SW destination ring select 9517 * 3 - Release destination ring select 9518 */ 9519 enum htt_rx_full_mon_release_ring { 9520 HTT_RX_MON_RING_REO, 9521 HTT_RX_MON_RING_FW, 9522 HTT_RX_MON_RING_SW, 9523 HTT_RX_MON_RING_RELEASE, 9524 }; 9525 9526 #define HTT_RX_FULL_MONITOR_MODE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_full_monitor_mode_t)) 9527 /* DWORD 0: Pdev ID */ 9528 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M 0x0000ff00 9529 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S 8 9530 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_GET(_var) \ 9531 (((_var) & HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M) >> \ 9532 HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S) 9533 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_SET(_var, _val) \ 9534 do { \ 9535 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID, _val); \ 9536 ((_var) |= ((_val) << HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)); \ 9537 } while (0) 9538 9539 /* DWORD 1:ENABLE */ 9540 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_M 0x00000001 9541 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_S 0 9542 9543 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_SET(word, enable) \ 9544 do { \ 9545 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ENABLE, enable); \ 9546 (word) |= ((enable) << HTT_RX_FULL_MONITOR_MODE_ENABLE_S); \ 9547 } while (0) 9548 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_GET(word) \ 9549 (((word) & HTT_RX_FULL_MONITOR_MODE_ENABLE_M) >> HTT_RX_FULL_MONITOR_MODE_ENABLE_S) 9550 9551 /* DWORD 1:ZERO_MPDU */ 9552 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M 0x00000002 9553 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S 1 9554 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_SET(word, zerompdu) \ 9555 do { \ 9556 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU, zerompdu); \ 9557 (word) |= ((zerompdu) << HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S); \ 9558 } while (0) 9559 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_GET(word) \ 9560 (((word) & HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S) 9561 9562 9563 /* DWORD 1:NON_ZERO_MPDU */ 9564 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M 0x00000004 9565 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S 2 9566 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_SET(word, nonzerompdu) \ 9567 do { \ 9568 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU, nonzerompdu); \ 9569 (word) |= ((nonzerompdu) << HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S); \ 9570 } while (0) 9571 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_GET(word) \ 9572 (((word) & HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S) 9573 9574 /* DWORD 1:RELEASE_RINGS */ 9575 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M 0x000007f8 9576 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S 3 9577 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_SET(word, releaserings) \ 9578 do { \ 9579 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS, releaserings); \ 9580 (word) |= ((releaserings) << HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S); \ 9581 } while (0) 9582 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_GET(word) \ 9583 (((word) & HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M) >> HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S) 9584 9585 /** 9586 * Enumeration for IP Protocol or IPSEC Protocol 9587 * IPsec describes the framework for providing security at IP layer. 9588 * IPsec is defined for both versions of IP: IPV4 and IPV6. 9589 */ 9590 enum htt_rx_flow_proto { 9591 HTT_RX_FLOW_IP_PROTO, 9592 HTT_RX_FLOW_IPSEC_PROTO, 9593 }; 9594 9595 /** 9596 * Enumeration for FSE Cache Invalidation 9597 * 0 - No Cache Invalidation required 9598 * 1 - Cache invalidate only one entry given by IP src/dest address at DWORD2:9 9599 * 2 - Complete FSE Cache Invalidation 9600 * 3 - FSE Disable 9601 * 4 - FSE Enable 9602 */ 9603 enum htt_rx_fse_operation { 9604 HTT_RX_FSE_CACHE_INVALIDATE_NONE, 9605 HTT_RX_FSE_CACHE_INVALIDATE_ENTRY, 9606 HTT_RX_FSE_CACHE_INVALIDATE_FULL, 9607 HTT_RX_FSE_DISABLE, 9608 HTT_RX_FSE_ENABLE, 9609 }; 9610 9611 /* DWORD 0: Pdev ID */ 9612 #define HTT_RX_FSE_OPERATION_PDEV_ID_M 0x0000ff00 9613 #define HTT_RX_FSE_OPERATION_PDEV_ID_S 8 9614 #define HTT_RX_FSE_OPERATION_PDEV_ID_GET(_var) \ 9615 (((_var) & HTT_RX_FSE_OPERATION_PDEV_ID_M) >> \ 9616 HTT_RX_FSE_OPERATION_PDEV_ID_S) 9617 #define HTT_RX_FSE_OPERATION_PDEV_ID_SET(_var, _val) \ 9618 do { \ 9619 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_PDEV_ID, _val); \ 9620 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_PDEV_ID_S)); \ 9621 } while (0) 9622 9623 /* DWORD 1:IP PROTO or IPSEC */ 9624 #define HTT_RX_FSE_IPSEC_VALID_M 0x00000001 9625 #define HTT_RX_FSE_IPSEC_VALID_S 0 9626 9627 #define HTT_RX_FSE_IPSEC_VALID_SET(word, ipsec_valid) \ 9628 do { \ 9629 HTT_CHECK_SET_VAL(HTT_RX_FSE_IPSEC_VALID, ipsec_valid); \ 9630 (word) |= ((ipsec_valid) << HTT_RX_FSE_IPSEC_VALID_S); \ 9631 } while (0) 9632 #define HTT_RX_FSE_IPSEC_VALID_GET(word) \ 9633 (((word) & HTT_RX_FSE_IPSEC_VALID_M) >> HTT_RX_FSE_IPSEC_VALID_S) 9634 9635 /* DWORD 1:FSE Operation */ 9636 #define HTT_RX_FSE_OPERATION_M 0x000000fe 9637 #define HTT_RX_FSE_OPERATION_S 1 9638 9639 #define HTT_RX_FSE_OPERATION_SET(word, op_val) \ 9640 do { \ 9641 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION, op_val); \ 9642 (word) |= ((op_val) << HTT_RX_FSE_OPERATION_S); \ 9643 } while (0) 9644 #define HTT_RX_FSE_OPERATION_GET(word) \ 9645 (((word) & HTT_RX_FSE_OPERATION_M) >> HTT_RX_FSE_OPERATION_S) 9646 9647 /* DWORD 2-9:IP Address */ 9648 #define HTT_RX_FSE_OPERATION_IP_ADDR_M 0xffffffff 9649 #define HTT_RX_FSE_OPERATION_IP_ADDR_S 0 9650 #define HTT_RX_FSE_OPERATION_IP_ADDR_GET(_var) \ 9651 (((_var) & HTT_RX_FSE_OPERATION_IP_ADDR_M) >> \ 9652 HTT_RX_FSE_OPERATION_IP_ADDR_S) 9653 #define HTT_RX_FSE_OPERATION_IP_ADDR_SET(_var, _val) \ 9654 do { \ 9655 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_IP_ADDR, _val); \ 9656 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_IP_ADDR_S)); \ 9657 } while (0) 9658 9659 /* DWORD 10:Source Port Number */ 9660 #define HTT_RX_FSE_SOURCEPORT_M 0x0000ffff 9661 #define HTT_RX_FSE_SOURCEPORT_S 0 9662 9663 #define HTT_RX_FSE_SOURCEPORT_SET(word, sport) \ 9664 do { \ 9665 HTT_CHECK_SET_VAL(HTT_RX_FSE_SOURCEPORT, sport); \ 9666 (word) |= ((sport) << HTT_RX_FSE_SOURCEPORT_S); \ 9667 } while (0) 9668 #define HTT_RX_FSE_SOURCEPORT_GET(word) \ 9669 (((word) & HTT_RX_FSE_SOURCEPORT_M) >> HTT_RX_FSE_SOURCEPORT_S) 9670 9671 9672 /* DWORD 11:Destination Port Number */ 9673 #define HTT_RX_FSE_DESTPORT_M 0xffff0000 9674 #define HTT_RX_FSE_DESTPORT_S 16 9675 9676 #define HTT_RX_FSE_DESTPORT_SET(word, dport) \ 9677 do { \ 9678 HTT_CHECK_SET_VAL(HTT_RX_FSE_DESTPORT, dport); \ 9679 (word) |= ((dport) << HTT_RX_FSE_DESTPORT_S); \ 9680 } while (0) 9681 #define HTT_RX_FSE_DESTPORT_GET(word) \ 9682 (((word) & HTT_RX_FSE_DESTPORT_M) >> HTT_RX_FSE_DESTPORT_S) 9683 9684 /* DWORD 10-11:SPI (In case of IPSEC) */ 9685 #define HTT_RX_FSE_OPERATION_SPI_M 0xffffffff 9686 #define HTT_RX_FSE_OPERATION_SPI_S 0 9687 #define HTT_RX_FSE_OPERATION_SPI_GET(_var) \ 9688 (((_var) & HTT_RX_FSE_OPERATION_SPI_ADDR_M) >> \ 9689 HTT_RX_FSE_OPERATION_SPI_ADDR_S) 9690 #define HTT_RX_FSE_OPERATION_SPI_SET(_var, _val) \ 9691 do { \ 9692 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_SPI, _val); \ 9693 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_SPI_S)); \ 9694 } while (0) 9695 9696 /* DWORD 12:L4 PROTO */ 9697 #define HTT_RX_FSE_L4_PROTO_M 0x000000ff 9698 #define HTT_RX_FSE_L4_PROTO_S 0 9699 9700 #define HTT_RX_FSE_L4_PROTO_SET(word, proto_val) \ 9701 do { \ 9702 HTT_CHECK_SET_VAL(HTT_RX_FSE_L4_PROTO, proto_val); \ 9703 (word) |= ((proto_val) << HTT_RX_FSE_L4_PROTO_S); \ 9704 } while (0) 9705 #define HTT_RX_FSE_L4_PROTO_GET(word) \ 9706 (((word) & HTT_RX_FSE_L4_PROTO_M) >> HTT_RX_FSE_L4_PROTO_S) 9707 9708 9709 /** 9710 * @brief host --> target Receive to configure the RxOLE 3-tuple Hash 9711 * 9712 * MSG_TYPE => HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG 9713 * 9714 * |31 24|23 |15 8|7 3|2|1|0| 9715 * |----------------+----------------+----------------+----------------| 9716 * | reserved | pdev_id | msg_type | 9717 * |---------------------------------+----------------+----------------| 9718 * | reserved |G|E|F| 9719 * |---------------------------------+----------------+----------------| 9720 * Where E = Configure the target to provide the 3-tuple hash value in 9721 * toeplitz_hash_2_or_4 field of rx_msdu_start tlv 9722 * F = Configure the target to provide the 3-tuple hash value in 9723 * flow_id_toeplitz field of rx_msdu_start tlv 9724 * G = Configure the target to provide the 3-tuple based flow 9725 * classification search 9726 * 9727 * The following field definitions describe the format of the 3 tuple hash value 9728 * message sent from the host to target as part of initialization sequence. 9729 * 9730 * Header fields: 9731 * dword0 - b'7:0 - msg_type: This will be set to 9732 * 0x16 (HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG) 9733 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9734 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9735 * specified pdev's LMAC ring. 9736 * b'31:16 - reserved : Reserved for future use 9737 * dword1 - b'0 - flow_id_toeplitz_field_enable 9738 * b'1 - toeplitz_hash_2_or_4_field_enable 9739 * b'2 - flow_classification_3_tuple_field_enable 9740 * b'31:3 - reserved : Reserved for future use 9741 * ---------+------+---------------------------------------------------------- 9742 * bit1 | bit0 | Functionality 9743 * ---------+------+---------------------------------------------------------- 9744 * 0 | 1 | Configure the target to provide the 3 tuple hash value 9745 * | | in flow_id_toeplitz field 9746 * ---------+------+---------------------------------------------------------- 9747 * 1 | 0 | Configure the target to provide the 3 tuple hash value 9748 * | | in toeplitz_hash_2_or_4 field 9749 * ---------+------+---------------------------------------------------------- 9750 * 1 | 1 | Configure the target to provide the 3 tuple hash value 9751 * | | in both flow_id_toeplitz & toeplitz_hash_2_or_4 field 9752 * ---------+------+---------------------------------------------------------- 9753 * 0 | 0 | Configure the target to provide the 5 tuple hash value 9754 * | | in flow_id_toeplitz field 2 or 4 tuple has value in 9755 * | | toeplitz_hash_2_or_4 field 9756 *---------------------------------------------------------------------------- 9757 */ 9758 PREPACK struct htt_h2t_msg_rx_3_tuple_hash_cfg_t { 9759 A_UINT32 msg_type :8, 9760 pdev_id :8, 9761 reserved0 :16; 9762 A_UINT32 flow_id_toeplitz_field_enable :1, 9763 toeplitz_hash_2_or_4_field_enable :1, 9764 flow_classification_3_tuple_field_enable :1, 9765 reserved1 :29; 9766 } POSTPACK; 9767 9768 /* DWORD0 : pdev_id configuration Macros */ 9769 #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_M 0xff00 9770 #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_S 8 9771 #define HTT_RX_3_TUPLE_HASH_PDEV_ID_GET(_var) \ 9772 (((_var) & HTT_H2T_3_TUPLE_HASH_PDEV_ID_M) >> \ 9773 HTT_H2T_3_TUPLE_HASH_PDEV_ID_S) 9774 #define HTT_RX_3_TUPLE_HASH_PDEV_ID_SET(_var, _val) \ 9775 do { \ 9776 HTT_CHECK_SET_VAL(HTT_H2T_3_TUPLE_HASH_PDEV_ID, _val); \ 9777 ((_var) |= ((_val) << HTT_H2T_3_TUPLE_HASH_PDEV_ID_S)); \ 9778 } while (0) 9779 9780 /* DWORD1: rx 3 tuple hash value reception field configuration Macros */ 9781 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M 0x00000001 9782 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S 0 9783 #define HTT_FLOW_ID_TOEPLITZ_FIELD_CONFIG_GET(_var) \ 9784 (((_var) & HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M) >> \ 9785 HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S) 9786 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_SET(_var, _val) \ 9787 do { \ 9788 HTT_CHECK_SET_VAL(HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG, _val); \ 9789 ((_var) |= ((_val) << HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S)); \ 9790 } while (0) 9791 9792 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M 0x00000002 9793 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S 1 9794 #define HTT_TOEPLITZ_2_OR_4_FIELD_CONFIG_GET(_var) \ 9795 (((_var) & HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M) >> \ 9796 HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S) 9797 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_SET(_var, _val) \ 9798 do { \ 9799 HTT_CHECK_SET_VAL(HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG, _val); \ 9800 ((_var) |= ((_val) << HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S)); \ 9801 } while (0) 9802 9803 #define HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_M 0x00000004 9804 #define HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_S 2 9805 #define HTT_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_GET(_var) \ 9806 (((_var) & HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_M) >> \ 9807 HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_S) 9808 #define HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_SET(_var, _val) \ 9809 do { \ 9810 HTT_CHECK_SET_VAL(HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE, _val); \ 9811 ((_var) |= ((_val) << HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_S)); \ 9812 } while (0) 9813 9814 9815 #define HTT_3_TUPLE_HASH_CFG_REQ_BYTES 8 9816 9817 /** 9818 * @brief host --> target Host PA Address Size 9819 * 9820 * MSG_TYPE => HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE 9821 * 9822 * @details 9823 * The HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE message is sent by the host to 9824 * provide the physical start address and size of each of the memory 9825 * areas within host DDR that the target FW may need to access. 9826 * 9827 * For example, the host can use this message to allow the target FW 9828 * to set up access to the host's pools of TQM link descriptors. 9829 * The message would appear as follows: 9830 * 9831 * |31 24|23 16|15 8|7 0| 9832 * |----------------+----------------+----------------+----------------| 9833 * | reserved | num_entries | msg_type | 9834 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9835 * | mem area 0 size | 9836 * |----------------+----------------+----------------+----------------| 9837 * | mem area 0 physical_address_lo | 9838 * |----------------+----------------+----------------+----------------| 9839 * | mem area 0 physical_address_hi | 9840 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9841 * | mem area 1 size | 9842 * |----------------+----------------+----------------+----------------| 9843 * | mem area 1 physical_address_lo | 9844 * |----------------+----------------+----------------+----------------| 9845 * | mem area 1 physical_address_hi | 9846 * |----------------+----------------+----------------+----------------| 9847 * ... 9848 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9849 * | mem area N size | 9850 * |----------------+----------------+----------------+----------------| 9851 * | mem area N physical_address_lo | 9852 * |----------------+----------------+----------------+----------------| 9853 * | mem area N physical_address_hi | 9854 * |----------------+----------------+----------------+----------------| 9855 * 9856 * The message is interpreted as follows: 9857 * dword0 - b'0:7 - msg_type: This will be set to 9858 * 0x18 (HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE) 9859 * b'8:15 - number_entries: Indicated the number of host memory 9860 * areas specified within the remainder of the message 9861 * b'16:31 - reserved. 9862 * dword1 - b'0:31 - memory area 0 size in bytes 9863 * dword2 - b'0:31 - memory area 0 physical address, lower 32 bits 9864 * dword3 - b'0:31 - memory area 0 physical address, upper 32 bits 9865 * and similar for memory area 1 through memory area N. 9866 */ 9867 9868 PREPACK struct htt_h2t_host_paddr_size { 9869 A_UINT32 msg_type: 8, 9870 num_entries: 8, 9871 reserved: 16; 9872 } POSTPACK; 9873 9874 PREPACK struct htt_h2t_host_paddr_size_entry_t { 9875 A_UINT32 size; 9876 A_UINT32 physical_address_lo; 9877 A_UINT32 physical_address_hi; 9878 } POSTPACK; 9879 9880 #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE \ 9881 (sizeof(struct htt_h2t_host_paddr_size_entry_t)) 9882 #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_DWORDS \ 9883 (HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE >> 2) 9884 9885 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M 0x0000FF00 9886 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S 8 9887 9888 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_GET(_var) \ 9889 (((_var) & HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M) >> \ 9890 HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S) 9891 9892 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_SET(_var, _val) \ 9893 do { \ 9894 HTT_CHECK_SET_VAL(HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES, _val); \ 9895 ((_var) |= ((_val) << HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S)); \ 9896 } while (0) 9897 9898 /** 9899 * @brief host --> target Host RXDMA RXOLE PPE register configuration 9900 * 9901 * MSG_TYPE => HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG 9902 * 9903 * @details 9904 * The HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG message is sent by the host to 9905 * provide the PPE DS register confiuration for RXOLE and RXDMA. 9906 * 9907 * The message would appear as follows: 9908 * 9909 * |31 19|18 |17 |16 |15 |14 |13 9|8|7 0| 9910 * |---------------------------------+---+---+----------+-+-----------| 9911 * | reserved |IFO|DNO|DRO|IBO|MIO| RDI |O| msg_type | 9912 * |---------------------+---+---+---+---+---+----------+-+-----------| 9913 * 9914 * 9915 * The message is interpreted as follows: 9916 * dword0 - b'0:7 - msg_type: This will be set to 9917 * 0x19 (HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG) 9918 * b'8 - override bit to drive MSDUs to PPE ring 9919 * b'9:13 - REO destination ring indication 9920 * b'14 - Multi buffer msdu override enable bit 9921 * b'15 - Intra BSS override 9922 * b'16 - Decap raw override 9923 * b'17 - Decap Native wifi override 9924 * b'18 - IP frag override 9925 * b'19:31 - reserved 9926 */ 9927 PREPACK struct htt_h2t_msg_type_rxdma_rxole_ppe_cfg_t { 9928 A_UINT32 msg_type: 8, /* HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG */ 9929 override: 1, 9930 reo_destination_indication: 5, 9931 multi_buffer_msdu_override_en: 1, 9932 intra_bss_override: 1, 9933 decap_raw_override: 1, 9934 decap_nwifi_override: 1, 9935 ip_frag_override: 1, 9936 reserved: 13; 9937 } POSTPACK; 9938 9939 /* DWORD 0: Override */ 9940 #define HTT_PPE_CFG_OVERRIDE_M 0x00000100 9941 #define HTT_PPE_CFG_OVERRIDE_S 8 9942 #define HTT_PPE_CFG_OVERRIDE_GET(_var) \ 9943 (((_var) & HTT_PPE_CFG_OVERRIDE_M) >> \ 9944 HTT_PPE_CFG_OVERRIDE_S) 9945 #define HTT_PPE_CFG_OVERRIDE_SET(_var, _val) \ 9946 do { \ 9947 HTT_CHECK_SET_VAL(HTT_PPE_CFG_OVERRIDE, _val); \ 9948 ((_var) |= ((_val) << HTT_PPE_CFG_OVERRIDE_S)); \ 9949 } while (0) 9950 9951 /* DWORD 0: REO Destination Indication*/ 9952 #define HTT_PPE_CFG_REO_DEST_IND_M 0x00003E00 9953 #define HTT_PPE_CFG_REO_DEST_IND_S 9 9954 #define HTT_PPE_CFG_REO_DEST_IND_GET(_var) \ 9955 (((_var) & HTT_PPE_CFG_REO_DEST_IND_M) >> \ 9956 HTT_PPE_CFG_REO_DEST_IND_S) 9957 #define HTT_PPE_CFG_REO_DEST_IND_SET(_var, _val) \ 9958 do { \ 9959 HTT_CHECK_SET_VAL(HTT_PPE_CFG_REO_DEST_IND, _val); \ 9960 ((_var) |= ((_val) << HTT_PPE_CFG_REO_DEST_IND_S)); \ 9961 } while (0) 9962 9963 /* DWORD 0: Multi buffer MSDU override */ 9964 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M 0x00004000 9965 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S 14 9966 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_GET(_var) \ 9967 (((_var) & HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M) >> \ 9968 HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S) 9969 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_SET(_var, _val) \ 9970 do { \ 9971 HTT_CHECK_SET_VAL(HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN, _val); \ 9972 ((_var) |= ((_val) << HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S)); \ 9973 } while (0) 9974 9975 /* DWORD 0: Intra BSS override */ 9976 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M 0x00008000 9977 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S 15 9978 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_GET(_var) \ 9979 (((_var) & HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M) >> \ 9980 HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S) 9981 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_SET(_var, _val) \ 9982 do { \ 9983 HTT_CHECK_SET_VAL(HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN, _val); \ 9984 ((_var) |= ((_val) << HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S)); \ 9985 } while (0) 9986 9987 /* DWORD 0: Decap RAW override */ 9988 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M 0x00010000 9989 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S 16 9990 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_GET(_var) \ 9991 (((_var) & HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M) >> \ 9992 HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S) 9993 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_SET(_var, _val) \ 9994 do { \ 9995 HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN, _val); \ 9996 ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S)); \ 9997 } while (0) 9998 9999 /* DWORD 0: Decap NWIFI override */ 10000 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M 0x00020000 10001 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S 17 10002 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_GET(_var) \ 10003 (((_var) & HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M) >> \ 10004 HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S) 10005 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_SET(_var, _val) \ 10006 do { \ 10007 HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN, _val); \ 10008 ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S)); \ 10009 } while (0) 10010 10011 /* DWORD 0: IP frag override */ 10012 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M 0x00040000 10013 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S 18 10014 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_GET(_var) \ 10015 (((_var) & HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M) >> \ 10016 HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S) 10017 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_SET(_var, _val) \ 10018 do { \ 10019 HTT_CHECK_SET_VAL(HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN, _val); \ 10020 ((_var) |= ((_val) << HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S)); \ 10021 } while (0) 10022 10023 /* 10024 * MSG_TYPE => HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG 10025 * 10026 * @details 10027 * The following field definitions describe the format of the HTT host 10028 * to target FW VDEV TX RX stats retrieve message. 10029 * The message specifies the type of stats the host wants to retrieve. 10030 * 10031 * |31 27|26 25|24 17|16|15 8|7 0| 10032 * |-----------------------------------------------------------| 10033 * | rsvd | R | Periodic Int| E| pdev_id | msg type | 10034 * |-----------------------------------------------------------| 10035 * | vdev_id lower bitmask | 10036 * |-----------------------------------------------------------| 10037 * | vdev_id upper bitmask | 10038 * |-----------------------------------------------------------| 10039 * Header fields: 10040 * Where: 10041 * dword0 - b'7:0 - msg_type: This will be set to 10042 * 0x1a (HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG) 10043 * b'15:8 - pdev id 10044 * b'16(E) - Enable/Disable the vdev HW stats 10045 * b'17:24(PI) - Periodic Interval, units = 8 ms, e.g. 125 -> 1000 ms 10046 * b'25:26(R) - Reset stats bits 10047 * 0: don't reset stats 10048 * 1: reset stats once 10049 * 2: reset stats at the start of each periodic interval 10050 * b'27:31 - reserved for future use 10051 * dword1 - b'0:31 - vdev_id lower bitmask 10052 * dword2 - b'0:31 - vdev_id upper bitmask 10053 */ 10054 10055 PREPACK struct htt_h2t_vdevs_txrx_stats_cfg { 10056 A_UINT32 msg_type :8, 10057 pdev_id :8, 10058 enable :1, 10059 periodic_interval :8, 10060 reset_stats_bits :2, 10061 reserved0 :5; 10062 A_UINT32 vdev_id_lower_bitmask; 10063 A_UINT32 vdev_id_upper_bitmask; 10064 } POSTPACK; 10065 10066 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M 0xFF00 10067 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S 8 10068 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_GET(_var) \ 10069 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M) >> \ 10070 HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S) 10071 #define HTT_RX_VDEVS_TXRX_STATS_PDEV_ID_SET(_var, _val) \ 10072 do { \ 10073 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID, _val); \ 10074 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S)); \ 10075 } while (0) 10076 10077 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M 0x10000 10078 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S 16 10079 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_GET(_var) \ 10080 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M) >> \ 10081 HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S) 10082 #define HTT_RX_VDEVS_TXRX_STATS_ENABLE_SET(_var, _val) \ 10083 do { \ 10084 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_ENABLE, _val); \ 10085 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S)); \ 10086 } while (0) 10087 10088 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M 0x1FE0000 10089 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S 17 10090 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_GET(_var) \ 10091 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M) >> \ 10092 HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S) 10093 #define HTT_RX_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_SET(_var, _val) \ 10094 do { \ 10095 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL, _val); \ 10096 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S)); \ 10097 } while (0) 10098 10099 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M 0x6000000 10100 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S 25 10101 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_GET(_var) \ 10102 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M) >> \ 10103 HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S) 10104 #define HTT_RX_VDEVS_TXRX_STATS_RESET_STATS_BITS_SET(_var, _val) \ 10105 do { \ 10106 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS, _val); \ 10107 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S)); \ 10108 } while (0) 10109 10110 10111 /* 10112 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ 10113 * 10114 * @details 10115 * The SAWF_DEF_QUEUES_MAP_REQ message is sent by the host to link 10116 * the default MSDU queues for one of the TIDs within the specified peer 10117 * to the specified service class. 10118 * The TID is indirectly specified - each service class is associated 10119 * with a TID. All default MSDU queues for this peer-TID will be 10120 * linked to the service class in question. 10121 * 10122 * |31 16|15 8|7 0| 10123 * |------------------------------+--------------+--------------| 10124 * | peer ID | svc class ID | msg type | 10125 * |------------------------------------------------------------| 10126 * Header fields: 10127 * dword0 - b'7:0 - msg_type: This will be set to 10128 * 0x1c (HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ) 10129 * b'15:8 - service class ID 10130 * b'31:16 - peer ID 10131 */ 10132 10133 PREPACK struct htt_h2t_sawf_def_queues_map_req { 10134 A_UINT32 msg_type :8, 10135 svc_class_id :8, 10136 peer_id :16; 10137 } POSTPACK; 10138 10139 #define HTT_SAWF_DEF_QUEUES_MAP_REQ_BYTES 4 10140 10141 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M 0x0000FF00 10142 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S 8 10143 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_GET(_var) \ 10144 (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M) >> \ 10145 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S) 10146 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_SET(_var, _val) \ 10147 do { \ 10148 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID, _val); \ 10149 ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S));\ 10150 } while (0) 10151 10152 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M 0xFFFF0000 10153 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S 16 10154 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_GET(_var) \ 10155 (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M) >> \ 10156 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S) 10157 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_SET(_var, _val) \ 10158 do { \ 10159 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID, _val); \ 10160 ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S)); \ 10161 } while (0) 10162 10163 10164 /* 10165 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ 10166 * 10167 * @details 10168 * The SAWF_DEF_QUEUES_UNMAP_REQ message is sent by the host to 10169 * remove the linkage of the specified peer-TID's MSDU queues to 10170 * service classes. 10171 * 10172 * |31 16|15 8|7 0| 10173 * |------------------------------+--------------+--------------| 10174 * | peer ID | svc class ID | msg type | 10175 * |------------------------------------------------------------| 10176 * Header fields: 10177 * dword0 - b'7:0 - msg_type: This will be set to 10178 * 0x1d (HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ) 10179 * b'15:8 - service class ID 10180 * b'31:16 - peer ID 10181 * A HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD 10182 * value for peer ID indicates that the target should 10183 * apply the UNMAP_REQ to all peers. 10184 */ 10185 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD 0xff 10186 PREPACK struct htt_h2t_sawf_def_queues_unmap_req { 10187 A_UINT32 msg_type :8, 10188 svc_class_id :8, 10189 peer_id :16; 10190 } POSTPACK; 10191 10192 #define HTT_SAWF_DEF_QUEUES_UNMAP_REQ_BYTES 4 10193 10194 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M 0x0000FF00 10195 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S 8 10196 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_GET(word0) \ 10197 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M) >> \ 10198 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S) 10199 #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_SET(word0, _val) \ 10200 do { \ 10201 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID, _val); \ 10202 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S)); \ 10203 } while (0) 10204 10205 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M 0xFFFF0000 10206 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S 16 10207 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_GET(word0) \ 10208 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M) >> \ 10209 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S) 10210 #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_SET(word0, _val) \ 10211 do { \ 10212 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID, _val); \ 10213 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S)); \ 10214 } while (0) 10215 10216 /* 10217 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ 10218 * 10219 * @details 10220 * The SAWF_DEF_QUEUES_MAP_REPORT_REQ message is sent by the host to 10221 * request the target to report what service class the default MSDU queues 10222 * of the specified TIDs within the peer are linked to. 10223 * The target will respond with a SAWF_DEF_QUEUES_MAP_REPORT_CONF message 10224 * to report what service class (if any) the default MSDU queues for 10225 * each of the specified TIDs are linked to. 10226 * 10227 * |31 16|15 8|7 1| 0| 10228 * |------------------------------+--------------+--------------| 10229 * | peer ID | TID mask | msg type | 10230 * |------------------------------------------------------------| 10231 * | reserved |ETO| 10232 * |------------------------------------------------------------| 10233 * Header fields: 10234 * dword0 - b'7:0 - msg_type: This will be set to 10235 * 0x1e (HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ) 10236 * b'15:8 - TID mask 10237 * b'31:16 - peer ID 10238 * dword1 - b'0 - "Existing Tids Only" flag 10239 * If this flag is set, the DEF_QUEUES_MAP_REPORT_CONF 10240 * message generated by this REQ will only show the 10241 * mapping for TIDs that actually exist in the target's 10242 * peer object. 10243 * Any TIDs that are covered by a MAP_REQ but which 10244 * do not actually exist will be shown as being 10245 * unmapped (i.e. svc class ID 0xff). 10246 * If this flag is cleared, the MAP_REPORT_CONF message 10247 * will consider not only the mapping of TIDs currently 10248 * existing in the peer, but also the mapping that will 10249 * be applied for any TID objects created within this 10250 * peer in the future. 10251 * b'31:1 - reserved for future use 10252 */ 10253 10254 PREPACK struct htt_h2t_sawf_def_queues_map_report_req { 10255 A_UINT32 msg_type :8, 10256 tid_mask :8, 10257 peer_id :16; 10258 A_UINT32 existing_tids_only:1, 10259 reserved :31; 10260 } POSTPACK; 10261 10262 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_REQ_BYTES 8 10263 10264 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M 0x0000FF00 10265 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S 8 10266 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_GET(word0) \ 10267 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M) >> \ 10268 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S) 10269 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_SET(word0, _val) \ 10270 do { \ 10271 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK, _val); \ 10272 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S));\ 10273 } while (0) 10274 10275 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M 0xFFFF0000 10276 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S 16 10277 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_GET(word0) \ 10278 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M) >> \ 10279 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S) 10280 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_SET(word0, _val) \ 10281 do { \ 10282 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID, _val); \ 10283 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S)); \ 10284 } while (0) 10285 10286 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M 0x00000001 10287 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S 0 10288 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_GET(word1) \ 10289 (((word1) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M) >> \ 10290 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S) 10291 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_SET(word1, _val) \ 10292 do { \ 10293 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY, _val); \ 10294 ((word1) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S)); \ 10295 } while (0) 10296 10297 /** 10298 * @brief Format of shared memory between Host and Target 10299 * for UMAC recovery feature messaging. 10300 * @details 10301 * This is shared memory between Host and Target allocated 10302 * and used in chips where UMAC recovery feature is supported. 10303 * This shared memory is allocated per SOC level by Host since each 10304 * SOC's target Q6FW needs to communicate independently to the Host 10305 * through its own shared memory. 10306 * If target sets a bit in t2h_msg (provided it's valid bit offset) 10307 * then host interprets it as a new message from target. 10308 * Host clears that particular read bit in t2h_msg after each read 10309 * operation. It is vice versa for h2t_msg. At any given point 10310 * of time there is expected to be only one bit set 10311 * either in t2h_msg or h2t_msg (referring to valid bit offset). 10312 * 10313 * The message is interpreted as follows: 10314 * dword0 - b'0:31 - magic_num: Magic number for the shared memory region 10315 * added for debuggability purpose. 10316 * dword1 - b'0 - do_pre_reset 10317 * b'1 - do_post_reset_start 10318 * b'2 - do_post_reset_complete 10319 * b'3 - initiate_umac_recovery 10320 * b'4 - initiate_target_recovery_sync_using_umac 10321 * b'5:31 - rsvd_t2h 10322 * dword2 - b'0 - pre_reset_done 10323 * b'1 - post_reset_start_done 10324 * b'2 - post_reset_complete_done 10325 * b'3 - start_pre_reset (deprecated) 10326 * b'4:31 - rsvd_h2t 10327 */ 10328 PREPACK typedef struct { 10329 /** Magic number added for debuggability. */ 10330 A_UINT32 magic_num; 10331 union { 10332 /* 10333 * BIT [0] :- T2H msg to do pre-reset 10334 * BIT [1] :- T2H msg to do post-reset start 10335 * BIT [2] :- T2H msg to do post-reset complete 10336 * BIT [3] :- T2H msg to indicate to Host that 10337 * a trigger request for MLO UMAC Recovery 10338 * is received for UMAC hang. 10339 * BIT [4] :- T2H msg to indicate to Host that 10340 * a trigger request for MLO UMAC Recovery 10341 * is received for Mode-1 Target Recovery. 10342 * BIT [31 : 5] :- reserved 10343 */ 10344 A_UINT32 t2h_msg; 10345 struct { 10346 A_UINT32 10347 do_pre_reset: 1, /* BIT [0] */ 10348 do_post_reset_start: 1, /* BIT [1] */ 10349 do_post_reset_complete: 1, /* BIT [2] */ 10350 initiate_umac_recovery: 1, /* BIT [3] */ 10351 initiate_target_recovery_sync_using_umac: 1, /* BIT [4] */ 10352 rsvd_t2h: 27; /* BIT [31:5] */ 10353 }; 10354 }; 10355 10356 union { 10357 /* 10358 * BIT [0] :- H2T msg to send pre-reset done 10359 * BIT [1] :- H2T msg to send post-reset start done 10360 * BIT [2] :- H2T msg to send post-reset complete done 10361 * BIT [3] :- H2T msg to start pre-reset. This is deprecated. 10362 * BIT [31 : 4] :- reserved 10363 */ 10364 A_UINT32 h2t_msg; 10365 struct { 10366 A_UINT32 pre_reset_done : 1, /* BIT [0] */ 10367 post_reset_start_done : 1, /* BIT [1] */ 10368 post_reset_complete_done : 1, /* BIT [2] */ 10369 start_pre_reset : 1, /* BIT [3] */ 10370 rsvd_h2t : 28; /* BIT [31 : 4] */ 10371 }; 10372 }; 10373 } POSTPACK htt_umac_hang_recovery_msg_shmem_t; 10374 10375 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES \ 10376 (sizeof(htt_umac_hang_recovery_msg_shmem_t)) 10377 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DWORDS \ 10378 (HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES >> 2) 10379 10380 /* dword1 - b'0 - do_pre_reset */ 10381 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M 0x00000001 10382 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S 0 10383 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_GET(word1) \ 10384 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M) >> \ 10385 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S) 10386 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_SET(word1, _val) \ 10387 do { \ 10388 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET, _val); \ 10389 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S));\ 10390 } while (0) 10391 10392 /* dword1 - b'1 - do_post_reset_start */ 10393 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M 0x00000002 10394 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S 1 10395 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_GET(word1) \ 10396 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M) >> \ 10397 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S) 10398 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_SET(word1, _val) \ 10399 do { \ 10400 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START, _val); \ 10401 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S));\ 10402 } while (0) 10403 10404 /* dword1 - b'2 - do_post_reset_complete */ 10405 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M 0x00000004 10406 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S 2 10407 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_GET(word1) \ 10408 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M) >> \ 10409 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S) 10410 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_SET(word1, _val) \ 10411 do { \ 10412 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE, _val); \ 10413 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S));\ 10414 } while (0) 10415 10416 /* dword1 - b'3 - initiate_umac_recovery */ 10417 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008 10418 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3 10419 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \ 10420 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ 10421 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S) 10422 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \ 10423 do { \ 10424 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY, _val); \ 10425 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\ 10426 } while (0) 10427 10428 /* dword1 - b'4 - initiate_target_recovery_sync_using_umac */ 10429 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M 0x00000010 10430 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S 4 10431 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_GET(word1) \ 10432 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M) >> \ 10433 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S) 10434 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_SET(word1, _val) \ 10435 do { \ 10436 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC, _val); \ 10437 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S));\ 10438 } while (0) 10439 10440 /* dword2 - b'0 - pre_reset_done */ 10441 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001 10442 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0 10443 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_GET(word2) \ 10444 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M) >> \ 10445 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S) 10446 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_SET(word2, _val) \ 10447 do { \ 10448 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE, _val); \ 10449 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S));\ 10450 } while (0) 10451 10452 /* dword2 - b'1 - post_reset_start_done */ 10453 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M 0x00000002 10454 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S 1 10455 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_GET(word2) \ 10456 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M) >> \ 10457 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S) 10458 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_SET(word2, _val) \ 10459 do { \ 10460 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE, _val); \ 10461 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S));\ 10462 } while (0) 10463 10464 /* dword2 - b'2 - post_reset_complete_done */ 10465 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M 0x00000004 10466 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S 2 10467 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_GET(word2) \ 10468 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M) >> \ 10469 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S) 10470 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_SET(word2, _val) \ 10471 do { \ 10472 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE, _val); \ 10473 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S));\ 10474 } while (0) 10475 10476 /* dword2 - b'3 - start_pre_reset */ 10477 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M 0x00000008 10478 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S 3 10479 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_GET(word2) \ 10480 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M) >> \ 10481 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S) 10482 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_SET(word2, _val) \ 10483 do { \ 10484 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET, _val); \ 10485 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S));\ 10486 } while (0) 10487 10488 /** 10489 * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message 10490 * 10491 * @details 10492 * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message is sent 10493 * by the host to provide prerequisite info to target for the UMAC hang 10494 * recovery feature. 10495 * The info sent in this H2T message are T2H message method, H2T message 10496 * method, T2H MSI interrupt number and physical start address, size of 10497 * the shared memory (refers to the shared memory dedicated for messaging 10498 * between host and target when the DUT is in UMAC hang recovery mode). 10499 * This H2T message is expected to be only sent if the WMI service bit 10500 * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target. 10501 * 10502 * |31 16|15 12|11 8|7 0| 10503 * |-------------------------------+--------------+--------------+------------| 10504 * | reserved |h2t msg method|t2h msg method| msg_type | 10505 * |--------------------------------------------------------------------------| 10506 * | t2h msi interrupt number | 10507 * |--------------------------------------------------------------------------| 10508 * | shared memory area size | 10509 * |--------------------------------------------------------------------------| 10510 * | shared memory area physical address low | 10511 * |--------------------------------------------------------------------------| 10512 * | shared memory area physical address high | 10513 * |--------------------------------------------------------------------------| 10514 * 10515 * The message is interpreted as follows: 10516 * dword0 - b'0:7 - msg_type 10517 * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP) 10518 * b'8:11 - t2h_msg_method: indicates method to be used for 10519 * T2H communication in UMAC hang recovery mode. 10520 * Value zero indicates MSI interrupt (default method). 10521 * Refer to htt_umac_hang_recovery_msg_method enum. 10522 * b'12:15 - h2t_msg_method: indicates method to be used for 10523 * H2T communication in UMAC hang recovery mode. 10524 * Value zero indicates polling by target for this h2t msg 10525 * during UMAC hang recovery mode. 10526 * Refer to htt_umac_hang_recovery_msg_method enum. 10527 * b'16:31 - reserved. 10528 * dword1 - b'0:31 - t2h_msi_data: MSI data to be used for 10529 * T2H communication in UMAC hang recovery mode. 10530 * dword2 - b'0:31 - size: size of shared memory dedicated for messaging 10531 * only when in UMAC hang recovery mode. 10532 * This refers to size in bytes. 10533 * dword3 - b'0:31 - physical_address_lo: lower 32 bit physical address 10534 * of the shared memory dedicated for messaging only when 10535 * in UMAC hang recovery mode. 10536 * dword4 - b'0:31 - physical_address_hi: higher 32 bit physical address 10537 * of the shared memory dedicated for messaging only when 10538 * in UMAC hang recovery mode. 10539 */ 10540 10541 /* t2h_msg_method and h2t_msg_method */ 10542 enum htt_umac_hang_recovery_msg_method { 10543 htt_umac_hang_recovery_msg_t2h_msi_and_h2t_polling = 0, 10544 }; 10545 10546 PREPACK typedef struct { 10547 A_UINT32 msg_type : 8, 10548 t2h_msg_method : 4, 10549 h2t_msg_method : 4, 10550 reserved : 16; 10551 A_UINT32 t2h_msi_data; 10552 /* size bytes and physical address of shared memory. */ 10553 struct htt_h2t_host_paddr_size_entry_t msg_shared_mem; 10554 } POSTPACK htt_h2t_umac_hang_recovery_prerequisite_setup_t; 10555 10556 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES \ 10557 (sizeof(htt_h2t_umac_hang_recovery_prerequisite_setup_t)) 10558 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_DWORDS \ 10559 (HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES >> 2) 10560 10561 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M 0x00000F00 10562 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S 8 10563 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_GET(word0) \ 10564 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M) >> \ 10565 HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S) 10566 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_SET(word0, _val) \ 10567 do { \ 10568 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD, _val); \ 10569 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S));\ 10570 } while (0) 10571 10572 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M 0x0000F000 10573 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S 12 10574 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_GET(word0) \ 10575 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M) >> \ 10576 HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S) 10577 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_SET(word0, _val) \ 10578 do { \ 10579 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD, _val); \ 10580 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S));\ 10581 } while (0) 10582 10583 /** 10584 * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET message 10585 * 10586 * @details 10587 * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET is a SOC level 10588 * HTT message sent by the host to indicate that the target needs to start the 10589 * UMAC hang recovery feature from the point of pre-reset routine. 10590 * The purpose of this H2T message is to have host synchronize and trigger 10591 * UMAC recovery across all targets. 10592 * The info sent in this H2T message is the flag to indicate whether the 10593 * target needs to execute UMAC-recovery in context of the Initiator or 10594 * Non-Initiator. 10595 * This H2T message is expected to be sent as response to the 10596 * initiate_umac_recovery indication from the Initiator target attached to 10597 * this same host. 10598 * This H2T message is expected to be only sent if the WMI service bit 10599 * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target 10600 * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent 10601 * beforehand. 10602 * 10603 * |31 10|9|8|7 0| 10604 * |-----------------------------------------------------------| 10605 * | reserved |U|I| msg_type | 10606 * |-----------------------------------------------------------| 10607 * Where: 10608 * I = is_initiator 10609 * U = is_umac_hang 10610 * 10611 * The message is interpreted as follows: 10612 * dword0 - b'0:7 - msg_type 10613 * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET) 10614 * b'8 - is_initiator: indicates whether the target needs to 10615 * execute the UMAC-recovery in context of the Initiator or 10616 * Non-Initiator. 10617 * The value zero indicates this target is Non-Initiator. 10618 * b'9 - is_umac_hang: indicates whether MLO UMAC recovery 10619 * executed in context of UMAC hang or Target recovery. 10620 * b'10:31 - reserved. 10621 */ 10622 10623 PREPACK typedef struct { 10624 A_UINT32 msg_type : 8, 10625 is_initiator : 1, 10626 is_umac_hang : 1, 10627 reserved : 22; 10628 } POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t; 10629 10630 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \ 10631 (sizeof(htt_h2t_umac_hang_recovery_start_pre_reset_t)) 10632 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_DWORDS \ 10633 (HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES >> 2) 10634 10635 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M 0x00000100 10636 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S 8 10637 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_GET(word0) \ 10638 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M) >> \ 10639 HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S) 10640 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_SET(word0, _val) \ 10641 do { \ 10642 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR, _val); \ 10643 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\ 10644 } while (0) 10645 10646 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200 10647 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9 10648 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \ 10649 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \ 10650 HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S) 10651 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \ 10652 do { \ 10653 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \ 10654 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\ 10655 } while (0) 10656 10657 10658 /* 10659 * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message 10660 * 10661 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP 10662 * 10663 * @details 10664 * Host sends RX_CCE_SUPER_RULE setup message to target, in order to request, 10665 * install or uninstall rx cce super rules to match certain kind of packets 10666 * with specific parameters. Target sets up HW registers based on setup message 10667 * and always confirms back to Host. 10668 * 10669 * The message would appear as follows: 10670 * |31 24|23 16|15 8|7 0| 10671 * |-----------------+-----------------+-----------------+-----------------| 10672 * | reserved | operation | pdev_id | msg_type | 10673 * |-----------------------------------------------------------------------| 10674 * | cce_super_rule_param[0] | 10675 * |-----------------------------------------------------------------------| 10676 * | cce_super_rule_param[1] | 10677 * |-----------------------------------------------------------------------| 10678 * 10679 * The message is interpreted as follows: 10680 * dword0 - b'0:7 - msg_type: This will be set to 10681 * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP) 10682 * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is for 10683 * b'16:23 - operation: Identify operation to be taken, 10684 * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST 10685 * 1: HTT_RX_CCE_SUPER_RULE_INSTALL 10686 * 2: HTT_RX_CCE_SUPER_RULE_RELEASE 10687 * b'24:31 - reserved 10688 * dword1~10 - cce_super_rule_param[0]: 10689 * contains parameters used to setup RX_CCE_SUPER_RULE_0 10690 * dword11~20 - cce_super_rule_param[1]: 10691 * contains parameters used to setup RX_CCE_SUPER_RULE_1 10692 * 10693 * Each cce_super_rule_param structure would appear as follows: 10694 * |31 24|23 16|15 8|7 0| 10695 * |-----------------+-----------------+-----------------+-----------------| 10696 * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] | 10697 * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]| 10698 * |-----------------------------------------------------------------------| 10699 * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] | 10700 * |-----------------------------------------------------------------------| 10701 * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] | 10702 * |-----------------------------------------------------------------------| 10703 * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]| 10704 * |-----------------------------------------------------------------------| 10705 * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] | 10706 * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]| 10707 * |-----------------------------------------------------------------------| 10708 * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] | 10709 * |-----------------------------------------------------------------------| 10710 * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] | 10711 * |-----------------------------------------------------------------------| 10712 * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]| 10713 * |-----------------------------------------------------------------------| 10714 * | is_valid | l4_type | l3_type | 10715 * |-----------------------------------------------------------------------| 10716 * | l4_dst_port | l4_src_port | 10717 * |-----------------------------------------------------------------------| 10718 * 10719 * The cce_super_rule_param[0] structure is interpreted as follows: 10720 * dword1 - b'0:7 - src_ipv6_addr[0]: b'120:127 of source ipv6 address 10721 * (or src_ipv4_addr[0]: b'24:31 of source ipv4 address, 10722 * in case of ipv4) 10723 * b'8:15 - src_ipv6_addr[1]: b'112:119 of source ipv6 address 10724 * (or src_ipv4_addr[1]: b'16:23 of source ipv4 address, 10725 * in case of ipv4) 10726 * b'16:23 - src_ipv6_addr[2]: b'104:111 of source ipv6 address 10727 * (or src_ipv4_addr[2]: b'8:15 of source ipv4 address, 10728 * in case of ipv4) 10729 * b'24:31 - src_ipv6_addr[3]: b'96:103 of source ipv6 address 10730 * (or src_ipv4_addr[3]: b'0:7 of source ipv4 address, 10731 * in case of ipv4) 10732 * dword2 - b'0:7 - src_ipv6_addr[4]: b'88:95 of source ipv6 address 10733 * b'8:15 - src_ipv6_addr[5]: b'80:87 of source ipv6 address 10734 * b'16:23 - src_ipv6_addr[6]: b'72:79 of source ipv6 address 10735 * b'24:31 - src_ipv6_addr[7]: b'64:71 of source ipv6 address 10736 * dword3 - b'0:7 - src_ipv6_addr[8]: b'56:63 of source ipv6 address 10737 * b'8:15 - src_ipv6_addr[9]: b'48:55 of source ipv6 address 10738 * b'16:23 - src_ipv6_addr[10]: b'40:47 of source ipv6 address 10739 * b'24:31 - src_ipv6_addr[11]: b'32:39 of source ipv6 address 10740 * dword4 - b'0:7 - src_ipv6_addr[12]: b'24:31 of source ipv6 address 10741 * b'8:15 - src_ipv6_addr[13]: b'16:23 of source ipv6 address 10742 * b'16:23 - src_ipv6_addr[14]: b'8:15 of source ipv6 address 10743 * b'24:31 - src_ipv6_addr[15]: b'0:7 of source ipv6 address 10744 * dword5 - b'0:7 - dst_ipv6_addr[0]: b'120:127 of destination ipv6 address 10745 * (or dst_ipv4_addr[0]: b'24:31 of destination 10746 * ipv4 address, in case of ipv4) 10747 * b'8:15 - dst_ipv6_addr[1]: b'112:119 of destination ipv6 address 10748 * (or dst_ipv4_addr[1]: b'16:23 of destination 10749 * ipv4 address, in case of ipv4) 10750 * b'16:23 - dst_ipv6_addr[2]: b'104:111 of destination ipv6 address 10751 * (or dst_ipv4_addr[2]: b'8:15 of destination 10752 * ipv4 address, in case of ipv4) 10753 * b'24:31 - dst_ipv6_addr[3]: b'96:103 of destination ipv6 address 10754 * (or dst_ipv4_addr[3]: b'0:7 of destination 10755 * ipv4 address, in case of ipv4) 10756 * dword6 - b'0:7 - dst_ipv6_addr[4]: b'88:95 of destination ipv6 address 10757 * b'8:15 - dst_ipv6_addr[5]: b'80:87 of destination ipv6 address 10758 * b'16:23 - dst_ipv6_addr[6]: b'72:79 of destination ipv6 address 10759 * b'24:31 - dst_ipv6_addr[7]: b'64:71 of destination ipv6 address 10760 * dword7 - b'0:7 - dst_ipv6_addr[8]: b'56:63 of destination ipv6 address 10761 * b'8:15 - dst_ipv6_addr[9]: b'48:55 of destination ipv6 address 10762 * b'16:23 - dst_ipv6_addr[10]: b'40:47 of destination ipv6 address 10763 * b'24:31 - dst_ipv6_addr[11]: b'32:39 of destination ipv6 address 10764 * dword8 - b'0:7 - dst_ipv6_addr[12]: b'24:31 of destination ipv6 address 10765 * b'8:15 - dst_ipv6_addr[13]: b'16:23 of destination ipv6 address 10766 * b'16:23 - dst_ipv6_addr[14]: b'8:15 of destination ipv6 address 10767 * b'24:31 - dst_ipv6_addr[15]: b'0:7 of destination ipv6 address 10768 * dword9 - b'0:15 - l3_type: type of L3 protocol, indicating L3 protocol used 10769 * 0x0008: ipv4 10770 * 0xdd86: ipv6 10771 * b'16:23 - l4_type: type of L4 protocol, indicating L4 protocol used 10772 * 6: TCP 10773 * 17: UDP 10774 * b'24:31 - is_valid: indicate whether this parameter is valid 10775 * 0: invalid 10776 * 1: valid 10777 * dword10 - b'0:15 - l4_src_port: TCP/UDP source port field 10778 * b'16:31 - l4_dst_port: TCP/UDP destination port field 10779 * 10780 * The cce_super_rule_param[1] structure is similar. 10781 */ 10782 #define HTT_RX_CCE_SUPER_RULE_SETUP_NUM 2 10783 10784 enum htt_rx_cce_super_rule_setup_operation { 10785 HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST = 0, 10786 HTT_RX_CCE_SUPER_RULE_INSTALL, 10787 HTT_RX_CCE_SUPER_RULE_RELEASE, 10788 10789 /* All operation should be before this */ 10790 HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_OPERATION, 10791 }; 10792 10793 typedef struct { 10794 union { 10795 A_UINT8 src_ipv4_addr[4]; 10796 A_UINT8 src_ipv6_addr[16]; 10797 }; 10798 union { 10799 A_UINT8 dst_ipv4_addr[4]; 10800 A_UINT8 dst_ipv6_addr[16]; 10801 }; 10802 A_UINT32 l3_type: 16, 10803 l4_type: 8, 10804 is_valid: 8; 10805 A_UINT32 l4_src_port: 16, 10806 l4_dst_port: 16; 10807 } htt_rx_cce_super_rule_param_t; 10808 10809 PREPACK struct htt_rx_cce_super_rule_setup_t { 10810 A_UINT32 msg_type: 8, 10811 pdev_id: 8, 10812 operation: 8, 10813 reserved: 8; 10814 htt_rx_cce_super_rule_param_t 10815 cce_super_rule_param[HTT_RX_CCE_SUPER_RULE_SETUP_NUM]; 10816 } POSTPACK; 10817 10818 #define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \ 10819 (sizeof(struct htt_rx_cce_super_rule_setup_t)) 10820 10821 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00 10822 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S 8 10823 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \ 10824 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \ 10825 HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S) 10826 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \ 10827 do { \ 10828 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID, _val); \ 10829 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)); \ 10830 } while (0) 10831 10832 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 10833 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S 16 10834 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \ 10835 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M) >> \ 10836 HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S) 10837 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \ 10838 do { \ 10839 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION, _val); \ 10840 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)); \ 10841 } while (0) 10842 10843 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff 10844 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S 0 10845 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \ 10846 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \ 10847 HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S) 10848 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \ 10849 do { \ 10850 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE, _val); \ 10851 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)); \ 10852 } while (0) 10853 10854 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000 10855 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S 16 10856 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \ 10857 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \ 10858 HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S) 10859 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \ 10860 do { \ 10861 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE, _val); \ 10862 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)); \ 10863 } while (0) 10864 10865 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000 10866 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S 24 10867 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \ 10868 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M) >> \ 10869 HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S) 10870 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \ 10871 do { \ 10872 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID, _val); \ 10873 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)); \ 10874 } while (0) 10875 10876 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff 10877 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0 10878 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \ 10879 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \ 10880 HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S) 10881 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \ 10882 do { \ 10883 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \ 10884 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \ 10885 } while (0) 10886 10887 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000 10888 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16 10889 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \ 10890 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \ 10891 HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S) 10892 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \ 10893 do { \ 10894 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \ 10895 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \ 10896 } while (0) 10897 10898 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \ 10899 do { \ 10900 A_MEMCPY(_array, _ptr, 4); \ 10901 } while (0) 10902 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \ 10903 do { \ 10904 A_MEMCPY(_ptr, _array, 4); \ 10905 } while (0) 10906 10907 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \ 10908 do { \ 10909 A_MEMCPY(_array, _ptr, 16); \ 10910 } while (0) 10911 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \ 10912 do { \ 10913 A_MEMCPY(_ptr, _array, 16); \ 10914 } while (0) 10915 10916 10917 /* 10918 * @brief host -> target HTT TX_LCE_SUPER_RULE_SETUP message 10919 * 10920 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP 10921 * 10922 * @details 10923 * Host sends TX_SUPER_RULE setup message to target, in order to request, 10924 * install, or uninstall tx super rules to match certain kind of packets 10925 * with specific parameters. Target sets up HW registers based on setup 10926 * message and always confirms back to host (by sending a T2H 10927 * TX_LCE_SUPER_RULE_SETUP_DONE message). 10928 * 10929 * The message would appear as follows: 10930 * |31 24|23 16|15 8|7 0| 10931 * |-----------------+-----------------+-----------------+-----------------| 10932 * | reserved | operation | pdev_id | msg_type | 10933 * |-----------------------------------------------------------------------| 10934 * | tx_super_rule_param[0] | 10935 * |-----------------------------------------------------------------------| 10936 * | tx_super_rule_param[1] | 10937 * |-----------------------------------------------------------------------| 10938 * | tx_super_rule_param[2] | 10939 * |-----------------------------------------------------------------------| 10940 * 10941 * The message is interpreted as follows: 10942 * dword0 - b'0:7 - msg_type: This will be set to 10943 * 0x26 (HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP) 10944 * b'8:15 - pdev_id: Identify which pdev TX_SUPER_RULE is for 10945 * b'16:23 - operation: Identify operation to be taken, 10946 * 0: HTT_TX_LCE_SUPER_RULE_INSTALL 10947 * 1: HTT_TX_LCE_SUPER_RULE_RELEASE 10948 * b'24:31 - reserved 10949 * dword1~10 - tx_super_rule_param[0]: 10950 * contains parameters used to setup TX_SUPER_RULE_0 10951 * dword11~20 - tx_super_rule_param[1]: 10952 * contains parameters used to setup TX_SUPER_RULE_1 10953 * dword21~30 - tx_super_rule_param[2]: 10954 * contains parameters used to setup TX_SUPER_RULE_2 10955 * 10956 * Each tx_super_rule_param structure would appear as follows: 10957 * |31 24|23 16|15 8|7 0| 10958 * |-----------------+-----------------+-----------------+-----------------| 10959 * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] | 10960 * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]| 10961 * |-----------------------------------------------------------------------| 10962 * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] | 10963 * |-----------------------------------------------------------------------| 10964 * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] | 10965 * |-----------------------------------------------------------------------| 10966 * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]| 10967 * |-----------------------------------------------------------------------| 10968 * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] | 10969 * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]| 10970 * |-----------------------------------------------------------------------| 10971 * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] | 10972 * |-----------------------------------------------------------------------| 10973 * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] | 10974 * |-----------------------------------------------------------------------| 10975 * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]| 10976 * |-----------------------------------------------------------------------| 10977 * | is_valid | l4_type | l3_type | 10978 * |-----------------------------------------------------------------------| 10979 * | l4_dst_port | l4_src_port | 10980 * |-----------------------------------------------------------------------| 10981 * Where l3_type is 802.3 EtherType, l4_type is IANA IP protocol type. 10982 * 10983 * The tx_super_rule_param[1] structure is similar. 10984 * The tx_super_rule_param[2] structure is similar. 10985 */ 10986 #define HTT_TX_LCE_SUPER_RULE_SETUP_NUM 3 10987 10988 enum htt_tx_lce_super_rule_setup_operation { 10989 HTT_TX_LCE_SUPER_RULE_INSTALL = 0, 10990 HTT_TX_LCE_SUPER_RULE_RELEASE, 10991 10992 /* All operation should be before this */ 10993 HTT_TX_LCE_SUPER_RULE_SETUP_INVALID_OPERATION, 10994 }; 10995 10996 typedef struct { 10997 union { 10998 A_UINT8 src_ipv4_addr[4]; 10999 A_UINT8 src_ipv6_addr[16]; 11000 }; 11001 union { 11002 A_UINT8 dst_ipv4_addr[4]; 11003 A_UINT8 dst_ipv6_addr[16]; 11004 }; 11005 A_UINT32 l3_type: 16, 11006 l4_type: 8, 11007 is_valid: 8; 11008 A_UINT32 l4_src_port: 16, 11009 l4_dst_port: 16; 11010 } htt_tx_lce_super_rule_param_t; 11011 11012 PREPACK struct htt_tx_lce_super_rule_setup_t { 11013 A_UINT32 msg_type: 8, 11014 pdev_id: 8, 11015 operation: 8, /* htt_tx_lce_super_rule_setup_operation */ 11016 reserved: 8; 11017 htt_tx_lce_super_rule_param_t 11018 lce_super_rule_param[HTT_TX_LCE_SUPER_RULE_SETUP_NUM]; 11019 } POSTPACK; 11020 11021 #define HTT_TX_LCE_SUPER_RULE_SETUP_SZ (sizeof(struct htt_tx_lce_super_rule_setup_t)) 11022 11023 #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00 11024 #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_S 8 11025 #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \ 11026 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \ 11027 HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_S) 11028 11029 #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \ 11030 do { \ 11031 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID, _val); \ 11032 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_S)); \ 11033 } while (0) 11034 11035 #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 11036 #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_S 16 11037 #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \ 11038 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_M) >> \ 11039 HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_S) 11040 #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \ 11041 do { \ 11042 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION, _val); \ 11043 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_S)); \ 11044 } while (0) 11045 #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff 11046 #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_S 0 11047 #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \ 11048 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \ 11049 HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_S) 11050 #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \ 11051 do { \ 11052 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE, _val); \ 11053 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_S)); \ 11054 } while (0) 11055 11056 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000 11057 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_S 16 11058 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \ 11059 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \ 11060 HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_S) 11061 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \ 11062 do { \ 11063 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE, _val); \ 11064 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_S)); \ 11065 } while (0) 11066 11067 #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000 11068 #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_S 24 11069 #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \ 11070 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_M) >> \ 11071 HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_S) 11072 #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \ 11073 do { \ 11074 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID, _val); \ 11075 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_S)); \ 11076 } while (0) 11077 11078 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff 11079 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0 11080 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \ 11081 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \ 11082 HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_S) 11083 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \ 11084 do { \ 11085 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \ 11086 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \ 11087 } while (0) 11088 11089 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000 11090 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16 11091 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \ 11092 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \ 11093 HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_S) 11094 #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \ 11095 do { \ 11096 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \ 11097 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \ 11098 } while (0) 11099 11100 #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \ 11101 do { \ 11102 A_MEMCPY(_array, _ptr, 4); \ 11103 } while (0) 11104 #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \ 11105 do { \ 11106 A_MEMCPY(_ptr, _array, 4); \ 11107 } while (0) 11108 #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \ 11109 do { \ 11110 A_MEMCPY(_array, _ptr, 16); \ 11111 } while (0) 11112 #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \ 11113 do { \ 11114 A_MEMCPY(_ptr, _array, 16); \ 11115 } while (0) 11116 11117 11118 /** 11119 * htt_h2t_primary_link_peer_status_type - 11120 * Unique number for each status or reasons 11121 * The status reasons can go up to 255 max 11122 */ 11123 enum htt_h2t_primary_link_peer_status_type { 11124 /* Host Primary Link Peer migration Success */ 11125 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_OK = 0, 11126 11127 11128 /* keep this last */ 11129 /* Host Primary Link Peer migration Fail */ 11130 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_FAIL = 254, 11131 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_NUM_STATUS = 255 11132 }; 11133 11134 11135 /** 11136 * @brief host -> Primary peer migration completion message from host 11137 * 11138 * MSG_TYPE => HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP 11139 * 11140 * @details 11141 * HTT_H2T_MSG_TYPE_PRIMARY_PEER_MIGRATE_RESP message is sent by host to 11142 * target Confirming that primary link peer migration has completed, 11143 * in response to a HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND 11144 * message from the target. 11145 * 11146 * The message would appear as follows: 11147 * 11148 * |31 25|24|23 16|15 12|11 8|7 0| 11149 * |----------------------------+----------+---------+--------------| 11150 * | vdev ID | pdev ID | chip ID | msg type | 11151 * |----------------------------+----------+---------+--------------| 11152 * | ML peer ID | SW peer ID | 11153 * |------------+--+------------+--------------------+--------------| 11154 * | reserved |SV| src_info | status | 11155 * |------------+--+---------------------------------+--------------| 11156 * Where: 11157 * SV = src_info_valid flag 11158 * 11159 * The message is interpreted as follows: 11160 * dword0 - b'0:7 - msg_type: This will be set to 0x24 11161 * (HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP) 11162 * b'8:11 - chip_id: Indicate which chip has been chosen as primary 11163 * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen 11164 * as primary 11165 * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen 11166 * as primary 11167 * 11168 * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer 11169 * chosen as primary 11170 * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the 11171 * primary peer belongs. 11172 * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration 11173 * b'8:23 - src_info: Indicates New Virtual port number through 11174 * which Rx Pipe connects to the correct PPE. 11175 * b'24 - src_info_valid: Indicates src_info is valid. 11176 */ 11177 11178 typedef struct { 11179 A_UINT32 msg_type: 8, /* bits 7:0 */ 11180 chip_id: 4, /* bits 11:8 */ 11181 pdev_id: 4, /* bits 15:12 */ 11182 vdev_id: 16; /* bits 31:16 */ 11183 A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ 11184 ml_peer_id: 16; /* bits 31:16 */ 11185 A_UINT32 status: 8, /* bits 7:0 */ 11186 src_info: 16, /* bits 23:8 */ 11187 src_info_valid: 1, /* bit 24 */ 11188 reserved: 7; /* bits 31:25 */ 11189 } htt_h2t_primary_link_peer_migrate_resp_t; 11190 11191 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 11192 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 11193 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ 11194 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ 11195 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) 11196 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ 11197 do { \ 11198 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ 11199 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ 11200 } while (0) 11201 11202 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 11203 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 11204 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ 11205 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ 11206 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) 11207 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ 11208 do { \ 11209 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ 11210 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ 11211 } while (0) 11212 11213 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 11214 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 11215 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ 11216 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ 11217 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) 11218 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ 11219 do { \ 11220 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ 11221 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ 11222 } while (0) 11223 11224 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF 11225 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 11226 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ 11227 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ 11228 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) 11229 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ 11230 do { \ 11231 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ 11232 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ 11233 } while (0) 11234 11235 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 11236 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 11237 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ 11238 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ 11239 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) 11240 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ 11241 do { \ 11242 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ 11243 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ 11244 } while (0) 11245 11246 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M 0x000000FF 11247 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S 0 11248 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_GET(_var) \ 11249 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M) >> \ 11250 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S) 11251 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_SET(_var, _val) \ 11252 do { \ 11253 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS, _val); \ 11254 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\ 11255 } while (0) 11256 11257 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00 11258 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8 11259 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \ 11260 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \ 11261 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S) 11262 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \ 11263 do { \ 11264 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \ 11265 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\ 11266 } while (0) 11267 11268 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000 11269 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24 11270 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \ 11271 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \ 11272 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S) 11273 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \ 11274 do { \ 11275 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \ 11276 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\ 11277 } while (0) 11278 11279 11280 /** 11281 * @brief host -> tgt msg to configure params for PPDU tx latency stats report 11282 * 11283 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG 11284 * 11285 * @details 11286 * HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to 11287 * configure the parameters needed for FW to report PPDU tx latency stats 11288 * for latency prediction in user space. 11289 * 11290 * The message would appear as follows: 11291 * |31 28|27 12|11|10 8|7 0| 11292 * |-----------+-------------------+--+-------+--------------| 11293 * |granularity| periodic interval | E|vdev ID| msg type | 11294 * |-----------+-------------------+--+-------+--------------| 11295 * Where: E = enable 11296 * 11297 * The message is interpreted as follows: 11298 * dword0 - b'0:7 - msg_type: This will be set to 0x25 11299 * (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG) 11300 * b'8:10 - vdev_id: Indicate which vdev is configuration is for 11301 * b'11 - enable: Indicate this message is to enable/disable 11302 * PPDU latency report from FW 11303 * b'12:27 - periodic_interval: Indicate the report interval in MS 11304 * b'28:31 - granularity: Indicate the granularity of the latency 11305 * stats report, in ms 11306 */ 11307 11308 /* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */ 11309 PREPACK struct htt_h2t_tx_latency_stats_cfg { 11310 A_UINT32 msg_type :8, 11311 vdev_id :3, 11312 enable :1, 11313 periodic_interval :16, 11314 granularity :4; 11315 } POSTPACK; 11316 11317 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700 11318 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8 11319 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \ 11320 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \ 11321 HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S) 11322 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \ 11323 do { \ 11324 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \ 11325 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \ 11326 } while (0) 11327 11328 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800 11329 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11 11330 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \ 11331 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \ 11332 HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S) 11333 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \ 11334 do { \ 11335 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \ 11336 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \ 11337 } while (0) 11338 11339 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000 11340 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12 11341 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \ 11342 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \ 11343 HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S) 11344 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \ 11345 do { \ 11346 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \ 11347 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \ 11348 } while (0) 11349 11350 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000 11351 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28 11352 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \ 11353 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \ 11354 HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S) 11355 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \ 11356 do { \ 11357 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \ 11358 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \ 11359 } while (0) 11360 11361 11362 /** 11363 * @brief host -> tgt msg to reconfigure params for a MSDU queue 11364 * 11365 * MSG_TYPE => HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ 11366 * 11367 * @details 11368 * HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ message is sent by the host to 11369 * update the configuration of the identified MSDU. 11370 * This message supports the following MSDU queue reconfigurations: 11371 * 1. Deactivating or reactivating the MSDU queue. 11372 * 2. Moving the MSDU queue from its current service class to a 11373 * different service class. 11374 * The new service class needs to be within the same TID as the 11375 * current service class. 11376 * This msg overlaps with the HTT_H2T_SAWF_DEF_QUEUES_[MAP,UNMAP]_REQ 11377 * messages, but those only apply to the default MSDU queues within 11378 * a peer-TID, while this message applies only to a single MSDU queue, 11379 * and that MSDU queue can be a user-defined queue or a default queue. 11380 * Also, the concurrent combination of reconfigurations 1+2 is supported. 11381 * 11382 * The message format is as follows: 11383 * |31 24|23 9|8|7 0| 11384 * |--------------------------------------------------------------| 11385 * | tgt_opaque_msduq_id | msg type | 11386 * |--------------------------------------------------------------| 11387 * | request_cookie | reserved |D| svc_class_id | 11388 * |--------------------------------------------------------------| 11389 * Where: D = deactivate flag 11390 * 11391 * The message is interpreted as follows: 11392 * dword0 - b'0:7 - msg_type: This will be set to 0x27 11393 * (HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ) 11394 * b'8:31 - tgt_opaque_msduq_id: tx flow number that uniquely 11395 * identifies the MSDU queue 11396 * dword1 - b'0:7 - svc_class_id: ID of the SAWF service class to which 11397 * the MSDU queue should be associated. 11398 * On reactivate requests, svc_class_id may be set to the 11399 * same service class ID as before the deactivate or it may 11400 * be set to a different service class ID. 11401 * b'8:8 - deactivate: Whether the MSDU queue should be deactivated 11402 * or reactivated (refer to HTT_MSDUQ_DEACTIVATE_E) 11403 * b'9:23 - reserved 11404 * b'31:24 - request_cookie: Identifier for FW to use in the 11405 * completion indication (T2H SDWF_MSDU_CFG_IND) to call 11406 * out this specific request. The host shall avoid using 11407 * a value of 0xFF (COOKIE_INVALID) here, so that a 11408 * 0xFF / COOKIE_INVALID value can be used in any T2H 11409 * SDWF_MSDUQ_CFG_IND messages that the target sends 11410 * autonomously rather than in response to a H2T 11411 * SDWF_MSDUQ_RECFG_REQ. 11412 */ 11413 11414 /* HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ */ 11415 typedef enum { 11416 HTT_MSDUQ_REACTIVATE = 0, 11417 HTT_MSDUQ_DEACTIVATE = 1, 11418 } HTT_MSDUQ_DEACTIVATE_E; 11419 11420 PREPACK struct htt_h2t_sdwf_msduq_recfg_req { 11421 A_UINT32 msg_type :8, /* bits 7:0 */ 11422 tgt_opaque_msduq_id :24; /* bits 31:8 */ 11423 A_UINT32 svc_class_id :8, /* bits 7:0 */ 11424 deactivate :1, /* bits 8:8 */ 11425 reserved :15, /* bits 23:9 */ 11426 request_cookie :8; /* bits 31:24 */ 11427 } POSTPACK; 11428 11429 #define HTT_MSDUQ_CFG_REG_COOKIE_INVALID 0xFF 11430 11431 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_M 0xFFFFFF00 11432 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_S 8 11433 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_GET(_var) \ 11434 (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_M) >> \ 11435 HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_S) 11436 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_SET(_var, _val) \ 11437 do { \ 11438 HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID, _val); \ 11439 ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_S)); \ 11440 } while (0) 11441 11442 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_M 0x000000FF 11443 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_S 0 11444 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_GET(_var) \ 11445 (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_M) >> \ 11446 HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_S) 11447 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_SET(_var, _val) \ 11448 do { \ 11449 HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID, _val); \ 11450 ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_S)); \ 11451 } while (0) 11452 11453 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_M 0x00000100 11454 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_S 8 11455 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_GET(_var) \ 11456 (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_M) >> \ 11457 HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_S) 11458 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_SET(_var, _val) \ 11459 do { \ 11460 HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE, _val); \ 11461 ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_S)); \ 11462 } while (0) 11463 11464 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_M 0xFF000000 11465 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_S 24 11466 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_GET(_var) \ 11467 (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_M) >> \ 11468 HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_S) 11469 #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_SET(_var, _val) \ 11470 do { \ 11471 HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE, _val); \ 11472 ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_S)); \ 11473 } while (0) 11474 11475 11476 11477 /*=== target -> host messages ===============================================*/ 11478 11479 11480 enum htt_t2h_msg_type { 11481 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 11482 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 11483 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 11484 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 11485 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 11486 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 11487 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 11488 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 11489 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 11490 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 11491 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 11492 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 11493 DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* no longer used */ 11494 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 11495 HTT_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 11496 /* only used for HL, add HTT MSG for HTT CREDIT update */ 11497 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 11498 HTT_T2H_MSG_TYPE_RX_PN_IND = 0x10, 11499 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 11500 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 11501 /* 0x13 is reserved for RX_RING_LOW_IND (RX Full reordering related) */ 11502 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 11503 HTT_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 11504 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 11505 HTT_T2H_MSG_TYPE_RATE_REPORT = 0x17, 11506 HTT_T2H_MSG_TYPE_FLOW_POOL_MAP = 0x18, 11507 HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP = 0x19, 11508 HTT_T2H_MSG_TYPE_SRING_SETUP_DONE = 0x1a, 11509 HTT_T2H_MSG_TYPE_MAP_FLOW_INFO = 0x1b, 11510 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 11511 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 11512 HTT_T2H_MSG_TYPE_PEER_MAP_V2 = 0x1e, 11513 HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 = 0x1f, 11514 HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND = 0x20, 11515 HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE = 0x21, 11516 HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND = 0x22, 11517 HTT_T2H_MSG_TYPE_PEER_STATS_IND = 0x23, 11518 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 11519 /* TX_OFFLOAD_DELIVER_IND: 11520 * Forward the target's locally-generated packets to the host, 11521 * to provide to the monitor mode interface. 11522 */ 11523 HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND = 0x25, 11524 HTT_T2H_MSG_TYPE_CHAN_CALDATA = 0x26, 11525 HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND = 0x27, 11526 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 11527 HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP = 0x29, 11528 HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP = 0x2a, 11529 HTT_T2H_MSG_TYPE_PEER_MAP_V3 = 0x2b, 11530 HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND = 0x2c, 11531 HTT_T2H_MSG_TYPE_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, 11532 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, /* alias */ 11533 HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND = 0x2e, 11534 HTT_T2H_SAWF_MSDUQ_INFO_IND = 0x2e, /* alias */ 11535 HTT_T2H_MSG_TYPE_STREAMING_STATS_IND = 0x2f, 11536 HTT_T2H_PPDU_ID_FMT_IND = 0x30, 11537 HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31, 11538 HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, 11539 HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, 11540 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, /* DEPRECATED */ 11541 HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, 11542 HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, 11543 HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, 11544 HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, 11545 HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39, 11546 HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a, 11547 HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE = 0x3b, 11548 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND = 0x3c, 11549 11550 11551 HTT_T2H_MSG_TYPE_TEST, 11552 /* keep this last */ 11553 HTT_T2H_NUM_MSGS 11554 }; 11555 11556 /* 11557 * HTT target to host message type - 11558 * stored in bits 7:0 of the first word of the message 11559 */ 11560 #define HTT_T2H_MSG_TYPE_M 0xff 11561 #define HTT_T2H_MSG_TYPE_S 0 11562 11563 #define HTT_T2H_MSG_TYPE_SET(word, msg_type) \ 11564 do { \ 11565 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE, msg_type); \ 11566 (word) |= ((msg_type) << HTT_T2H_MSG_TYPE_S); \ 11567 } while (0) 11568 #define HTT_T2H_MSG_TYPE_GET(word) \ 11569 (((word) & HTT_T2H_MSG_TYPE_M) >> HTT_T2H_MSG_TYPE_S) 11570 11571 /** 11572 * @brief target -> host version number confirmation message definition 11573 * 11574 * MSG_TYPE => HTT_T2H_MSG_TYPE_VERSION_CONF 11575 * 11576 * |31 24|23 16|15 8|7 0| 11577 * |----------------+----------------+----------------+----------------| 11578 * | reserved | major number | minor number | msg type | 11579 * |-------------------------------------------------------------------| 11580 * : option request TLV (optional) | 11581 * :...................................................................: 11582 * 11583 * The VER_CONF message may consist of a single 4-byte word, or may be 11584 * extended with TLVs that specify HTT options selected by the target. 11585 * The following option TLVs may be appended to the VER_CONF message: 11586 * - LL_BUS_ADDR_SIZE 11587 * - HL_SUPPRESS_TX_COMPL_IND 11588 * - MAX_TX_QUEUE_GROUPS 11589 * These TLVs may appear in an arbitrary order. Any number of these TLVs 11590 * may be appended to the VER_CONF message (but only one TLV of each type). 11591 * 11592 * Header fields: 11593 * - MSG_TYPE 11594 * Bits 7:0 11595 * Purpose: identifies this as a version number confirmation message 11596 * Value: 0x0 (HTT_T2H_MSG_TYPE_VERSION_CONF) 11597 * - VER_MINOR 11598 * Bits 15:8 11599 * Purpose: Specify the minor number of the HTT message library version 11600 * in use by the target firmware. 11601 * The minor number specifies the specific revision within a range 11602 * of fundamentally compatible HTT message definition revisions. 11603 * Compatible revisions involve adding new messages or perhaps 11604 * adding new fields to existing messages, in a backwards-compatible 11605 * manner. 11606 * Incompatible revisions involve changing the message type values, 11607 * or redefining existing messages. 11608 * Value: minor number 11609 * - VER_MAJOR 11610 * Bits 15:8 11611 * Purpose: Specify the major number of the HTT message library version 11612 * in use by the target firmware. 11613 * The major number specifies the family of minor revisions that are 11614 * fundamentally compatible with each other, but not with prior or 11615 * later families. 11616 * Value: major number 11617 */ 11618 11619 #define HTT_VER_CONF_MINOR_M 0x0000ff00 11620 #define HTT_VER_CONF_MINOR_S 8 11621 #define HTT_VER_CONF_MAJOR_M 0x00ff0000 11622 #define HTT_VER_CONF_MAJOR_S 16 11623 11624 11625 #define HTT_VER_CONF_MINOR_SET(word, value) \ 11626 do { \ 11627 HTT_CHECK_SET_VAL(HTT_VER_CONF_MINOR, value); \ 11628 (word) |= (value) << HTT_VER_CONF_MINOR_S; \ 11629 } while (0) 11630 #define HTT_VER_CONF_MINOR_GET(word) \ 11631 (((word) & HTT_VER_CONF_MINOR_M) >> HTT_VER_CONF_MINOR_S) 11632 11633 #define HTT_VER_CONF_MAJOR_SET(word, value) \ 11634 do { \ 11635 HTT_CHECK_SET_VAL(HTT_VER_CONF_MAJOR, value); \ 11636 (word) |= (value) << HTT_VER_CONF_MAJOR_S; \ 11637 } while (0) 11638 #define HTT_VER_CONF_MAJOR_GET(word) \ 11639 (((word) & HTT_VER_CONF_MAJOR_M) >> HTT_VER_CONF_MAJOR_S) 11640 11641 11642 #define HTT_VER_CONF_BYTES 4 11643 11644 11645 /** 11646 * @brief - target -> host HTT Rx In order indication message 11647 * 11648 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND 11649 * 11650 * @details 11651 * 11652 * |31 24|23 |15|14|13|12|11|10|9|8|7|6|5|4 0| 11653 * |----------------+-------------------+---------------------+---------------| 11654 * | peer ID | P| F| O| ext TID | msg type | 11655 * |--------------------------------------------------------------------------| 11656 * | MSDU count | Reserved | vdev id | 11657 * |--------------------------------------------------------------------------| 11658 * | MSDU 0 bus address (bits 31:0) | 11659 #if HTT_PADDR64 11660 * | MSDU 0 bus address (bits 63:32) | 11661 #endif 11662 * |--------------------------------------------------------------------------| 11663 * | MSDU info | MSDU 0 FW Desc | MSDU 0 Length | 11664 * |--------------------------------------------------------------------------| 11665 * | MSDU 1 bus address (bits 31:0) | 11666 #if HTT_PADDR64 11667 * | MSDU 1 bus address (bits 63:32) | 11668 #endif 11669 * |--------------------------------------------------------------------------| 11670 * | MSDU info | MSDU 1 FW Desc | MSDU 1 Length | 11671 * |--------------------------------------------------------------------------| 11672 */ 11673 11674 11675 /** @brief - MSDU info byte for TCP_CHECKSUM_OFFLOAD use 11676 * 11677 * @details 11678 * bits 11679 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 11680 * |-----+----+-------+--------+--------+---------+---------+-----------| 11681 * | reserved | is IP | is UDP | is TCP | is IPv6 |IP chksum| TCP/UDP | 11682 * | | frag | | | | fail |chksum fail| 11683 * |-----+----+-------+--------+--------+---------+---------+-----------| 11684 * (see fw_rx_msdu_info def in wal_rx_desc.h) 11685 */ 11686 11687 struct htt_rx_in_ord_paddr_ind_hdr_t 11688 { 11689 A_UINT32 /* word 0 */ 11690 msg_type: 8, 11691 ext_tid: 5, 11692 offload: 1, 11693 frag: 1, 11694 pktlog: 1, /* tell host whether to store MSDUs referenced in this message in pktlog */ 11695 peer_id: 16; 11696 11697 A_UINT32 /* word 1 */ 11698 vap_id: 8, 11699 /* NOTE: 11700 * This reserved_1 field is not truly reserved - certain targets use 11701 * this field internally to store debug information, and do not zero 11702 * out the contents of the field before uploading the message to the 11703 * host. Thus, any host-target communication supported by this field 11704 * is limited to using values that are never used by the debug 11705 * information stored by certain targets in the reserved_1 field. 11706 * In particular, the targets in question don't use the value 0x3 11707 * within bits 7:6 of this field (i.e. bits 15:14 of the A_UINT32), 11708 * so this previously-unused value within these bits is available to 11709 * use as the host / target PKT_CAPTURE_MODE flag. 11710 */ 11711 reserved_1: 8, /* reserved_1a: 6, pkt_capture_mode: 2, */ 11712 /* if pkt_capture_mode == 0x3, host should 11713 * send rx frames to monitor mode interface 11714 */ 11715 msdu_cnt: 16; 11716 }; 11717 11718 struct htt_rx_in_ord_paddr_ind_msdu32_t 11719 { 11720 A_UINT32 dma_addr; 11721 A_UINT32 11722 length: 16, 11723 fw_desc: 8, 11724 msdu_info:8; 11725 }; 11726 struct htt_rx_in_ord_paddr_ind_msdu64_t 11727 { 11728 A_UINT32 dma_addr_lo; 11729 A_UINT32 dma_addr_hi; 11730 A_UINT32 11731 length: 16, 11732 fw_desc: 8, 11733 msdu_info:8; 11734 }; 11735 #if HTT_PADDR64 11736 #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu64_t 11737 #else 11738 #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu32_t 11739 #endif 11740 11741 11742 #define HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_hdr_t)) 11743 #define HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS (HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES >> 2) 11744 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTE_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES 11745 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORD_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS 11746 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu64_t)) 11747 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_64 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 >> 2) 11748 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu32_t)) 11749 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_32 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 >> 2) 11750 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_msdu_t)) 11751 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES >> 2) 11752 11753 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M 0x00001f00 11754 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S 8 11755 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M 0x00002000 11756 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S 13 11757 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_M 0x00004000 11758 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_S 14 11759 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M 0x00008000 11760 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S 15 11761 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M 0xffff0000 11762 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S 16 11763 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M 0x000000ff 11764 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S 0 11765 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M 0x0000c000 11766 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S 14 11767 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M 0xffff0000 11768 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S 16 11769 /* for systems using 64-bit format for bus addresses */ 11770 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M 0xffffffff 11771 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S 0 11772 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M 0xffffffff 11773 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S 0 11774 /* for systems using 32-bit format for bus addresses */ 11775 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_M 0xffffffff 11776 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_S 0 11777 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M 0x0000ffff 11778 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S 0 11779 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M 0x00ff0000 11780 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S 16 11781 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M 0xff000000 11782 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S 24 11783 11784 11785 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_SET(word, value) \ 11786 do { \ 11787 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_EXT_TID, value); \ 11788 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S; \ 11789 } while (0) 11790 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_GET(word) \ 11791 (((word) & HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M) >> HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S) 11792 11793 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_SET(word, value) \ 11794 do { \ 11795 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PEER_ID, value); \ 11796 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S; \ 11797 } while (0) 11798 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_GET(word) \ 11799 (((word) & HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S) 11800 11801 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_SET(word, value) \ 11802 do { \ 11803 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_VAP_ID, value); \ 11804 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S; \ 11805 } while (0) 11806 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \ 11807 (((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S) 11808 11809 /* 11810 * If the PKT_CAPTURE_MODE flags value is MONITOR (0x3), the host should 11811 * deliver the rx frames to the monitor mode interface. 11812 * The HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET macro 11813 * sets the PKT_CAPTURE_MODE flags value to MONITOR, and the 11814 * HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET macro 11815 * checks whether the PKT_CAPTURE_MODE flags value is MONITOR. 11816 */ 11817 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR 0x3 11818 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET(word) \ 11819 do { \ 11820 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE, HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR); \ 11821 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S; \ 11822 } while (0) 11823 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET(word) \ 11824 ((((word) & HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M) >> HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S) == \ 11825 HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR) 11826 11827 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \ 11828 do { \ 11829 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \ 11830 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S; \ 11831 } while (0) 11832 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_GET(word) \ 11833 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S) 11834 11835 /* for systems using 64-bit format for bus addresses */ 11836 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_SET(word, value) \ 11837 do { \ 11838 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_HI, value); \ 11839 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S; \ 11840 } while (0) 11841 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_GET(word) \ 11842 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S) 11843 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_SET(word, value) \ 11844 do { \ 11845 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_LO, value); \ 11846 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S; \ 11847 } while (0) 11848 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_GET(word) \ 11849 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S) 11850 11851 /* for systems using 32-bit format for bus addresses */ 11852 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_SET(word, value) \ 11853 do { \ 11854 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR, value); \ 11855 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_S; \ 11856 } while (0) 11857 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_GET(word) \ 11858 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_S) 11859 11860 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_SET(word, value) \ 11861 do { \ 11862 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN, value); \ 11863 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S; \ 11864 } while (0) 11865 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_GET(word) \ 11866 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S) 11867 11868 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_SET(word, value) \ 11869 do { \ 11870 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_FW_DESC, value); \ 11871 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S; \ 11872 } while (0) 11873 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_GET(word) \ 11874 (((word) & HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M) >> HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S) 11875 11876 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_SET(word, value) \ 11877 do { \ 11878 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO, value); \ 11879 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S; \ 11880 } while (0) 11881 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_GET(word) \ 11882 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S) 11883 11884 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_SET(word, value) \ 11885 do { \ 11886 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_OFFLOAD, value); \ 11887 (word) |= (value) << HTT_RX_IN_ORD_IND_OFFLOAD_S; \ 11888 } while (0) 11889 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_GET(word) \ 11890 (((word) & HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M) >> HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S) 11891 11892 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_SET(word, value) \ 11893 do { \ 11894 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_FRAG, value); \ 11895 (word) |= (value) << HTT_RX_IN_ORD_IND_FRAG_S; \ 11896 } while (0) 11897 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_GET(word) \ 11898 (((word) & HTT_RX_IN_ORD_PADDR_IND_FRAG_M) >> HTT_RX_IN_ORD_PADDR_IND_FRAG_S) 11899 11900 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_SET(word, value) \ 11901 do { \ 11902 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKTLOG, value); \ 11903 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S; \ 11904 } while (0) 11905 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_GET(word) \ 11906 (((word) & HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M) >> HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S) 11907 11908 11909 /* definitions used within target -> host rx indication message */ 11910 11911 PREPACK struct htt_rx_ind_hdr_prefix_t 11912 { 11913 A_UINT32 /* word 0 */ 11914 msg_type: 8, 11915 ext_tid: 5, 11916 release_valid: 1, 11917 flush_valid: 1, 11918 reserved0: 1, 11919 peer_id: 16; 11920 11921 A_UINT32 /* word 1 */ 11922 flush_start_seq_num: 6, 11923 flush_end_seq_num: 6, 11924 release_start_seq_num: 6, 11925 release_end_seq_num: 6, 11926 num_mpdu_ranges: 8; 11927 } POSTPACK; 11928 11929 #define HTT_RX_IND_HDR_PREFIX_BYTES (sizeof(struct htt_rx_ind_hdr_prefix_t)) 11930 #define HTT_RX_IND_HDR_PREFIX_SIZE32 (HTT_RX_IND_HDR_PREFIX_BYTES >> 2) 11931 11932 #define HTT_TGT_RSSI_INVALID 0x80 11933 11934 PREPACK struct htt_rx_ppdu_desc_t 11935 { 11936 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI_CMB 0 11937 #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_SUBMICROSEC 0 11938 #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR_CODE 0 11939 #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR 0 11940 #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE 0 11941 #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE_SEL 0 11942 #define HTT_RX_IND_PPDU_OFFSET_WORD_END_VALID 0 11943 #define HTT_RX_IND_PPDU_OFFSET_WORD_START_VALID 0 11944 A_UINT32 /* word 0 */ 11945 rssi_cmb: 8, 11946 timestamp_submicrosec: 8, 11947 phy_err_code: 8, 11948 phy_err: 1, 11949 legacy_rate: 4, 11950 legacy_rate_sel: 1, 11951 end_valid: 1, 11952 start_valid: 1; 11953 11954 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI0 1 11955 union { 11956 A_UINT32 /* word 1 */ 11957 rssi0_pri20: 8, 11958 rssi0_ext20: 8, 11959 rssi0_ext40: 8, 11960 rssi0_ext80: 8; 11961 A_UINT32 rssi0; /* access all 20/40/80 per-bandwidth RSSIs together */ 11962 } u0; 11963 11964 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI1 2 11965 union { 11966 A_UINT32 /* word 2 */ 11967 rssi1_pri20: 8, 11968 rssi1_ext20: 8, 11969 rssi1_ext40: 8, 11970 rssi1_ext80: 8; 11971 A_UINT32 rssi1; /* access all 20/40/80 per-bandwidth RSSIs together */ 11972 } u1; 11973 11974 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI2 3 11975 union { 11976 A_UINT32 /* word 3 */ 11977 rssi2_pri20: 8, 11978 rssi2_ext20: 8, 11979 rssi2_ext40: 8, 11980 rssi2_ext80: 8; 11981 A_UINT32 rssi2; /* access all 20/40/80 per-bandwidth RSSIs together */ 11982 } u2; 11983 11984 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI3 4 11985 union { 11986 A_UINT32 /* word 4 */ 11987 rssi3_pri20: 8, 11988 rssi3_ext20: 8, 11989 rssi3_ext40: 8, 11990 rssi3_ext80: 8; 11991 A_UINT32 rssi3; /* access all 20/40/80 per-bandwidth RSSIs together */ 11992 } u3; 11993 11994 #define HTT_RX_IND_PPDU_OFFSET_WORD_TSF32 5 11995 A_UINT32 tsf32; /* word 5 */ 11996 11997 #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_MICROSEC 6 11998 A_UINT32 timestamp_microsec; /* word 6 */ 11999 12000 #define HTT_RX_IND_PPDU_OFFSET_WORD_PREAMBLE_TYPE 7 12001 #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A1 7 12002 A_UINT32 /* word 7 */ 12003 vht_sig_a1: 24, 12004 preamble_type: 8; 12005 12006 #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8 12007 #define HTT_RX_IND_PPDU_OFFSET_WORD_SA_ANT_MATRIX 8 12008 A_UINT32 /* word 8 */ 12009 vht_sig_a2: 24, 12010 /* sa_ant_matrix 12011 * For cases where a single rx chain has options to be connected to 12012 * different rx antennas, show which rx antennas were in use during 12013 * receipt of a given PPDU. 12014 * This sa_ant_matrix provides a bitmask of the antennas used while 12015 * receiving this frame. 12016 */ 12017 sa_ant_matrix: 8; 12018 } POSTPACK; 12019 12020 #define HTT_RX_PPDU_DESC_BYTES (sizeof(struct htt_rx_ppdu_desc_t)) 12021 #define HTT_RX_PPDU_DESC_SIZE32 (HTT_RX_PPDU_DESC_BYTES >> 2) 12022 12023 PREPACK struct htt_rx_ind_hdr_suffix_t 12024 { 12025 A_UINT32 /* word 0 */ 12026 fw_rx_desc_bytes: 16, 12027 reserved0: 16; 12028 } POSTPACK; 12029 12030 #define HTT_RX_IND_HDR_SUFFIX_BYTES (sizeof(struct htt_rx_ind_hdr_suffix_t)) 12031 #define HTT_RX_IND_HDR_SUFFIX_SIZE32 (HTT_RX_IND_HDR_SUFFIX_BYTES >> 2) 12032 12033 PREPACK struct htt_rx_ind_hdr_t 12034 { 12035 struct htt_rx_ind_hdr_prefix_t prefix; 12036 struct htt_rx_ppdu_desc_t rx_ppdu_desc; 12037 struct htt_rx_ind_hdr_suffix_t suffix; 12038 } POSTPACK; 12039 12040 #define HTT_RX_IND_HDR_BYTES (sizeof(struct htt_rx_ind_hdr_t)) 12041 #define HTT_RX_IND_HDR_SIZE32 (HTT_RX_IND_HDR_BYTES >> 2) 12042 12043 /* confirm that HTT_RX_IND_HDR_BYTES is a multiple of 4 */ 12044 A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum, 12045 (HTT_RX_IND_HDR_BYTES & 0x3) == 0); 12046 12047 /* 12048 * HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET: 12049 * the offset into the HTT rx indication message at which the 12050 * FW rx PPDU descriptor resides 12051 */ 12052 #define HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET HTT_RX_IND_HDR_PREFIX_BYTES 12053 12054 /* 12055 * HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET: 12056 * the offset into the HTT rx indication message at which the 12057 * header suffix (FW rx MSDU byte count) resides 12058 */ 12059 #define HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET \ 12060 (HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET + HTT_RX_PPDU_DESC_BYTES) 12061 12062 /* 12063 * HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET: 12064 * the offset into the HTT rx indication message at which the per-MSDU 12065 * information starts 12066 * Bytes 0-7 are the message header; bytes 8-11 contain the length of the 12067 * per-MSDU information portion of the message. The per-MSDU info itself 12068 * starts at byte 12. 12069 */ 12070 #define HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET HTT_RX_IND_HDR_BYTES 12071 12072 12073 /** 12074 * @brief target -> host rx indication message definition 12075 * 12076 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IND 12077 * 12078 * @details 12079 * The following field definitions describe the format of the rx indication 12080 * message sent from the target to the host. 12081 * The message consists of three major sections: 12082 * 1. a fixed-length header 12083 * 2. a variable-length list of firmware rx MSDU descriptors 12084 * 3. one or more 4-octet MPDU range information elements 12085 * The fixed length header itself has two sub-sections 12086 * 1. the message meta-information, including identification of the 12087 * sender and type of the received data, and a 4-octet flush/release IE 12088 * 2. the firmware rx PPDU descriptor 12089 * 12090 * The format of the message is depicted below. 12091 * in this depiction, the following abbreviations are used for information 12092 * elements within the message: 12093 * - SV - start valid: this flag is set if the FW rx PPDU descriptor 12094 * elements associated with the PPDU start are valid. 12095 * Specifically, the following fields are valid only if SV is set: 12096 * RSSI (all variants), L, legacy rate, preamble type, service, 12097 * VHT-SIG-A 12098 * - EV - end valid: this flag is set if the FW rx PPDU descriptor 12099 * elements associated with the PPDU end are valid. 12100 * Specifically, the following fields are valid only if EV is set: 12101 * P, PHY err code, TSF, microsec / sub-microsec timestamp 12102 * - L - Legacy rate selector - if legacy rates are used, this flag 12103 * indicates whether the rate is from a CCK (L == 1) or OFDM 12104 * (L == 0) PHY. 12105 * - P - PHY error flag - boolean indication of whether the rx frame had 12106 * a PHY error 12107 * 12108 * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| 12109 * |----------------+-------------------+---------------------+---------------| 12110 * | peer ID | |RV|FV| ext TID | msg type | 12111 * |--------------------------------------------------------------------------| 12112 * | num | release | release | flush | flush | 12113 * | MPDU | end | start | end | start | 12114 * | ranges | seq num | seq num | seq num | seq num | 12115 * |==========================================================================| 12116 * |S|E|L| legacy |P| PHY err code | sub-microsec | combined | 12117 * |V|V| | rate | | | timestamp | RSSI | 12118 * |--------------------------------------------------------------------------| 12119 * | RSSI rx0 ext80 | RSSI rx0 ext40 | RSSI rx0 ext20 | RSSI rx0 pri20| 12120 * |--------------------------------------------------------------------------| 12121 * | RSSI rx1 ext80 | RSSI rx1 ext40 | RSSI rx1 ext20 | RSSI rx1 pri20| 12122 * |--------------------------------------------------------------------------| 12123 * | RSSI rx2 ext80 | RSSI rx2 ext40 | RSSI rx2 ext20 | RSSI rx2 pri20| 12124 * |--------------------------------------------------------------------------| 12125 * | RSSI rx3 ext80 | RSSI rx3 ext40 | RSSI rx3 ext20 | RSSI rx3 pri20| 12126 * |--------------------------------------------------------------------------| 12127 * | TSF LSBs | 12128 * |--------------------------------------------------------------------------| 12129 * | microsec timestamp | 12130 * |--------------------------------------------------------------------------| 12131 * | preamble type | HT-SIG / VHT-SIG-A1 | 12132 * |--------------------------------------------------------------------------| 12133 * | service | HT-SIG / VHT-SIG-A2 | 12134 * |==========================================================================| 12135 * | reserved | FW rx desc bytes | 12136 * |--------------------------------------------------------------------------| 12137 * | MSDU Rx | MSDU Rx | MSDU Rx | MSDU Rx | 12138 * | desc B3 | desc B2 | desc B1 | desc B0 | 12139 * |--------------------------------------------------------------------------| 12140 * : : : 12141 * |--------------------------------------------------------------------------| 12142 * | alignment | MSDU Rx | 12143 * | padding | desc Bn | 12144 * |--------------------------------------------------------------------------| 12145 * | reserved | MPDU range status | MPDU count | 12146 * |--------------------------------------------------------------------------| 12147 * : reserved : MPDU range status : MPDU count : 12148 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : 12149 * 12150 * Header fields: 12151 * - MSG_TYPE 12152 * Bits 7:0 12153 * Purpose: identifies this as an rx indication message 12154 * Value: 0x1 (HTT_T2H_MSG_TYPE_RX_IND) 12155 * - EXT_TID 12156 * Bits 12:8 12157 * Purpose: identify the traffic ID of the rx data, including 12158 * special "extended" TID values for multicast, broadcast, and 12159 * non-QoS data frames 12160 * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS 12161 * - FLUSH_VALID (FV) 12162 * Bit 13 12163 * Purpose: indicate whether the flush IE (start/end sequence numbers) 12164 * is valid 12165 * Value: 12166 * 1 -> flush IE is valid and needs to be processed 12167 * 0 -> flush IE is not valid and should be ignored 12168 * - REL_VALID (RV) 12169 * Bit 13 12170 * Purpose: indicate whether the release IE (start/end sequence numbers) 12171 * is valid 12172 * Value: 12173 * 1 -> release IE is valid and needs to be processed 12174 * 0 -> release IE is not valid and should be ignored 12175 * - PEER_ID 12176 * Bits 31:16 12177 * Purpose: Identify, by ID, which peer sent the rx data 12178 * Value: ID of the peer who sent the rx data 12179 * - FLUSH_SEQ_NUM_START 12180 * Bits 5:0 12181 * Purpose: Indicate the start of a series of MPDUs to flush 12182 * Not all MPDUs within this series are necessarily valid - the host 12183 * must check each sequence number within this range to see if the 12184 * corresponding MPDU is actually present. 12185 * This field is only valid if the FV bit is set. 12186 * Value: 12187 * The sequence number for the first MPDUs to check to flush. 12188 * The sequence number is masked by 0x3f. 12189 * - FLUSH_SEQ_NUM_END 12190 * Bits 11:6 12191 * Purpose: Indicate the end of a series of MPDUs to flush 12192 * Value: 12193 * The sequence number one larger than the sequence number of the 12194 * last MPDU to check to flush. 12195 * The sequence number is masked by 0x3f. 12196 * Not all MPDUs within this series are necessarily valid - the host 12197 * must check each sequence number within this range to see if the 12198 * corresponding MPDU is actually present. 12199 * This field is only valid if the FV bit is set. 12200 * - REL_SEQ_NUM_START 12201 * Bits 17:12 12202 * Purpose: Indicate the start of a series of MPDUs to release. 12203 * All MPDUs within this series are present and valid - the host 12204 * need not check each sequence number within this range to see if 12205 * the corresponding MPDU is actually present. 12206 * This field is only valid if the RV bit is set. 12207 * Value: 12208 * The sequence number for the first MPDUs to check to release. 12209 * The sequence number is masked by 0x3f. 12210 * - REL_SEQ_NUM_END 12211 * Bits 23:18 12212 * Purpose: Indicate the end of a series of MPDUs to release. 12213 * Value: 12214 * The sequence number one larger than the sequence number of the 12215 * last MPDU to check to release. 12216 * The sequence number is masked by 0x3f. 12217 * All MPDUs within this series are present and valid - the host 12218 * need not check each sequence number within this range to see if 12219 * the corresponding MPDU is actually present. 12220 * This field is only valid if the RV bit is set. 12221 * - NUM_MPDU_RANGES 12222 * Bits 31:24 12223 * Purpose: Indicate how many ranges of MPDUs are present. 12224 * Each MPDU range consists of a series of contiguous MPDUs within the 12225 * rx frame sequence which all have the same MPDU status. 12226 * Value: 1-63 (typically a small number, like 1-3) 12227 * 12228 * Rx PPDU descriptor fields: 12229 * - RSSI_CMB 12230 * Bits 7:0 12231 * Purpose: Combined RSSI from all active rx chains, across the active 12232 * bandwidth. 12233 * Value: RSSI dB units w.r.t. noise floor 12234 * - TIMESTAMP_SUBMICROSEC 12235 * Bits 15:8 12236 * Purpose: high-resolution timestamp 12237 * Value: 12238 * Sub-microsecond time of PPDU reception. 12239 * This timestamp ranges from [0,MAC clock MHz). 12240 * This timestamp can be used in conjunction with TIMESTAMP_MICROSEC 12241 * to form a high-resolution, large range rx timestamp. 12242 * - PHY_ERR_CODE 12243 * Bits 23:16 12244 * Purpose: 12245 * If the rx frame processing resulted in a PHY error, indicate what 12246 * type of rx PHY error occurred. 12247 * Value: 12248 * This field is valid if the "P" (PHY_ERR) flag is set. 12249 * TBD: document/specify the values for this field 12250 * - PHY_ERR 12251 * Bit 24 12252 * Purpose: indicate whether the rx PPDU had a PHY error 12253 * Value: 0 -> no rx PHY error, 1 -> rx PHY error encountered 12254 * - LEGACY_RATE 12255 * Bits 28:25 12256 * Purpose: 12257 * If the rx frame used a legacy rate rather than a HT or VHT rate, 12258 * specify which rate was used. 12259 * Value: 12260 * The LEGACY_RATE field's value depends on the "L" (LEGACY_RATE_SEL) 12261 * flag. 12262 * If LEGACY_RATE_SEL is 0: 12263 * 0x8: OFDM 48 Mbps 12264 * 0x9: OFDM 24 Mbps 12265 * 0xA: OFDM 12 Mbps 12266 * 0xB: OFDM 6 Mbps 12267 * 0xC: OFDM 54 Mbps 12268 * 0xD: OFDM 36 Mbps 12269 * 0xE: OFDM 18 Mbps 12270 * 0xF: OFDM 9 Mbps 12271 * If LEGACY_RATE_SEL is 1: 12272 * 0x8: CCK 11 Mbps long preamble 12273 * 0x9: CCK 5.5 Mbps long preamble 12274 * 0xA: CCK 2 Mbps long preamble 12275 * 0xB: CCK 1 Mbps long preamble 12276 * 0xC: CCK 11 Mbps short preamble 12277 * 0xD: CCK 5.5 Mbps short preamble 12278 * 0xE: CCK 2 Mbps short preamble 12279 * - LEGACY_RATE_SEL 12280 * Bit 29 12281 * Purpose: if rx used a legacy rate, specify whether it was OFDM or CCK 12282 * Value: 12283 * This field is valid if the PREAMBLE_TYPE field indicates the rx 12284 * used a legacy rate. 12285 * 0 -> OFDM, 1 -> CCK 12286 * - END_VALID 12287 * Bit 30 12288 * Purpose: Indicate whether the FW rx PPDU desc fields associated with 12289 * the start of the PPDU are valid. Specifically, the following 12290 * fields are only valid if END_VALID is set: 12291 * PHY_ERR, PHY_ERR_CODE, TSF32, TIMESTAMP_MICROSEC, 12292 * TIMESTAMP_SUBMICROSEC 12293 * Value: 12294 * 0 -> rx PPDU desc end fields are not valid 12295 * 1 -> rx PPDU desc end fields are valid 12296 * - START_VALID 12297 * Bit 31 12298 * Purpose: Indicate whether the FW rx PPDU desc fields associated with 12299 * the end of the PPDU are valid. Specifically, the following 12300 * fields are only valid if START_VALID is set: 12301 * RSSI, LEGACY_RATE_SEL, LEGACY_RATE, PREAMBLE_TYPE, SERVICE, 12302 * VHT-SIG-A 12303 * Value: 12304 * 0 -> rx PPDU desc start fields are not valid 12305 * 1 -> rx PPDU desc start fields are valid 12306 * - RSSI0_PRI20 12307 * Bits 7:0 12308 * Purpose: RSSI from chain 0 on the primary 20 MHz channel 12309 * Value: RSSI dB units w.r.t. noise floor 12310 * 12311 * - RSSI0_EXT20 12312 * Bits 7:0 12313 * Purpose: RSSI from chain 0 on the bonded extension 20 MHz channel 12314 * (if the rx bandwidth was >= 40 MHz) 12315 * Value: RSSI dB units w.r.t. noise floor 12316 * - RSSI0_EXT40 12317 * Bits 7:0 12318 * Purpose: RSSI from chain 0 on the bonded extension 40 MHz channel 12319 * (if the rx bandwidth was >= 80 MHz) 12320 * Value: RSSI dB units w.r.t. noise floor 12321 * - RSSI0_EXT80 12322 * Bits 7:0 12323 * Purpose: RSSI from chain 0 on the bonded extension 80 MHz channel 12324 * (if the rx bandwidth was >= 160 MHz) 12325 * Value: RSSI dB units w.r.t. noise floor 12326 * 12327 * - RSSI1_PRI20 12328 * Bits 7:0 12329 * Purpose: RSSI from chain 1 on the primary 20 MHz channel 12330 * Value: RSSI dB units w.r.t. noise floor 12331 * - RSSI1_EXT20 12332 * Bits 7:0 12333 * Purpose: RSSI from chain 1 on the bonded extension 20 MHz channel 12334 * (if the rx bandwidth was >= 40 MHz) 12335 * Value: RSSI dB units w.r.t. noise floor 12336 * - RSSI1_EXT40 12337 * Bits 7:0 12338 * Purpose: RSSI from chain 1 on the bonded extension 40 MHz channel 12339 * (if the rx bandwidth was >= 80 MHz) 12340 * Value: RSSI dB units w.r.t. noise floor 12341 * - RSSI1_EXT80 12342 * Bits 7:0 12343 * Purpose: RSSI from chain 1 on the bonded extension 80 MHz channel 12344 * (if the rx bandwidth was >= 160 MHz) 12345 * Value: RSSI dB units w.r.t. noise floor 12346 * 12347 * - RSSI2_PRI20 12348 * Bits 7:0 12349 * Purpose: RSSI from chain 2 on the primary 20 MHz channel 12350 * Value: RSSI dB units w.r.t. noise floor 12351 * - RSSI2_EXT20 12352 * Bits 7:0 12353 * Purpose: RSSI from chain 2 on the bonded extension 20 MHz channel 12354 * (if the rx bandwidth was >= 40 MHz) 12355 * Value: RSSI dB units w.r.t. noise floor 12356 * - RSSI2_EXT40 12357 * Bits 7:0 12358 * Purpose: RSSI from chain 2 on the bonded extension 40 MHz channel 12359 * (if the rx bandwidth was >= 80 MHz) 12360 * Value: RSSI dB units w.r.t. noise floor 12361 * - RSSI2_EXT80 12362 * Bits 7:0 12363 * Purpose: RSSI from chain 2 on the bonded extension 80 MHz channel 12364 * (if the rx bandwidth was >= 160 MHz) 12365 * Value: RSSI dB units w.r.t. noise floor 12366 * 12367 * - RSSI3_PRI20 12368 * Bits 7:0 12369 * Purpose: RSSI from chain 3 on the primary 20 MHz channel 12370 * Value: RSSI dB units w.r.t. noise floor 12371 * - RSSI3_EXT20 12372 * Bits 7:0 12373 * Purpose: RSSI from chain 3 on the bonded extension 20 MHz channel 12374 * (if the rx bandwidth was >= 40 MHz) 12375 * Value: RSSI dB units w.r.t. noise floor 12376 * - RSSI3_EXT40 12377 * Bits 7:0 12378 * Purpose: RSSI from chain 3 on the bonded extension 40 MHz channel 12379 * (if the rx bandwidth was >= 80 MHz) 12380 * Value: RSSI dB units w.r.t. noise floor 12381 * - RSSI3_EXT80 12382 * Bits 7:0 12383 * Purpose: RSSI from chain 3 on the bonded extension 80 MHz channel 12384 * (if the rx bandwidth was >= 160 MHz) 12385 * Value: RSSI dB units w.r.t. noise floor 12386 * 12387 * - TSF32 12388 * Bits 31:0 12389 * Purpose: specify the time the rx PPDU was received, in TSF units 12390 * Value: 32 LSBs of the TSF 12391 * - TIMESTAMP_MICROSEC 12392 * Bits 31:0 12393 * Purpose: specify the time the rx PPDU was received, in microsecond units 12394 * Value: PPDU rx time, in microseconds 12395 * - VHT_SIG_A1 12396 * Bits 23:0 12397 * Purpose: Provide the HT-SIG (initial 24 bits) or VHT-SIG-A1 field 12398 * from the rx PPDU 12399 * Value: 12400 * If PREAMBLE_TYPE specifies VHT, then this field contains the 12401 * VHT-SIG-A1 data. 12402 * If PREAMBLE_TYPE specifies HT, then this field contains the 12403 * first 24 bits of the HT-SIG data. 12404 * Otherwise, this field is invalid. 12405 * Refer to the the 802.11 protocol for the definition of the 12406 * HT-SIG and VHT-SIG-A1 fields 12407 * - VHT_SIG_A2 12408 * Bits 23:0 12409 * Purpose: Provide the HT-SIG (final 24 bits) or VHT-SIG-A2 field 12410 * from the rx PPDU 12411 * Value: 12412 * If PREAMBLE_TYPE specifies VHT, then this field contains the 12413 * VHT-SIG-A2 data. 12414 * If PREAMBLE_TYPE specifies HT, then this field contains the 12415 * last 24 bits of the HT-SIG data. 12416 * Otherwise, this field is invalid. 12417 * Refer to the the 802.11 protocol for the definition of the 12418 * HT-SIG and VHT-SIG-A2 fields 12419 * - PREAMBLE_TYPE 12420 * Bits 31:24 12421 * Purpose: indicate the PHY format of the received burst 12422 * Value: 12423 * 0x4: Legacy (OFDM/CCK) 12424 * 0x8: HT 12425 * 0x9: HT with TxBF 12426 * 0xC: VHT 12427 * 0xD: VHT with TxBF 12428 * - SERVICE 12429 * Bits 31:24 12430 * Purpose: TBD 12431 * Value: TBD 12432 * 12433 * Rx MSDU descriptor fields: 12434 * - FW_RX_DESC_BYTES 12435 * Bits 15:0 12436 * Purpose: Indicate how many bytes in the Rx indication are used for 12437 * FW Rx descriptors 12438 * 12439 * Payload fields: 12440 * - MPDU_COUNT 12441 * Bits 7:0 12442 * Purpose: Indicate how many sequential MPDUs share the same status. 12443 * All MPDUs within the indicated list are from the same RA-TA-TID. 12444 * - MPDU_STATUS 12445 * Bits 15:8 12446 * Purpose: Indicate whether the (group of sequential) MPDU(s) were 12447 * received successfully. 12448 * Value: 12449 * 0x1: success 12450 * 0x2: FCS error 12451 * 0x3: duplicate error 12452 * 0x4: replay error 12453 * 0x5: invalid peer 12454 */ 12455 /* header fields */ 12456 #define HTT_RX_IND_EXT_TID_M 0x1f00 12457 #define HTT_RX_IND_EXT_TID_S 8 12458 #define HTT_RX_IND_FLUSH_VALID_M 0x2000 12459 #define HTT_RX_IND_FLUSH_VALID_S 13 12460 #define HTT_RX_IND_REL_VALID_M 0x4000 12461 #define HTT_RX_IND_REL_VALID_S 14 12462 #define HTT_RX_IND_PEER_ID_M 0xffff0000 12463 #define HTT_RX_IND_PEER_ID_S 16 12464 12465 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_M 0x3f 12466 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_S 0 12467 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_M 0xfc0 12468 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_S 6 12469 #define HTT_RX_IND_REL_SEQ_NUM_START_M 0x3f000 12470 #define HTT_RX_IND_REL_SEQ_NUM_START_S 12 12471 #define HTT_RX_IND_REL_SEQ_NUM_END_M 0xfc0000 12472 #define HTT_RX_IND_REL_SEQ_NUM_END_S 18 12473 #define HTT_RX_IND_NUM_MPDU_RANGES_M 0xff000000 12474 #define HTT_RX_IND_NUM_MPDU_RANGES_S 24 12475 12476 /* rx PPDU descriptor fields */ 12477 #define HTT_RX_IND_RSSI_CMB_M 0x000000ff 12478 #define HTT_RX_IND_RSSI_CMB_S 0 12479 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M 0x0000ff00 12480 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S 8 12481 #define HTT_RX_IND_PHY_ERR_CODE_M 0x00ff0000 12482 #define HTT_RX_IND_PHY_ERR_CODE_S 16 12483 #define HTT_RX_IND_PHY_ERR_M 0x01000000 12484 #define HTT_RX_IND_PHY_ERR_S 24 12485 #define HTT_RX_IND_LEGACY_RATE_M 0x1e000000 12486 #define HTT_RX_IND_LEGACY_RATE_S 25 12487 #define HTT_RX_IND_LEGACY_RATE_SEL_M 0x20000000 12488 #define HTT_RX_IND_LEGACY_RATE_SEL_S 29 12489 #define HTT_RX_IND_END_VALID_M 0x40000000 12490 #define HTT_RX_IND_END_VALID_S 30 12491 #define HTT_RX_IND_START_VALID_M 0x80000000 12492 #define HTT_RX_IND_START_VALID_S 31 12493 12494 #define HTT_RX_IND_RSSI_PRI20_M 0x000000ff 12495 #define HTT_RX_IND_RSSI_PRI20_S 0 12496 #define HTT_RX_IND_RSSI_EXT20_M 0x0000ff00 12497 #define HTT_RX_IND_RSSI_EXT20_S 8 12498 #define HTT_RX_IND_RSSI_EXT40_M 0x00ff0000 12499 #define HTT_RX_IND_RSSI_EXT40_S 16 12500 #define HTT_RX_IND_RSSI_EXT80_M 0xff000000 12501 #define HTT_RX_IND_RSSI_EXT80_S 24 12502 12503 #define HTT_RX_IND_VHT_SIG_A1_M 0x00ffffff 12504 #define HTT_RX_IND_VHT_SIG_A1_S 0 12505 #define HTT_RX_IND_VHT_SIG_A2_M 0x00ffffff 12506 #define HTT_RX_IND_VHT_SIG_A2_S 0 12507 #define HTT_RX_IND_PREAMBLE_TYPE_M 0xff000000 12508 #define HTT_RX_IND_PREAMBLE_TYPE_S 24 12509 #define HTT_RX_IND_SERVICE_M 0xff000000 12510 #define HTT_RX_IND_SERVICE_S 24 12511 #define HTT_RX_IND_SA_ANT_MATRIX_M 0xff000000 12512 #define HTT_RX_IND_SA_ANT_MATRIX_S 24 12513 12514 /* rx MSDU descriptor fields */ 12515 #define HTT_RX_IND_FW_RX_DESC_BYTES_M 0xffff 12516 #define HTT_RX_IND_FW_RX_DESC_BYTES_S 0 12517 12518 /* payload fields */ 12519 #define HTT_RX_IND_MPDU_COUNT_M 0xff 12520 #define HTT_RX_IND_MPDU_COUNT_S 0 12521 #define HTT_RX_IND_MPDU_STATUS_M 0xff00 12522 #define HTT_RX_IND_MPDU_STATUS_S 8 12523 12524 12525 #define HTT_RX_IND_EXT_TID_SET(word, value) \ 12526 do { \ 12527 HTT_CHECK_SET_VAL(HTT_RX_IND_EXT_TID, value); \ 12528 (word) |= (value) << HTT_RX_IND_EXT_TID_S; \ 12529 } while (0) 12530 #define HTT_RX_IND_EXT_TID_GET(word) \ 12531 (((word) & HTT_RX_IND_EXT_TID_M) >> HTT_RX_IND_EXT_TID_S) 12532 12533 #define HTT_RX_IND_FLUSH_VALID_SET(word, value) \ 12534 do { \ 12535 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_VALID, value); \ 12536 (word) |= (value) << HTT_RX_IND_FLUSH_VALID_S; \ 12537 } while (0) 12538 #define HTT_RX_IND_FLUSH_VALID_GET(word) \ 12539 (((word) & HTT_RX_IND_FLUSH_VALID_M) >> HTT_RX_IND_FLUSH_VALID_S) 12540 12541 #define HTT_RX_IND_REL_VALID_SET(word, value) \ 12542 do { \ 12543 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_VALID, value); \ 12544 (word) |= (value) << HTT_RX_IND_REL_VALID_S; \ 12545 } while (0) 12546 #define HTT_RX_IND_REL_VALID_GET(word) \ 12547 (((word) & HTT_RX_IND_REL_VALID_M) >> HTT_RX_IND_REL_VALID_S) 12548 12549 #define HTT_RX_IND_PEER_ID_SET(word, value) \ 12550 do { \ 12551 HTT_CHECK_SET_VAL(HTT_RX_IND_PEER_ID, value); \ 12552 (word) |= (value) << HTT_RX_IND_PEER_ID_S; \ 12553 } while (0) 12554 #define HTT_RX_IND_PEER_ID_GET(word) \ 12555 (((word) & HTT_RX_IND_PEER_ID_M) >> HTT_RX_IND_PEER_ID_S) 12556 12557 12558 #define HTT_RX_IND_FW_RX_DESC_BYTES_SET(word, value) \ 12559 do { \ 12560 HTT_CHECK_SET_VAL(HTT_RX_IND_FW_RX_DESC_BYTES, value); \ 12561 (word) |= (value) << HTT_RX_IND_FW_RX_DESC_BYTES_S; \ 12562 } while (0) 12563 #define HTT_RX_IND_FW_RX_DESC_BYTES_GET(word) \ 12564 (((word) & HTT_RX_IND_FW_RX_DESC_BYTES_M) >> HTT_RX_IND_FW_RX_DESC_BYTES_S) 12565 12566 12567 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_SET(word, value) \ 12568 do { \ 12569 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_START, value); \ 12570 (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_START_S; \ 12571 } while (0) 12572 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_GET(word) \ 12573 (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_START_M) >> \ 12574 HTT_RX_IND_FLUSH_SEQ_NUM_START_S) 12575 12576 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_SET(word, value) \ 12577 do { \ 12578 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_END, value); \ 12579 (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_END_S; \ 12580 } while (0) 12581 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_GET(word) \ 12582 (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_END_M) >> \ 12583 HTT_RX_IND_FLUSH_SEQ_NUM_END_S) 12584 12585 #define HTT_RX_IND_REL_SEQ_NUM_START_SET(word, value) \ 12586 do { \ 12587 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_START, value); \ 12588 (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_START_S; \ 12589 } while (0) 12590 #define HTT_RX_IND_REL_SEQ_NUM_START_GET(word) \ 12591 (((word) & HTT_RX_IND_REL_SEQ_NUM_START_M) >> \ 12592 HTT_RX_IND_REL_SEQ_NUM_START_S) 12593 12594 #define HTT_RX_IND_REL_SEQ_NUM_END_SET(word, value) \ 12595 do { \ 12596 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_END, value); \ 12597 (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_END_S; \ 12598 } while (0) 12599 #define HTT_RX_IND_REL_SEQ_NUM_END_GET(word) \ 12600 (((word) & HTT_RX_IND_REL_SEQ_NUM_END_M) >> \ 12601 HTT_RX_IND_REL_SEQ_NUM_END_S) 12602 12603 #define HTT_RX_IND_NUM_MPDU_RANGES_SET(word, value) \ 12604 do { \ 12605 HTT_CHECK_SET_VAL(HTT_RX_IND_NUM_MPDU_RANGES, value); \ 12606 (word) |= (value) << HTT_RX_IND_NUM_MPDU_RANGES_S; \ 12607 } while (0) 12608 #define HTT_RX_IND_NUM_MPDU_RANGES_GET(word) \ 12609 (((word) & HTT_RX_IND_NUM_MPDU_RANGES_M) >> \ 12610 HTT_RX_IND_NUM_MPDU_RANGES_S) 12611 12612 /* FW rx PPDU descriptor fields */ 12613 #define HTT_RX_IND_RSSI_CMB_SET(word, value) \ 12614 do { \ 12615 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_CMB, value); \ 12616 (word) |= (value) << HTT_RX_IND_RSSI_CMB_S; \ 12617 } while (0) 12618 #define HTT_RX_IND_RSSI_CMB_GET(word) \ 12619 (((word) & HTT_RX_IND_RSSI_CMB_M) >> \ 12620 HTT_RX_IND_RSSI_CMB_S) 12621 12622 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_SET(word, value) \ 12623 do { \ 12624 HTT_CHECK_SET_VAL(HTT_RX_IND_TIMESTAMP_SUBMICROSEC, value); \ 12625 (word) |= (value) << HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S; \ 12626 } while (0) 12627 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_GET(word) \ 12628 (((word) & HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M) >> \ 12629 HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S) 12630 12631 #define HTT_RX_IND_PHY_ERR_CODE_SET(word, value) \ 12632 do { \ 12633 HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR_CODE, value); \ 12634 (word) |= (value) << HTT_RX_IND_PHY_ERR_CODE_S; \ 12635 } while (0) 12636 #define HTT_RX_IND_PHY_ERR_CODE_GET(word) \ 12637 (((word) & HTT_RX_IND_PHY_ERR_CODE_M) >> \ 12638 HTT_RX_IND_PHY_ERR_CODE_S) 12639 12640 #define HTT_RX_IND_PHY_ERR_SET(word, value) \ 12641 do { \ 12642 HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR, value); \ 12643 (word) |= (value) << HTT_RX_IND_PHY_ERR_S; \ 12644 } while (0) 12645 #define HTT_RX_IND_PHY_ERR_GET(word) \ 12646 (((word) & HTT_RX_IND_PHY_ERR_M) >> \ 12647 HTT_RX_IND_PHY_ERR_S) 12648 12649 #define HTT_RX_IND_LEGACY_RATE_SET(word, value) \ 12650 do { \ 12651 HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE, value); \ 12652 (word) |= (value) << HTT_RX_IND_LEGACY_RATE_S; \ 12653 } while (0) 12654 #define HTT_RX_IND_LEGACY_RATE_GET(word) \ 12655 (((word) & HTT_RX_IND_LEGACY_RATE_M) >> \ 12656 HTT_RX_IND_LEGACY_RATE_S) 12657 12658 #define HTT_RX_IND_LEGACY_RATE_SEL_SET(word, value) \ 12659 do { \ 12660 HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE_SEL, value); \ 12661 (word) |= (value) << HTT_RX_IND_LEGACY_RATE_SEL_S; \ 12662 } while (0) 12663 #define HTT_RX_IND_LEGACY_RATE_SEL_GET(word) \ 12664 (((word) & HTT_RX_IND_LEGACY_RATE_SEL_M) >> \ 12665 HTT_RX_IND_LEGACY_RATE_SEL_S) 12666 12667 #define HTT_RX_IND_END_VALID_SET(word, value) \ 12668 do { \ 12669 HTT_CHECK_SET_VAL(HTT_RX_IND_END_VALID, value); \ 12670 (word) |= (value) << HTT_RX_IND_END_VALID_S; \ 12671 } while (0) 12672 #define HTT_RX_IND_END_VALID_GET(word) \ 12673 (((word) & HTT_RX_IND_END_VALID_M) >> \ 12674 HTT_RX_IND_END_VALID_S) 12675 12676 #define HTT_RX_IND_START_VALID_SET(word, value) \ 12677 do { \ 12678 HTT_CHECK_SET_VAL(HTT_RX_IND_START_VALID, value); \ 12679 (word) |= (value) << HTT_RX_IND_START_VALID_S; \ 12680 } while (0) 12681 #define HTT_RX_IND_START_VALID_GET(word) \ 12682 (((word) & HTT_RX_IND_START_VALID_M) >> \ 12683 HTT_RX_IND_START_VALID_S) 12684 12685 #define HTT_RX_IND_RSSI_PRI20_SET(word, value) \ 12686 do { \ 12687 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_PRI20, value); \ 12688 (word) |= (value) << HTT_RX_IND_RSSI_PRI20_S; \ 12689 } while (0) 12690 #define HTT_RX_IND_RSSI_PRI20_GET(word) \ 12691 (((word) & HTT_RX_IND_RSSI_PRI20_M) >> \ 12692 HTT_RX_IND_RSSI_PRI20_S) 12693 12694 #define HTT_RX_IND_RSSI_EXT20_SET(word, value) \ 12695 do { \ 12696 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT20, value); \ 12697 (word) |= (value) << HTT_RX_IND_RSSI_EXT20_S; \ 12698 } while (0) 12699 #define HTT_RX_IND_RSSI_EXT20_GET(word) \ 12700 (((word) & HTT_RX_IND_RSSI_EXT20_M) >> \ 12701 HTT_RX_IND_RSSI_EXT20_S) 12702 12703 #define HTT_RX_IND_RSSI_EXT40_SET(word, value) \ 12704 do { \ 12705 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT40, value); \ 12706 (word) |= (value) << HTT_RX_IND_RSSI_EXT40_S; \ 12707 } while (0) 12708 #define HTT_RX_IND_RSSI_EXT40_GET(word) \ 12709 (((word) & HTT_RX_IND_RSSI_EXT40_M) >> \ 12710 HTT_RX_IND_RSSI_EXT40_S) 12711 12712 #define HTT_RX_IND_RSSI_EXT80_SET(word, value) \ 12713 do { \ 12714 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT80, value); \ 12715 (word) |= (value) << HTT_RX_IND_RSSI_EXT80_S; \ 12716 } while (0) 12717 #define HTT_RX_IND_RSSI_EXT80_GET(word) \ 12718 (((word) & HTT_RX_IND_RSSI_EXT80_M) >> \ 12719 HTT_RX_IND_RSSI_EXT80_S) 12720 12721 #define HTT_RX_IND_VHT_SIG_A1_SET(word, value) \ 12722 do { \ 12723 HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A1, value); \ 12724 (word) |= (value) << HTT_RX_IND_VHT_SIG_A1_S; \ 12725 } while (0) 12726 #define HTT_RX_IND_VHT_SIG_A1_GET(word) \ 12727 (((word) & HTT_RX_IND_VHT_SIG_A1_M) >> \ 12728 HTT_RX_IND_VHT_SIG_A1_S) 12729 12730 #define HTT_RX_IND_VHT_SIG_A2_SET(word, value) \ 12731 do { \ 12732 HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A2, value); \ 12733 (word) |= (value) << HTT_RX_IND_VHT_SIG_A2_S; \ 12734 } while (0) 12735 #define HTT_RX_IND_VHT_SIG_A2_GET(word) \ 12736 (((word) & HTT_RX_IND_VHT_SIG_A2_M) >> \ 12737 HTT_RX_IND_VHT_SIG_A2_S) 12738 12739 #define HTT_RX_IND_PREAMBLE_TYPE_SET(word, value) \ 12740 do { \ 12741 HTT_CHECK_SET_VAL(HTT_RX_IND_PREAMBLE_TYPE, value); \ 12742 (word) |= (value) << HTT_RX_IND_PREAMBLE_TYPE_S; \ 12743 } while (0) 12744 #define HTT_RX_IND_PREAMBLE_TYPE_GET(word) \ 12745 (((word) & HTT_RX_IND_PREAMBLE_TYPE_M) >> \ 12746 HTT_RX_IND_PREAMBLE_TYPE_S) 12747 12748 #define HTT_RX_IND_SERVICE_SET(word, value) \ 12749 do { \ 12750 HTT_CHECK_SET_VAL(HTT_RX_IND_SERVICE, value); \ 12751 (word) |= (value) << HTT_RX_IND_SERVICE_S; \ 12752 } while (0) 12753 #define HTT_RX_IND_SERVICE_GET(word) \ 12754 (((word) & HTT_RX_IND_SERVICE_M) >> \ 12755 HTT_RX_IND_SERVICE_S) 12756 12757 #define HTT_RX_IND_SA_ANT_MATRIX_SET(word, value) \ 12758 do { \ 12759 HTT_CHECK_SET_VAL(HTT_RX_IND_SA_ANT_MATRIX, value); \ 12760 (word) |= (value) << HTT_RX_IND_SA_ANT_MATRIX_S; \ 12761 } while (0) 12762 #define HTT_RX_IND_SA_ANT_MATRIX_GET(word) \ 12763 (((word) & HTT_RX_IND_SA_ANT_MATRIX_M) >> \ 12764 HTT_RX_IND_SA_ANT_MATRIX_S) 12765 12766 #define HTT_RX_IND_MPDU_COUNT_SET(word, value) \ 12767 do { \ 12768 HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_COUNT, value); \ 12769 (word) |= (value) << HTT_RX_IND_MPDU_COUNT_S; \ 12770 } while (0) 12771 #define HTT_RX_IND_MPDU_COUNT_GET(word) \ 12772 (((word) & HTT_RX_IND_MPDU_COUNT_M) >> HTT_RX_IND_MPDU_COUNT_S) 12773 12774 #define HTT_RX_IND_MPDU_STATUS_SET(word, value) \ 12775 do { \ 12776 HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_STATUS, value); \ 12777 (word) |= (value) << HTT_RX_IND_MPDU_STATUS_S; \ 12778 } while (0) 12779 #define HTT_RX_IND_MPDU_STATUS_GET(word) \ 12780 (((word) & HTT_RX_IND_MPDU_STATUS_M) >> HTT_RX_IND_MPDU_STATUS_S) 12781 12782 12783 #define HTT_RX_IND_HL_BYTES \ 12784 (HTT_RX_IND_HDR_BYTES + \ 12785 4 /* single FW rx MSDU descriptor */ + \ 12786 4 /* single MPDU range information element */) 12787 #define HTT_RX_IND_HL_SIZE32 (HTT_RX_IND_HL_BYTES >> 2) 12788 12789 /* Could we use one macro entry? */ 12790 #define HTT_WORD_SET(word, field, value) \ 12791 do { \ 12792 HTT_CHECK_SET_VAL(field, value); \ 12793 (word) |= ((value) << field ## _S); \ 12794 } while (0) 12795 #define HTT_WORD_GET(word, field) \ 12796 (((word) & field ## _M) >> field ## _S) 12797 12798 PREPACK struct hl_htt_rx_ind_base { 12799 A_UINT32 rx_ind_msg[HTT_RX_IND_HL_SIZE32]; /* align with LL case rx indication message, but reduced to 5 words */ 12800 } POSTPACK; 12801 12802 /* 12803 * HTT_RX_IND_HL_RX_DESC_BASE_OFFSET 12804 * Currently, we use a resv field in hl_htt_rx_ind_base to store some 12805 * HL host needed info; refer to fw_rx_desc_base in wal_rx_desc.h. 12806 * The field is just after the MSDU FW rx desc, and 1 byte ahead of 12807 * htt_rx_ind_hl_rx_desc_t. 12808 */ 12809 #define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1) 12810 struct htt_rx_ind_hl_rx_desc_t { 12811 A_UINT8 ver; 12812 A_UINT8 len; 12813 struct { 12814 A_UINT8 12815 first_msdu: 1, 12816 last_msdu: 1, 12817 c3_failed: 1, 12818 c4_failed: 1, 12819 ipv6: 1, 12820 tcp: 1, 12821 udp: 1, 12822 reserved: 1; 12823 } flags; 12824 /* NOTE: no reserved space - don't append any new fields here */ 12825 }; 12826 12827 #define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \ 12828 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12829 + offsetof(struct htt_rx_ind_hl_rx_desc_t, ver)) 12830 #define HTT_RX_IND_HL_RX_DESC_VER 0 12831 12832 #define HTT_RX_IND_HL_RX_DESC_LEN_OFFSET \ 12833 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12834 + offsetof(struct htt_rx_ind_hl_rx_desc_t, len)) 12835 12836 #define HTT_RX_IND_HL_FLAG_OFFSET \ 12837 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12838 + offsetof(struct htt_rx_ind_hl_rx_desc_t, flags)) 12839 12840 #define HTT_RX_IND_HL_FLAG_FIRST_MSDU (0x01 << 0) 12841 #define HTT_RX_IND_HL_FLAG_LAST_MSDU (0x01 << 1) 12842 #define HTT_RX_IND_HL_FLAG_C3_FAILED (0x01 << 2) /* L3 checksum failed */ 12843 #define HTT_RX_IND_HL_FLAG_C4_FAILED (0x01 << 3) /* L4 checksum failed */ 12844 #define HTT_RX_IND_HL_FLAG_IPV6 (0x01 << 4) /* is ipv6, or else ipv4 */ 12845 #define HTT_RX_IND_HL_FLAG_TCP (0x01 << 5) /* is tcp */ 12846 #define HTT_RX_IND_HL_FLAG_UDP (0x01 << 6) /* is udp */ 12847 /* This structure is used in HL, the basic descriptor information 12848 * used by host. the structure is translated by FW from HW desc 12849 * or generated by FW. But in HL monitor mode, the host would use 12850 * the same structure with LL. 12851 */ 12852 PREPACK struct hl_htt_rx_desc_base { 12853 A_UINT32 12854 seq_num:12, 12855 encrypted:1, 12856 chan_info_present:1, 12857 resv0:2, 12858 mcast_bcast:1, 12859 fragment:1, 12860 key_id_oct:8, 12861 resv1:6; 12862 A_UINT32 12863 pn_31_0; 12864 union { 12865 struct { 12866 A_UINT16 pn_47_32; 12867 A_UINT16 pn_63_48; 12868 } pn16; 12869 A_UINT32 pn_63_32; 12870 } u0; 12871 A_UINT32 12872 pn_95_64; 12873 A_UINT32 12874 pn_127_96; 12875 } POSTPACK; 12876 12877 12878 /* 12879 * Channel information can optionally be appended after hl_htt_rx_desc_base. 12880 * If so, the len field in htt_rx_ind_hl_rx_desc_t will be updated accordingly, 12881 * and the chan_info_present flag in hl_htt_rx_desc_base will be set. 12882 * Please see htt_chan_change_t for description of the fields. 12883 */ 12884 PREPACK struct htt_chan_info_t 12885 { 12886 A_UINT32 primary_chan_center_freq_mhz: 16, 12887 contig_chan1_center_freq_mhz: 16; 12888 A_UINT32 contig_chan2_center_freq_mhz: 16, 12889 phy_mode: 8, 12890 reserved: 8; 12891 } POSTPACK; 12892 12893 #define HTT_CHAN_INFO_SIZE sizeof(struct htt_chan_info_t) 12894 12895 #define HL_RX_DESC_SIZE (sizeof(struct hl_htt_rx_desc_base)) 12896 #define HL_RX_DESC_SIZE_DWORD (HL_RX_STD_DESC_SIZE >> 2) 12897 12898 #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_M 0xfff 12899 #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_S 0 12900 #define HTT_HL_RX_DESC_MPDU_ENC_M 0x1000 12901 #define HTT_HL_RX_DESC_MPDU_ENC_S 12 12902 #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_M 0x2000 12903 #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_S 13 12904 #define HTT_HL_RX_DESC_MCAST_BCAST_M 0x10000 12905 #define HTT_HL_RX_DESC_MCAST_BCAST_S 16 12906 #define HTT_HL_RX_DESC_FRAGMENT_M 0x20000 12907 #define HTT_HL_RX_DESC_FRAGMENT_S 17 12908 #define HTT_HL_RX_DESC_KEY_ID_OCT_M 0x3fc0000 12909 #define HTT_HL_RX_DESC_KEY_ID_OCT_S 18 12910 12911 #define HTT_HL_RX_DESC_PN_OFFSET offsetof(struct hl_htt_rx_desc_base, pn_31_0) 12912 #define HTT_HL_RX_DESC_PN_WORD_OFFSET (HTT_HL_RX_DESC_PN_OFFSET >> 2) 12913 12914 12915 /* Channel information */ 12916 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M 0x0000ffff 12917 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S 0 12918 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M 0xffff0000 12919 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S 16 12920 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M 0x0000ffff 12921 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S 0 12922 #define HTT_CHAN_INFO_PHY_MODE_M 0x00ff0000 12923 #define HTT_CHAN_INFO_PHY_MODE_S 16 12924 12925 12926 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_SET(word, value) \ 12927 do { \ 12928 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ, value); \ 12929 (word) |= (value) << HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S; \ 12930 } while (0) 12931 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_GET(word) \ 12932 (((word) & HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M) >> HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S) 12933 12934 12935 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_SET(word, value) \ 12936 do { \ 12937 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ, value); \ 12938 (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S; \ 12939 } while (0) 12940 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_GET(word) \ 12941 (((word) & HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S) 12942 12943 12944 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_SET(word, value) \ 12945 do { \ 12946 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ, value); \ 12947 (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S; \ 12948 } while (0) 12949 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_GET(word) \ 12950 (((word) & HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S) 12951 12952 12953 #define HTT_CHAN_INFO_PHY_MODE_SET(word, value) \ 12954 do { \ 12955 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PHY_MODE, value); \ 12956 (word) |= (value) << HTT_CHAN_INFO_PHY_MODE_S; \ 12957 } while (0) 12958 #define HTT_CHAN_INFO_PHY_MODE_GET(word) \ 12959 (((word) & HTT_CHAN_INFO_PHY_MODE_M) >> HTT_CHAN_INFO_PHY_MODE_S) 12960 12961 /* 12962 * @brief target -> host message definition for FW offloaded pkts 12963 * 12964 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND 12965 * 12966 * @details 12967 * The following field definitions describe the format of the firmware 12968 * offload deliver message sent from the target to the host. 12969 * 12970 * definition for struct htt_tx_offload_deliver_ind_hdr_t 12971 * 12972 * |31 20|19 16|15 13|12 8|7 5|4|3|2 0| 12973 * |----------------------------+--------+-----+---------------+-----+-+-+----| 12974 * | reserved_1 | msg type | 12975 * |--------------------------------------------------------------------------| 12976 * | phy_timestamp_l32 | 12977 * |--------------------------------------------------------------------------| 12978 * | WORD2 (see below) | 12979 * |--------------------------------------------------------------------------| 12980 * | seqno | framectrl | 12981 * |--------------------------------------------------------------------------| 12982 * | reserved_3 | vdev_id | tid_num| 12983 * |--------------------------------------------------------------------------| 12984 * | reserved_4 | tx_mpdu_bytes |F|STAT| 12985 * |--------------------------------------------------------------------------| 12986 * 12987 * where: 12988 * STAT = status 12989 * F = format (802.3 vs. 802.11) 12990 * 12991 * definition for word 2 12992 * 12993 * |31 26|25| 24 |23 | 22 |21 19|18 17|16 9|8 6|5 2|1 0| 12994 * |--------+--+----+---+----+-----+-----+---------------------+----+-----+---| 12995 * |reserv_2|BF|LDPC|SGI|STBC| BW | NSS | RSSI |RATE| MCS |PR | 12996 * |--------------------------------------------------------------------------| 12997 * 12998 * where: 12999 * PR = preamble 13000 * BF = beamformed 13001 */ 13002 13003 PREPACK struct htt_tx_offload_deliver_ind_hdr_t 13004 { 13005 A_UINT32 /* word 0 */ 13006 msg_type:8, /* [ 7: 0] */ 13007 reserved_1:24; /* [31: 8] */ 13008 A_UINT32 phy_timestamp_l32; /* word 1 [31:0] */ 13009 A_UINT32 /* word 2 */ 13010 /* preamble: 13011 * 0-OFDM, 13012 * 1-CCk, 13013 * 2-HT, 13014 * 3-VHT 13015 */ 13016 preamble: 2, /* [1:0] */ 13017 /* mcs: 13018 * In case of HT preamble interpret 13019 * MCS along with NSS. 13020 * Valid values for HT are 0 to 7. 13021 * HT mcs 0 with NSS 2 is mcs 8. 13022 * Valid values for VHT are 0 to 9. 13023 */ 13024 mcs: 4, /* [5:2] */ 13025 /* rate: 13026 * This is applicable only for 13027 * CCK and OFDM preamble type 13028 * rate 0: OFDM 48 Mbps, 13029 * 1: OFDM 24 Mbps, 13030 * 2: OFDM 12 Mbps 13031 * 3: OFDM 6 Mbps 13032 * 4: OFDM 54 Mbps 13033 * 5: OFDM 36 Mbps 13034 * 6: OFDM 18 Mbps 13035 * 7: OFDM 9 Mbps 13036 * rate 0: CCK 11 Mbps Long 13037 * 1: CCK 5.5 Mbps Long 13038 * 2: CCK 2 Mbps Long 13039 * 3: CCK 1 Mbps Long 13040 * 4: CCK 11 Mbps Short 13041 * 5: CCK 5.5 Mbps Short 13042 * 6: CCK 2 Mbps Short 13043 */ 13044 rate : 3, /* [ 8: 6] */ 13045 rssi : 8, /* [16: 9] units=dBm */ 13046 nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */ 13047 bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */ 13048 stbc : 1, /* [22] */ 13049 sgi : 1, /* [23] */ 13050 ldpc : 1, /* [24] */ 13051 beamformed: 1, /* [25] */ 13052 reserved_2: 6; /* [31:26] */ 13053 A_UINT32 /* word 3 */ 13054 framectrl:16, /* [15: 0] */ 13055 seqno:16; /* [31:16] */ 13056 A_UINT32 /* word 4 */ 13057 tid_num:5, /* [ 4: 0] actual TID number */ 13058 vdev_id:8, /* [12: 5] */ 13059 reserved_3:19; /* [31:13] */ 13060 A_UINT32 /* word 5 */ 13061 /* status: 13062 * 0: tx_ok 13063 * 1: retry 13064 * 2: drop 13065 * 3: filtered 13066 * 4: abort 13067 * 5: tid delete 13068 * 6: sw abort 13069 * 7: dropped by peer migration 13070 */ 13071 status:3, /* [2:0] */ 13072 format:1, /* [3] 0: 802.3 format, 1: 802.11 format */ 13073 tx_mpdu_bytes:16, /* [19:4] */ 13074 /* Indicates retry count of offloaded/local generated Data tx frames */ 13075 tx_retry_cnt:6, /* [25:20] */ 13076 reserved_4:6; /* [31:26] */ 13077 } POSTPACK; 13078 13079 /* FW offload deliver ind message header fields */ 13080 13081 /* DWORD one */ 13082 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M 0xffffffff 13083 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S 0 13084 13085 /* DWORD two */ 13086 #define HTT_FW_OFFLOAD_IND_PREAMBLE_M 0x00000003 13087 #define HTT_FW_OFFLOAD_IND_PREAMBLE_S 0 13088 #define HTT_FW_OFFLOAD_IND_MCS_M 0x0000003c 13089 #define HTT_FW_OFFLOAD_IND_MCS_S 2 13090 #define HTT_FW_OFFLOAD_IND_RATE_M 0x000001c0 13091 #define HTT_FW_OFFLOAD_IND_RATE_S 6 13092 #define HTT_FW_OFFLOAD_IND_RSSI_M 0x0001fe00 13093 #define HTT_FW_OFFLOAD_IND_RSSI_S 9 13094 #define HTT_FW_OFFLOAD_IND_NSS_M 0x00060000 13095 #define HTT_FW_OFFLOAD_IND_NSS_S 17 13096 #define HTT_FW_OFFLOAD_IND_BW_M 0x00380000 13097 #define HTT_FW_OFFLOAD_IND_BW_S 19 13098 #define HTT_FW_OFFLOAD_IND_STBC_M 0x00400000 13099 #define HTT_FW_OFFLOAD_IND_STBC_S 22 13100 #define HTT_FW_OFFLOAD_IND_SGI_M 0x00800000 13101 #define HTT_FW_OFFLOAD_IND_SGI_S 23 13102 #define HTT_FW_OFFLOAD_IND_LDPC_M 0x01000000 13103 #define HTT_FW_OFFLOAD_IND_LDPC_S 24 13104 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_M 0x02000000 13105 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_S 25 13106 13107 /* DWORD three*/ 13108 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_M 0x0000ffff 13109 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_S 0 13110 #define HTT_FW_OFFLOAD_IND_SEQNO_M 0xffff0000 13111 #define HTT_FW_OFFLOAD_IND_SEQNO_S 16 13112 13113 /* DWORD four */ 13114 #define HTT_FW_OFFLOAD_IND_TID_NUM_M 0x0000001f 13115 #define HTT_FW_OFFLOAD_IND_TID_NUM_S 0 13116 #define HTT_FW_OFFLOAD_IND_VDEV_ID_M 0x00001fe0 13117 #define HTT_FW_OFFLOAD_IND_VDEV_ID_S 5 13118 13119 /* DWORD five */ 13120 #define HTT_FW_OFFLOAD_IND_STATUS_M 0x00000007 13121 #define HTT_FW_OFFLOAD_IND_STATUS_S 0 13122 #define HTT_FW_OFFLOAD_IND_FORMAT_M 0x00000008 13123 #define HTT_FW_OFFLOAD_IND_FORMAT_S 3 13124 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M 0x000ffff0 13125 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S 4 13126 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M 0x03f00000 13127 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S 20 13128 13129 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_SET(word, value) \ 13130 do { \ 13131 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32, value); \ 13132 (word) |= (value) << HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S; \ 13133 } while (0) 13134 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_GET(word) \ 13135 (((word) & HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M) >> HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S) 13136 13137 #define HTT_FW_OFFLOAD_IND_PREAMBLE_SET(word, value) \ 13138 do { \ 13139 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PREAMBLE, value); \ 13140 (word) |= (value) << HTT_FW_OFFLOAD_IND_PREAMBLE_S; \ 13141 } while (0) 13142 #define HTT_FW_OFFLOAD_IND_PREAMBLE_GET(word) \ 13143 (((word) & HTT_FW_OFFLOAD_IND_PREAMBLE_M) >> HTT_FW_OFFLOAD_IND_PREAMBLE_S) 13144 13145 #define HTT_FW_OFFLOAD_IND_MCS_SET(word, value) \ 13146 do { \ 13147 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_MCS, value); \ 13148 (word) |= (value) << HTT_FW_OFFLOAD_IND_MCS_S; \ 13149 } while (0) 13150 #define HTT_FW_OFFLOAD_IND_MCS_GET(word) \ 13151 (((word) & HTT_FW_OFFLOAD_IND_MCS_M) >> HTT_FW_OFFLOAD_IND_MCS_S) 13152 13153 #define HTT_FW_OFFLOAD_IND_RATE_SET(word, value) \ 13154 do { \ 13155 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RATE, value); \ 13156 (word) |= (value) << HTT_FW_OFFLOAD_IND_RATE_S; \ 13157 } while (0) 13158 #define HTT_FW_OFFLOAD_IND_RATE_GET(word) \ 13159 (((word) & HTT_FW_OFFLOAD_IND_RATE_M) >> HTT_FW_OFFLOAD_IND_RATE_S) 13160 13161 #define HTT_FW_OFFLOAD_IND_RSSI_SET(word, value) \ 13162 do { \ 13163 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RSSI, value); \ 13164 (word) |= (value) << HTT_FW_OFFLOAD_IND_RSSI_S; \ 13165 } while (0) 13166 #define HTT_FW_OFFLOAD_IND_RSSI_GET(word) \ 13167 (((word) & HTT_FW_OFFLOAD_IND_RSSI_M) >> HTT_FW_OFFLOAD_IND_RSSI_S) 13168 13169 13170 #define HTT_FW_OFFLOAD_IND_NSS_SET(word, value) \ 13171 do { \ 13172 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_NSS, value); \ 13173 (word) |= (value) << HTT_FW_OFFLOAD_IND_NSS_S; \ 13174 } while (0) 13175 #define HTT_FW_OFFLOAD_IND_NSS_GET(word) \ 13176 (((word) & HTT_FW_OFFLOAD_IND_NSS_M) >> HTT_FW_OFFLOAD_IND_NSS_S) 13177 13178 #define HTT_FW_OFFLOAD_IND_BW_SET(word, value) \ 13179 do { \ 13180 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BW, value); \ 13181 (word) |= (value) << HTT_FW_OFFLOAD_IND_BW_S; \ 13182 } while (0) 13183 #define HTT_FW_OFFLOAD_IND_BW_GET(word) \ 13184 (((word) & HTT_FW_OFFLOAD_IND_BW_M) >> HTT_FW_OFFLOAD_IND_BW_S) 13185 13186 13187 #define HTT_FW_OFFLOAD_IND_STBC_SET(word, value) \ 13188 do { \ 13189 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STBC, value); \ 13190 (word) |= (value) << HTT_FW_OFFLOAD_IND_STBC_S; \ 13191 } while (0) 13192 #define HTT_FW_OFFLOAD_IND_STBC_GET(word) \ 13193 (((word) & HTT_FW_OFFLOAD_IND_STBC_M) >> HTT_FW_OFFLOAD_IND_STBC_S) 13194 13195 13196 #define HTT_FW_OFFLOAD_IND_SGI_SET(word, value) \ 13197 do { \ 13198 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SGI, value); \ 13199 (word) |= (value) << HTT_FW_OFFLOAD_IND_SGI_S; \ 13200 } while (0) 13201 #define HTT_FW_OFFLOAD_IND_SGI_GET(word) \ 13202 (((word) & HTT_FW_OFFLOAD_IND_SGI_M) >> HTT_FW_OFFLOAD_IND_SGI_S) 13203 13204 #define HTT_FW_OFFLOAD_IND_LDPC_SET(word, value) \ 13205 do { \ 13206 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_LDPC, value); \ 13207 (word) |= (value) << HTT_FW_OFFLOAD_IND_LDPC_S; \ 13208 } while (0) 13209 #define HTT_FW_OFFLOAD_IND_LDPC_GET(word) \ 13210 (((word) & HTT_FW_OFFLOAD_IND_LDPC_M) >> HTT_FW_OFFLOAD_IND_LDPC_S) 13211 13212 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_SET(word, value) \ 13213 do { \ 13214 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BEAMFORMED, value); \ 13215 (word) |= (value) << HTT_FW_OFFLOAD_IND_BEAMFORMED_S; \ 13216 } while (0) 13217 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_GET(word) \ 13218 (((word) & HTT_FW_OFFLOAD_IND_BEAMFORMED_M) >> HTT_FW_OFFLOAD_IND_BEAMFORMED_S) 13219 13220 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_SET(word, value) \ 13221 do { \ 13222 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FRAMECTRL, value); \ 13223 (word) |= (value) << HTT_FW_OFFLOAD_IND_FRAMECTRL_S; \ 13224 } while (0) 13225 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_GET(word) \ 13226 (((word) & HTT_FW_OFFLOAD_IND_FRAMECTRL_M) >> HTT_FW_OFFLOAD_IND_FRAMECTRL_S) 13227 13228 13229 #define HTT_FW_OFFLOAD_IND_SEQNO_SET(word, value) \ 13230 do { \ 13231 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SEQNO, value); \ 13232 (word) |= (value) << HTT_FW_OFFLOAD_IND_SEQNO_S; \ 13233 } while (0) 13234 #define HTT_FW_OFFLOAD_IND_SEQNO_GET(word) \ 13235 (((word) & HTT_FW_OFFLOAD_IND_SEQNO_M) >> HTT_FW_OFFLOAD_IND_SEQNO_S) 13236 13237 #define HTT_FW_OFFLOAD_IND_TID_NUM_SET(word, value) \ 13238 do { \ 13239 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TID_NUM, value); \ 13240 (word) |= (value) << HTT_FW_OFFLOAD_IND_TID_NUM_S; \ 13241 } while (0) 13242 #define HTT_FW_OFFLOAD_IND_TID_NUM_GET(word) \ 13243 (((word) & HTT_FW_OFFLOAD_IND_TID_NUM_M) >> HTT_FW_OFFLOAD_IND_TID_NUM_S) 13244 13245 #define HTT_FW_OFFLOAD_IND_VDEV_ID_SET(word, value) \ 13246 do { \ 13247 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_VDEV_ID, value); \ 13248 (word) |= (value) << HTT_FW_OFFLOAD_IND_VDEV_ID_S; \ 13249 } while (0) 13250 #define HTT_FW_OFFLOAD_IND_VDEV_ID_GET(word) \ 13251 (((word) & HTT_FW_OFFLOAD_IND_VDEV_ID_M) >> HTT_FW_OFFLOAD_IND_VDEV_ID_S) 13252 13253 #define HTT_FW_OFFLOAD_IND_STATUS_SET(word, value) \ 13254 do { \ 13255 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STATUS, value); \ 13256 (word) |= (value) << HTT_FW_OFFLOAD_IND_STATUS_S; \ 13257 } while (0) 13258 #define HTT_FW_OFFLOAD_IND_STATUS_GET(word) \ 13259 (((word) & HTT_FW_OFFLOAD_IND_STATUS_M) >> HTT_FW_OFFLOAD_IND_STATUS_M) 13260 13261 13262 #define HTT_FW_OFFLOAD_IND_FORMAT_SET(word, value) \ 13263 do { \ 13264 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FORMAT, value); \ 13265 (word) |= (value) << HTT_FW_OFFLOAD_IND_FORMAT_S; \ 13266 } while (0) 13267 #define HTT_FW_OFFLOAD_IND_FORMAT_GET(word) \ 13268 (((word) & HTT_FW_OFFLOAD_IND_FORMAT_M) >> HTT_FW_OFFLOAD_IND_FORMAT_S) 13269 13270 13271 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_SET(word, value) \ 13272 do { \ 13273 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES, value); \ 13274 (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S; \ 13275 } while (0) 13276 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_GET(word) \ 13277 (((word) & HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M) >> HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S) 13278 13279 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_SET(word, value) \ 13280 do { \ 13281 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_RETRY_CNT, value); \ 13282 (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S; \ 13283 } while (0) 13284 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_GET(word) \ 13285 (((word) & HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M) >> HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S) 13286 13287 13288 /* 13289 * @brief target -> host rx reorder flush message definition 13290 * 13291 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FLUSH 13292 * 13293 * @details 13294 * The following field definitions describe the format of the rx flush 13295 * message sent from the target to the host. 13296 * The message consists of a 4-octet header, followed by one or more 13297 * 4-octet payload information elements. 13298 * 13299 * |31 24|23 8|7 0| 13300 * |--------------------------------------------------------------| 13301 * | TID | peer ID | msg type | 13302 * |--------------------------------------------------------------| 13303 * | seq num end | seq num start | MPDU status | reserved | 13304 * |--------------------------------------------------------------| 13305 * First DWORD: 13306 * - MSG_TYPE 13307 * Bits 7:0 13308 * Purpose: identifies this as an rx flush message 13309 * Value: 0x2 (HTT_T2H_MSG_TYPE_RX_FLUSH) 13310 * - PEER_ID 13311 * Bits 23:8 (only bits 18:8 actually used) 13312 * Purpose: identify which peer's rx data is being flushed 13313 * Value: (rx) peer ID 13314 * - TID 13315 * Bits 31:24 (only bits 27:24 actually used) 13316 * Purpose: Specifies which traffic identifier's rx data is being flushed 13317 * Value: traffic identifier 13318 * Second DWORD: 13319 * - MPDU_STATUS 13320 * Bits 15:8 13321 * Purpose: 13322 * Indicate whether the flushed MPDUs should be discarded or processed. 13323 * Value: 13324 * 0x1: send the MPDUs from the rx reorder buffer to subsequent 13325 * stages of rx processing 13326 * other: discard the MPDUs 13327 * It is anticipated that flush messages will always have 13328 * MPDU status == 1, but the status flag is included for 13329 * flexibility. 13330 * - SEQ_NUM_START 13331 * Bits 23:16 13332 * Purpose: 13333 * Indicate the start of a series of consecutive MPDUs being flushed. 13334 * Not all MPDUs within this range are necessarily valid - the host 13335 * must check each sequence number within this range to see if the 13336 * corresponding MPDU is actually present. 13337 * Value: 13338 * The sequence number for the first MPDU in the sequence. 13339 * This sequence number is the 6 LSBs of the 802.11 sequence number. 13340 * - SEQ_NUM_END 13341 * Bits 30:24 13342 * Purpose: 13343 * Indicate the end of a series of consecutive MPDUs being flushed. 13344 * Value: 13345 * The sequence number one larger than the sequence number of the 13346 * last MPDU being flushed. 13347 * This sequence number is the 6 LSBs of the 802.11 sequence number. 13348 * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] inclusive 13349 * are to be released for further rx processing. 13350 * Not all MPDUs within this range are necessarily valid - the host 13351 * must check each sequence number within this range to see if the 13352 * corresponding MPDU is actually present. 13353 */ 13354 /* first DWORD */ 13355 #define HTT_RX_FLUSH_PEER_ID_M 0xffff00 13356 #define HTT_RX_FLUSH_PEER_ID_S 8 13357 #define HTT_RX_FLUSH_TID_M 0xff000000 13358 #define HTT_RX_FLUSH_TID_S 24 13359 /* second DWORD */ 13360 #define HTT_RX_FLUSH_MPDU_STATUS_M 0x0000ff00 13361 #define HTT_RX_FLUSH_MPDU_STATUS_S 8 13362 #define HTT_RX_FLUSH_SEQ_NUM_START_M 0x00ff0000 13363 #define HTT_RX_FLUSH_SEQ_NUM_START_S 16 13364 #define HTT_RX_FLUSH_SEQ_NUM_END_M 0xff000000 13365 #define HTT_RX_FLUSH_SEQ_NUM_END_S 24 13366 13367 #define HTT_RX_FLUSH_BYTES 8 13368 13369 #define HTT_RX_FLUSH_PEER_ID_SET(word, value) \ 13370 do { \ 13371 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_PEER_ID, value); \ 13372 (word) |= (value) << HTT_RX_FLUSH_PEER_ID_S; \ 13373 } while (0) 13374 #define HTT_RX_FLUSH_PEER_ID_GET(word) \ 13375 (((word) & HTT_RX_FLUSH_PEER_ID_M) >> HTT_RX_FLUSH_PEER_ID_S) 13376 13377 #define HTT_RX_FLUSH_TID_SET(word, value) \ 13378 do { \ 13379 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_TID, value); \ 13380 (word) |= (value) << HTT_RX_FLUSH_TID_S; \ 13381 } while (0) 13382 #define HTT_RX_FLUSH_TID_GET(word) \ 13383 (((word) & HTT_RX_FLUSH_TID_M) >> HTT_RX_FLUSH_TID_S) 13384 13385 #define HTT_RX_FLUSH_MPDU_STATUS_SET(word, value) \ 13386 do { \ 13387 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_MPDU_STATUS, value); \ 13388 (word) |= (value) << HTT_RX_FLUSH_MPDU_STATUS_S; \ 13389 } while (0) 13390 #define HTT_RX_FLUSH_MPDU_STATUS_GET(word) \ 13391 (((word) & HTT_RX_FLUSH_MPDU_STATUS_M) >> HTT_RX_FLUSH_MPDU_STATUS_S) 13392 13393 #define HTT_RX_FLUSH_SEQ_NUM_START_SET(word, value) \ 13394 do { \ 13395 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_START, value); \ 13396 (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_START_S; \ 13397 } while (0) 13398 #define HTT_RX_FLUSH_SEQ_NUM_START_GET(word) \ 13399 (((word) & HTT_RX_FLUSH_SEQ_NUM_START_M) >> HTT_RX_FLUSH_SEQ_NUM_START_S) 13400 13401 #define HTT_RX_FLUSH_SEQ_NUM_END_SET(word, value) \ 13402 do { \ 13403 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_END, value); \ 13404 (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_END_S; \ 13405 } while (0) 13406 #define HTT_RX_FLUSH_SEQ_NUM_END_GET(word) \ 13407 (((word) & HTT_RX_FLUSH_SEQ_NUM_END_M) >> HTT_RX_FLUSH_SEQ_NUM_END_S) 13408 13409 /* 13410 * @brief target -> host rx pn check indication message 13411 * 13412 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_PN_IND 13413 * 13414 * @details 13415 * The following field definitions describe the format of the Rx PN check 13416 * indication message sent from the target to the host. 13417 * The message consists of a 4-octet header, followed by the start and 13418 * end sequence numbers to be released, followed by the PN IEs. Each PN 13419 * IE is one octet containing the sequence number that failed the PN 13420 * check. 13421 * 13422 * |31 24|23 8|7 0| 13423 * |--------------------------------------------------------------| 13424 * | TID | peer ID | msg type | 13425 * |--------------------------------------------------------------| 13426 * | Reserved | PN IE count | seq num end | seq num start| 13427 * |--------------------------------------------------------------| 13428 * l : PN IE 2 | PN IE 1 | PN IE 0 | 13429 * |--------------------------------------------------------------| 13430 13431 * First DWORD: 13432 * - MSG_TYPE 13433 * Bits 7:0 13434 * Purpose: Identifies this as an rx pn check indication message 13435 * Value: 0x10 (HTT_T2H_MSG_TYPE_RX_PN_IND) 13436 * - PEER_ID 13437 * Bits 23:8 (only bits 18:8 actually used) 13438 * Purpose: identify which peer 13439 * Value: (rx) peer ID 13440 * - TID 13441 * Bits 31:24 (only bits 27:24 actually used) 13442 * Purpose: identify traffic identifier 13443 * Value: traffic identifier 13444 * Second DWORD: 13445 * - SEQ_NUM_START 13446 * Bits 7:0 13447 * Purpose: 13448 * Indicates the starting sequence number of the MPDU in this 13449 * series of MPDUs that went though PN check. 13450 * Value: 13451 * The sequence number for the first MPDU in the sequence. 13452 * This sequence number is the 6 LSBs of the 802.11 sequence number. 13453 * - SEQ_NUM_END 13454 * Bits 15:8 13455 * Purpose: 13456 * Indicates the ending sequence number of the MPDU in this 13457 * series of MPDUs that went though PN check. 13458 * Value: 13459 * The sequence number one larger then the sequence number of the last 13460 * MPDU being flushed. 13461 * This sequence number is the 6 LSBs of the 802.11 sequence number. 13462 * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] have been checked 13463 * for invalid PN numbers and are ready to be released for further processing. 13464 * Not all MPDUs within this range are necessarily valid - the host 13465 * must check each sequence number within this range to see if the 13466 * corresponding MPDU is actually present. 13467 * - PN_IE_COUNT 13468 * Bits 23:16 13469 * Purpose: 13470 * Used to determine the variable number of PN information elements in this 13471 * message 13472 * 13473 * PN information elements: 13474 * - PN_IE_x- 13475 * Purpose: 13476 * Each PN information element contains the sequence number of the MPDU that 13477 * has failed the target PN check. 13478 * Value: 13479 * Contains the 6 LSBs of the 802.11 sequence number corresponding to the MPDU 13480 * that failed the PN check. 13481 */ 13482 /* first DWORD */ 13483 #define HTT_RX_PN_IND_PEER_ID_M 0xffff00 13484 #define HTT_RX_PN_IND_PEER_ID_S 8 13485 #define HTT_RX_PN_IND_TID_M 0xff000000 13486 #define HTT_RX_PN_IND_TID_S 24 13487 /* second DWORD */ 13488 #define HTT_RX_PN_IND_SEQ_NUM_START_M 0x000000ff 13489 #define HTT_RX_PN_IND_SEQ_NUM_START_S 0 13490 #define HTT_RX_PN_IND_SEQ_NUM_END_M 0x0000ff00 13491 #define HTT_RX_PN_IND_SEQ_NUM_END_S 8 13492 #define HTT_RX_PN_IND_PN_IE_CNT_M 0x00ff0000 13493 #define HTT_RX_PN_IND_PN_IE_CNT_S 16 13494 13495 #define HTT_RX_PN_IND_BYTES 8 13496 13497 #define HTT_RX_PN_IND_PEER_ID_SET(word, value) \ 13498 do { \ 13499 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PEER_ID, value); \ 13500 (word) |= (value) << HTT_RX_PN_IND_PEER_ID_S; \ 13501 } while (0) 13502 #define HTT_RX_PN_IND_PEER_ID_GET(word) \ 13503 (((word) & HTT_RX_PN_IND_PEER_ID_M) >> HTT_RX_PN_IND_PEER_ID_S) 13504 13505 #define HTT_RX_PN_IND_EXT_TID_SET(word, value) \ 13506 do { \ 13507 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_TID, value); \ 13508 (word) |= (value) << HTT_RX_PN_IND_TID_S; \ 13509 } while (0) 13510 #define HTT_RX_PN_IND_EXT_TID_GET(word) \ 13511 (((word) & HTT_RX_PN_IND_TID_M) >> HTT_RX_PN_IND_TID_S) 13512 13513 #define HTT_RX_PN_IND_SEQ_NUM_START_SET(word, value) \ 13514 do { \ 13515 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_START, value); \ 13516 (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_START_S; \ 13517 } while (0) 13518 #define HTT_RX_PN_IND_SEQ_NUM_START_GET(word) \ 13519 (((word) & HTT_RX_PN_IND_SEQ_NUM_START_M) >> HTT_RX_PN_IND_SEQ_NUM_START_S) 13520 13521 #define HTT_RX_PN_IND_SEQ_NUM_END_SET(word, value) \ 13522 do { \ 13523 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_END, value); \ 13524 (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_END_S; \ 13525 } while (0) 13526 #define HTT_RX_PN_IND_SEQ_NUM_END_GET(word) \ 13527 (((word) & HTT_RX_PN_IND_SEQ_NUM_END_M) >> HTT_RX_PN_IND_SEQ_NUM_END_S) 13528 13529 #define HTT_RX_PN_IND_PN_IE_CNT_SET(word, value) \ 13530 do { \ 13531 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PN_IE_CNT, value); \ 13532 (word) |= (value) << HTT_RX_PN_IND_PN_IE_CNT_S; \ 13533 } while (0) 13534 #define HTT_RX_PN_IND_PN_IE_CNT_GET(word) \ 13535 (((word) & HTT_RX_PN_IND_PN_IE_CNT_M) >> HTT_RX_PN_IND_PN_IE_CNT_S) 13536 13537 /* 13538 * @brief target -> host rx offload deliver message for LL system 13539 * 13540 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND 13541 * 13542 * @details 13543 * In a low latency system this message is sent whenever the offload 13544 * manager flushes out the packets it has coalesced in its coalescing buffer. 13545 * The DMA of the actual packets into host memory is done before sending out 13546 * this message. This message indicates only how many MSDUs to reap. The 13547 * peer ID, vdev ID, tid and MSDU length are copied inline into the header 13548 * portion of the MSDU while DMA'ing into the host memory. Unlike the packets 13549 * DMA'd by the MAC directly into host memory these packets do not contain 13550 * the MAC descriptors in the header portion of the packet. Instead they contain 13551 * the peer ID, vdev ID, tid and MSDU length. Also when the host receives this 13552 * message, the packets are delivered directly to the NW stack without going 13553 * through the regular reorder buffering and PN checking path since it has 13554 * already been done in target. 13555 * 13556 * |31 24|23 16|15 8|7 0| 13557 * |-----------------------------------------------------------------------| 13558 * | Total MSDU count | reserved | msg type | 13559 * |-----------------------------------------------------------------------| 13560 * 13561 * @brief target -> host rx offload deliver message for HL system 13562 * 13563 * @details 13564 * In a high latency system this message is sent whenever the offload manager 13565 * flushes out the packets it has coalesced in its coalescing buffer. The 13566 * actual packets are also carried along with this message. When the host 13567 * receives this message, it is expected to deliver these packets to the NW 13568 * stack directly instead of routing them through the reorder buffering and 13569 * PN checking path since it has already been done in target. 13570 * 13571 * |31 24|23 16|15 8|7 0| 13572 * |-----------------------------------------------------------------------| 13573 * | Total MSDU count | reserved | msg type | 13574 * |-----------------------------------------------------------------------| 13575 * | peer ID | MSDU length | 13576 * |-----------------------------------------------------------------------| 13577 * | MSDU payload | FW Desc | tid | vdev ID | 13578 * |-----------------------------------------------------------------------| 13579 * | MSDU payload contd. | 13580 * |-----------------------------------------------------------------------| 13581 * | peer ID | MSDU length | 13582 * |-----------------------------------------------------------------------| 13583 * | MSDU payload | FW Desc | tid | vdev ID | 13584 * |-----------------------------------------------------------------------| 13585 * | MSDU payload contd. | 13586 * |-----------------------------------------------------------------------| 13587 * 13588 */ 13589 /* first DWORD */ 13590 #define HTT_RX_OFFLOAD_DELIVER_IND_HDR_BYTES 4 13591 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_HDR_BYTES 7 13592 13593 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M 0xffff0000 13594 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S 16 13595 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M 0x0000ffff 13596 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S 0 13597 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M 0xffff0000 13598 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S 16 13599 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M 0x000000ff 13600 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S 0 13601 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M 0x0000ff00 13602 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S 8 13603 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M 0x00ff0000 13604 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S 16 13605 13606 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_GET(word) \ 13607 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S) 13608 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_SET(word, value) \ 13609 do { \ 13610 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT, value); \ 13611 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S; \ 13612 } while (0) 13613 13614 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_GET(word) \ 13615 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S) 13616 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_SET(word, value) \ 13617 do { \ 13618 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN, value); \ 13619 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S; \ 13620 } while (0) 13621 13622 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_GET(word) \ 13623 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S) 13624 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_SET(word, value) \ 13625 do { \ 13626 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID, value); \ 13627 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S; \ 13628 } while (0) 13629 13630 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_GET(word) \ 13631 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S) 13632 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_SET(word, value) \ 13633 do { \ 13634 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID, value); \ 13635 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S; \ 13636 } while (0) 13637 13638 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_GET(word) \ 13639 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S) 13640 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_SET(word, value) \ 13641 do { \ 13642 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID, value); \ 13643 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S; \ 13644 } while (0) 13645 13646 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_GET(word) \ 13647 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S) 13648 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_SET(word, value) \ 13649 do { \ 13650 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC, value); \ 13651 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S; \ 13652 } while (0) 13653 13654 /** 13655 * @brief target -> host rx peer map/unmap message definition 13656 * 13657 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP 13658 * 13659 * @details 13660 * The following diagram shows the format of the rx peer map message sent 13661 * from the target to the host. This layout assumes the target operates 13662 * as little-endian. 13663 * 13664 * This message always contains a SW peer ID. The main purpose of the 13665 * SW peer ID is to tell the host what peer ID rx packets will be tagged 13666 * with, so that the host can use that peer ID to determine which peer 13667 * transmitted the rx frame. This SW peer ID is sometimes also used for 13668 * other purposes, such as identifying during tx completions which peer 13669 * the tx frames in question were transmitted to. 13670 * 13671 * In certain generations of chips, the peer map message also contains 13672 * a HW peer ID. This HW peer ID is used during rx --> tx frame forwarding 13673 * to identify which peer the frame needs to be forwarded to (i.e. the 13674 * peer associated with the Destination MAC Address within the packet), 13675 * and particularly which vdev needs to transmit the frame (for cases 13676 * of inter-vdev rx --> tx forwarding). The HW peer id here is the same 13677 * meaning as AST_INDEX_0. 13678 * This DA-based peer ID that is provided for certain rx frames 13679 * (the rx frames that need to be re-transmitted as tx frames) 13680 * is the ID that the HW uses for referring to the peer in question, 13681 * rather than the peer ID that the SW+FW use to refer to the peer. 13682 * 13683 * 13684 * |31 24|23 16|15 8|7 0| 13685 * |-----------------------------------------------------------------------| 13686 * | SW peer ID | VDEV ID | msg type | 13687 * |-----------------------------------------------------------------------| 13688 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13689 * |-----------------------------------------------------------------------| 13690 * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 | 13691 * |-----------------------------------------------------------------------| 13692 * 13693 * 13694 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP 13695 * 13696 * The following diagram shows the format of the rx peer unmap message sent 13697 * from the target to the host. 13698 * 13699 * |31 24|23 16|15 8|7 0| 13700 * |-----------------------------------------------------------------------| 13701 * | SW peer ID | VDEV ID | msg type | 13702 * |-----------------------------------------------------------------------| 13703 * 13704 * The following field definitions describe the format of the rx peer map 13705 * and peer unmap messages sent from the target to the host. 13706 * - MSG_TYPE 13707 * Bits 7:0 13708 * Purpose: identifies this as an rx peer map or peer unmap message 13709 * Value: peer map -> 0x3 (HTT_T2H_MSG_TYPE_PEER_MAP), 13710 * peer unmap -> 0x4 (HTT_T2H_MSG_TYPE_PEER_UNMAP) 13711 * - VDEV_ID 13712 * Bits 15:8 13713 * Purpose: Indicates which virtual device the peer is associated 13714 * with. 13715 * Value: vdev ID (used in the host to look up the vdev object) 13716 * - PEER_ID (a.k.a. SW_PEER_ID) 13717 * Bits 31:16 13718 * Purpose: The peer ID (index) that WAL is allocating (map) or 13719 * freeing (unmap) 13720 * Value: (rx) peer ID 13721 * - MAC_ADDR_L32 (peer map only) 13722 * Bits 31:0 13723 * Purpose: Identifies which peer node the peer ID is for. 13724 * Value: lower 4 bytes of peer node's MAC address 13725 * - MAC_ADDR_U16 (peer map only) 13726 * Bits 15:0 13727 * Purpose: Identifies which peer node the peer ID is for. 13728 * Value: upper 2 bytes of peer node's MAC address 13729 * - HW_PEER_ID 13730 * Bits 31:16 13731 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13732 * address, so for rx frames marked for rx --> tx forwarding, the 13733 * host can determine from the HW peer ID provided as meta-data with 13734 * the rx frame which peer the frame is supposed to be forwarded to. 13735 * Value: ID used by the MAC HW to identify the peer 13736 */ 13737 #define HTT_RX_PEER_MAP_VDEV_ID_M 0xff00 13738 #define HTT_RX_PEER_MAP_VDEV_ID_S 8 13739 #define HTT_RX_PEER_MAP_PEER_ID_M 0xffff0000 13740 #define HTT_RX_PEER_MAP_PEER_ID_S 16 13741 #define HTT_RX_PEER_MAP_SW_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M /* alias */ 13742 #define HTT_RX_PEER_MAP_SW_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S /* alias */ 13743 #define HTT_RX_PEER_MAP_MAC_ADDR_L32_M 0xffffffff 13744 #define HTT_RX_PEER_MAP_MAC_ADDR_L32_S 0 13745 #define HTT_RX_PEER_MAP_MAC_ADDR_U16_M 0xffff 13746 #define HTT_RX_PEER_MAP_MAC_ADDR_U16_S 0 13747 #define HTT_RX_PEER_MAP_HW_PEER_ID_M 0xffff0000 13748 #define HTT_RX_PEER_MAP_HW_PEER_ID_S 16 13749 13750 #define HTT_RX_PEER_MAP_VAP_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET /* deprecated */ 13751 #define HTT_RX_PEER_MAP_VDEV_ID_SET(word, value) \ 13752 do { \ 13753 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_VDEV_ID, value); \ 13754 (word) |= (value) << HTT_RX_PEER_MAP_VDEV_ID_S; \ 13755 } while (0) 13756 #define HTT_RX_PEER_MAP_VAP_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET /* deprecated */ 13757 #define HTT_RX_PEER_MAP_VDEV_ID_GET(word) \ 13758 (((word) & HTT_RX_PEER_MAP_VDEV_ID_M) >> HTT_RX_PEER_MAP_VDEV_ID_S) 13759 13760 #define HTT_RX_PEER_MAP_PEER_ID_SET(word, value) \ 13761 do { \ 13762 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ 13763 (word) |= (value) << HTT_RX_PEER_MAP_PEER_ID_S; \ 13764 } while (0) 13765 #define HTT_RX_PEER_MAP_PEER_ID_GET(word) \ 13766 (((word) & HTT_RX_PEER_MAP_PEER_ID_M) >> HTT_RX_PEER_MAP_PEER_ID_S) 13767 #define HTT_RX_PEER_MAP_SW_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET /* alias */ 13768 #define HTT_RX_PEER_MAP_SW_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET /* alias */ 13769 13770 #define HTT_RX_PEER_MAP_HW_PEER_ID_SET(word, value) \ 13771 do { \ 13772 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_HW_PEER_ID, value); \ 13773 (word) |= (value) << HTT_RX_PEER_MAP_HW_PEER_ID_S; \ 13774 } while (0) 13775 #define HTT_RX_PEER_MAP_HW_PEER_ID_GET(word) \ 13776 (((word) & HTT_RX_PEER_MAP_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_HW_PEER_ID_S) 13777 13778 #define HTT_RX_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ 13779 #define HTT_RX_PEER_MAP_HW_PEER_ID_OFFSET 8 /* bytes */ 13780 13781 #define HTT_RX_PEER_MAP_BYTES 12 13782 13783 13784 #define HTT_RX_PEER_UNMAP_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M 13785 #define HTT_RX_PEER_UNMAP_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S 13786 #define HTT_RX_PEER_UNMAP_SW_PEER_ID_M HTT_RX_PEER_MAP_SW_PEER_ID_M 13787 #define HTT_RX_PEER_UNMAP_SW_PEER_ID_S HTT_RX_PEER_MAP_SW_PEER_ID_S 13788 13789 #define HTT_RX_PEER_UNMAP_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET 13790 #define HTT_RX_PEER_UNMAP_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET 13791 13792 #define HTT_RX_PEER_UNMAP_VDEV_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET 13793 #define HTT_RX_PEER_UNMAP_VDEV_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET 13794 13795 #define HTT_RX_PEER_UNMAP_BYTES 4 13796 13797 13798 /** 13799 * @brief target -> host rx peer map V2 message definition 13800 * 13801 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V2 13802 * 13803 * @details 13804 * The following diagram shows the format of the rx peer map v2 message sent 13805 * from the target to the host. This layout assumes the target operates 13806 * as little-endian. 13807 * 13808 * This message always contains a SW peer ID. The main purpose of the 13809 * SW peer ID is to tell the host what peer ID rx packets will be tagged 13810 * with, so that the host can use that peer ID to determine which peer 13811 * transmitted the rx frame. This SW peer ID is sometimes also used for 13812 * other purposes, such as identifying during tx completions which peer 13813 * the tx frames in question were transmitted to. 13814 * 13815 * The peer map v2 message also contains a HW peer ID. This HW peer ID 13816 * is used during rx --> tx frame forwarding to identify which peer the 13817 * frame needs to be forwarded to (i.e. the peer associated with the 13818 * Destination MAC Address within the packet), and particularly which vdev 13819 * needs to transmit the frame (for cases of inter-vdev rx --> tx forwarding). 13820 * This DA-based peer ID that is provided for certain rx frames 13821 * (the rx frames that need to be re-transmitted as tx frames) 13822 * is the ID that the HW uses for referring to the peer in question, 13823 * rather than the peer ID that the SW+FW use to refer to the peer. 13824 * 13825 * The HW peer id here is the same meaning as AST_INDEX_0. 13826 * Some chips support up to 4 AST indices per peer: AST_INDEX_0, AST_INDEX_1, 13827 * AST_INDEX_2, and AST_INDEX_3. AST 0 is always valid; for AST 1 through 13828 * AST 3, check the AST_VALID_MASK(3) to see if the corresponding extension 13829 * AST is valid. 13830 * 13831 * |31 28|27 24|23 21|20|19 17|16|15 8|7 0| 13832 * |-------------------------------------------------------------------------| 13833 * | SW peer ID | VDEV ID | msg type | 13834 * |-------------------------------------------------------------------------| 13835 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13836 * |-------------------------------------------------------------------------| 13837 * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 | 13838 * |-------------------------------------------------------------------------| 13839 * | Reserved_21_31 |OA|ASTVM|NH| AST Hash Value | 13840 * |-------------------------------------------------------------------------| 13841 * | ASTFM3 | ASTFM2 | ASTFM1 | ASTFM0 | AST index 1 | 13842 * |-------------------------------------------------------------------------| 13843 * |TID valid low pri| TID valid hi pri | AST index 2 | 13844 * |-------------------------------------------------------------------------| 13845 * | LMAC/PMAC_RXPCU AST index | AST index 3 | 13846 * |-------------------------------------------------------------------------| 13847 * | Reserved_2 | 13848 * |-------------------------------------------------------------------------| 13849 * Where: 13850 * NH = Next Hop 13851 * ASTVM = AST valid mask 13852 * OA = on-chip AST valid bit 13853 * ASTFM = AST flow mask 13854 * 13855 * The following field definitions describe the format of the rx peer map v2 13856 * messages sent from the target to the host. 13857 * - MSG_TYPE 13858 * Bits 7:0 13859 * Purpose: identifies this as an rx peer map v2 message 13860 * Value: peer map v2 -> 0x1e (HTT_T2H_MSG_TYPE_PEER_MAP_V2) 13861 * - VDEV_ID 13862 * Bits 15:8 13863 * Purpose: Indicates which virtual device the peer is associated with. 13864 * Value: vdev ID (used in the host to look up the vdev object) 13865 * - SW_PEER_ID 13866 * Bits 31:16 13867 * Purpose: The peer ID (index) that WAL is allocating 13868 * Value: (rx) peer ID 13869 * - MAC_ADDR_L32 13870 * Bits 31:0 13871 * Purpose: Identifies which peer node the peer ID is for. 13872 * Value: lower 4 bytes of peer node's MAC address 13873 * - MAC_ADDR_U16 13874 * Bits 15:0 13875 * Purpose: Identifies which peer node the peer ID is for. 13876 * Value: upper 2 bytes of peer node's MAC address 13877 * - HW_PEER_ID / AST_INDEX_0 13878 * Bits 31:16 13879 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13880 * address, so for rx frames marked for rx --> tx forwarding, the 13881 * host can determine from the HW peer ID provided as meta-data with 13882 * the rx frame which peer the frame is supposed to be forwarded to. 13883 * Value: ID used by the MAC HW to identify the peer 13884 * - AST_HASH_VALUE 13885 * Bits 15:0 13886 * Purpose: Indicates AST Hash value is required for the TCL AST index 13887 * override feature. 13888 * - NEXT_HOP 13889 * Bit 16 13890 * Purpose: Bit indicates that a next_hop AST entry is used for WDS 13891 * (Wireless Distribution System). 13892 * - AST_VALID_MASK 13893 * Bits 19:17 13894 * Purpose: Indicate if the AST 1 through AST 3 are valid 13895 * - ONCHIP_AST_VALID_FLAG 13896 * Bit 20 13897 * Purpose: Indicate if the on-chip AST index field (ONCHIP_AST_IDX) 13898 * is valid. 13899 * - AST_INDEX_1 13900 * Bits 15:0 13901 * Purpose: indicate the second AST index for this peer 13902 * - AST_0_FLOW_MASK 13903 * Bits 19:16 13904 * Purpose: identify the which flow the AST 0 entry corresponds to. 13905 * - AST_1_FLOW_MASK 13906 * Bits 23:20 13907 * Purpose: identify the which flow the AST 1 entry corresponds to. 13908 * - AST_2_FLOW_MASK 13909 * Bits 27:24 13910 * Purpose: identify the which flow the AST 2 entry corresponds to. 13911 * - AST_3_FLOW_MASK 13912 * Bits 31:28 13913 * Purpose: identify the which flow the AST 3 entry corresponds to. 13914 * - AST_INDEX_2 13915 * Bits 15:0 13916 * Purpose: indicate the third AST index for this peer 13917 * - TID_VALID_HI_PRI 13918 * Bits 23:16 13919 * Purpose: identify if this peer's TIDs 0-7 support HI priority flow 13920 * - TID_VALID_LOW_PRI 13921 * Bits 31:24 13922 * Purpose: identify if this peer's TIDs 0-7 support Low priority flow 13923 * - AST_INDEX_3 13924 * Bits 15:0 13925 * Purpose: indicate the fourth AST index for this peer 13926 * - ONCHIP_AST_IDX / RESERVED 13927 * Bits 31:16 13928 * Purpose: This field is valid only when split AST feature is enabled. 13929 * The ONCHIP_AST_VALID_FLAG identifies whether this field is valid. 13930 * If valid, identifies the HW peer ID corresponding to the peer MAC 13931 * address, this ast_idx is used for LMAC modules for RXPCU. 13932 * Value: ID used by the LMAC HW to identify the peer 13933 */ 13934 #define HTT_RX_PEER_MAP_V2_VDEV_ID_M 0xff00 13935 #define HTT_RX_PEER_MAP_V2_VDEV_ID_S 8 13936 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_M 0xffff0000 13937 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_S 16 13938 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M 0xffffffff 13939 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S 0 13940 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M 0xffff 13941 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S 0 13942 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_M 0xffff0000 13943 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_S 16 13944 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M 0x0000ffff 13945 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S 0 13946 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_M 0x00010000 13947 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_S 16 13948 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M 0x000e0000 13949 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S 17 13950 13951 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M 0x00100000 13952 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S 20 13953 13954 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_M 0xffff 13955 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_S 0 13956 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M 0x000f0000 13957 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S 16 13958 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M 0x00f00000 13959 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S 20 13960 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M 0x0f000000 13961 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S 24 13962 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M 0xf0000000 13963 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S 28 13964 13965 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_M 0xffff 13966 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_S 0 13967 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M 0x00ff0000 13968 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S 16 13969 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M 0xff000000 13970 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S 24 13971 13972 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_M 0xffff 13973 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_S 0 13974 13975 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M 0xffff0000 13976 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S 16 13977 13978 #define HTT_RX_PEER_MAP_V2_VDEV_ID_SET(word, value) \ 13979 do { \ 13980 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_VDEV_ID, value); \ 13981 (word) |= (value) << HTT_RX_PEER_MAP_V2_VDEV_ID_S; \ 13982 } while (0) 13983 #define HTT_RX_PEER_MAP_V2_VDEV_ID_GET(word) \ 13984 (((word) & HTT_RX_PEER_MAP_V2_VDEV_ID_M) >> HTT_RX_PEER_MAP_V2_VDEV_ID_S) 13985 13986 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET(word, value) \ 13987 do { \ 13988 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_SW_PEER_ID, value); \ 13989 (word) |= (value) << HTT_RX_PEER_MAP_V2_SW_PEER_ID_S; \ 13990 } while (0) 13991 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET(word) \ 13992 (((word) & HTT_RX_PEER_MAP_V2_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_SW_PEER_ID_S) 13993 13994 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_SET(word, value) \ 13995 do { \ 13996 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_HW_PEER_ID, value); \ 13997 (word) |= (value) << HTT_RX_PEER_MAP_V2_HW_PEER_ID_S; \ 13998 } while (0) 13999 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_GET(word) \ 14000 (((word) & HTT_RX_PEER_MAP_V2_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_HW_PEER_ID_S) 14001 14002 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_SET(word, value) \ 14003 do { \ 14004 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_HASH_VALUE, value); \ 14005 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S; \ 14006 } while (0) 14007 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_GET(word) \ 14008 (((word) & HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S) 14009 14010 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_SET(word, value) \ 14011 do { \ 14012 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M, value); \ 14013 (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S; \ 14014 } while (0) 14015 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_GET(word) \ 14016 (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S) 14017 14018 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_SET(word, value) \ 14019 do { \ 14020 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_NEXT_HOP, value); \ 14021 (word) |= (value) << HTT_RX_PEER_MAP_V2_NEXT_HOP_S; \ 14022 } while (0) 14023 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_GET(word) \ 14024 (((word) & HTT_RX_PEER_MAP_V2_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V2_NEXT_HOP_S) 14025 14026 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_SET(word, value) \ 14027 do { \ 14028 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_VALID_MASK, value); \ 14029 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S; \ 14030 } while (0) 14031 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_GET(word) \ 14032 (((word) & HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S) 14033 14034 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_SET(word, value) \ 14035 do { \ 14036 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M, value); \ 14037 (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S; \ 14038 } while (0) 14039 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_MASK_GET(word) \ 14040 (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S) 14041 14042 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_SET(word, value) \ 14043 do { \ 14044 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_1, value); \ 14045 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_1_S; \ 14046 } while (0) 14047 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_GET(word) \ 14048 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_1_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_1_S) 14049 14050 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_SET(word, value) \ 14051 do { \ 14052 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK, value); \ 14053 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S; \ 14054 } while (0) 14055 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_GET(word) \ 14056 (((word) & HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S) 14057 14058 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_SET(word, value) \ 14059 do { \ 14060 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK, value); \ 14061 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S; \ 14062 } while (0) 14063 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_GET(word) \ 14064 (((word) & HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S) 14065 14066 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_SET(word, value) \ 14067 do { \ 14068 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK, value); \ 14069 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S; \ 14070 } while (0) 14071 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_GET(word) \ 14072 (((word) & HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S) 14073 14074 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_SET(word, value) \ 14075 do { \ 14076 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK, value); \ 14077 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S; \ 14078 } while (0) 14079 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_GET(word) \ 14080 (((word) & HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S) 14081 14082 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_SET(word, value) \ 14083 do { \ 14084 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_2, value); \ 14085 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_2_S; \ 14086 } while (0) 14087 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_GET(word) \ 14088 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_2_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_2_S) 14089 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_SET(word, value) \ 14090 do { \ 14091 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI, value); \ 14092 (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S; \ 14093 } while (0) 14094 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_GET(word) \ 14095 (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S) 14096 14097 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_SET(word, value) \ 14098 do { \ 14099 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI, value); \ 14100 (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S; \ 14101 } while (0) 14102 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_GET(word) \ 14103 (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S) 14104 14105 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_SET(word, value) \ 14106 do { \ 14107 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_3, value); \ 14108 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_3_S; \ 14109 } while (0) 14110 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_GET(word) \ 14111 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_3_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_3_S) 14112 14113 14114 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_OFFSET 4 /* bytes */ 14115 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_OFFSET 8 /* bytes */ 14116 #define HTT_RX_PEER_MAP_V2_AST_HASH_INDEX_OFFSET 12 /* bytes */ 14117 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_OFFSET 12 /* bytes */ 14118 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_OFFSET 12 /* bytes */ 14119 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_OFFSET 16 /* bytes */ 14120 #define HTT_RX_PEER_MAP_V2_AST_X_FLOW_MASK_OFFSET 16 /* bytes */ 14121 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_OFFSET 20 /* bytes */ 14122 #define HTT_RX_PEER_MAP_V2_TID_VALID_LO_PRI_OFFSET 20 /* bytes */ 14123 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_OFFSET 20 /* bytes */ 14124 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_OFFSET 24 /* bytes */ 14125 14126 #define HTT_RX_PEER_MAP_V2_BYTES 32 14127 14128 /** 14129 * @brief target -> host rx peer map V3 message definition 14130 * 14131 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V3 14132 * 14133 * @details 14134 * The following diagram shows the format of the rx peer map v3 message sent 14135 * from the target to the host. 14136 * Format inherits HTT_T2H_MSG_TYPE_PEER_MAP_V2 published above 14137 * This layout assumes the target operates as little-endian. 14138 * 14139 * |31 24|23 20|19|18|17|16|15 8|7 0| 14140 * |-----------------+--------+--+--+--+--+-----------------+-----------------| 14141 * | SW peer ID | VDEV ID | msg type | 14142 * |-----------------+--------------------+-----------------+-----------------| 14143 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 14144 * |-----------------+--------------------+-----------------+-----------------| 14145 * | Multicast SW peer ID | MAC addr 5 | MAC addr 4 | 14146 * |-----------------+--------+-----------+-----------------+-----------------| 14147 * | HTT_MSDU_IDX_ |RESERVED| CACHE_ | | 14148 * | VALID_MASK |(4bits) | SET_NUM | HW peer ID / AST index | 14149 * | (8bits) | | (4bits) | | 14150 * |-----------------+--------+--+--+--+--------------------------------------| 14151 * | RESERVED |E |O | | | 14152 * | (13bits) |A |A |NH| on-Chip PMAC_RXPCU AST index | 14153 * | |V |V | | | 14154 * |-----------------+--------------------+-----------------------------------| 14155 * | HTT_MSDU_IDX_ | RESERVED | | 14156 * | VALID_MASK_EXT | (8bits) | EXT AST index | 14157 * | (8bits) | | | 14158 * |-----------------+--------------------+-----------------------------------| 14159 * | Reserved_2 | 14160 * |--------------------------------------------------------------------------| 14161 * | Reserved_3 | 14162 * |--------------------------------------------------------------------------| 14163 * 14164 * Where: 14165 * EAV = EXT_AST_VALID flag, for "EXT AST index" 14166 * OAV = ONCHIP_AST_VALID flag, for "on-Chip PMAC_RXPCU AST index" 14167 * NH = Next Hop 14168 * The following field definitions describe the format of the rx peer map v3 14169 * messages sent from the target to the host. 14170 * - MSG_TYPE 14171 * Bits 7:0 14172 * Purpose: identifies this as a peer map v3 message 14173 * Value: 0x2b (HTT_T2H_MSG_TYPE_PEER_MAP_V3) 14174 * - VDEV_ID 14175 * Bits 15:8 14176 * Purpose: Indicates which virtual device the peer is associated with. 14177 * - SW_PEER_ID 14178 * Bits 31:16 14179 * Purpose: The peer ID (index) that WAL has allocated for this peer. 14180 * - MAC_ADDR_L32 14181 * Bits 31:0 14182 * Purpose: Identifies which peer node the peer ID is for. 14183 * Value: lower 4 bytes of peer node's MAC address 14184 * - MAC_ADDR_U16 14185 * Bits 15:0 14186 * Purpose: Identifies which peer node the peer ID is for. 14187 * Value: upper 2 bytes of peer node's MAC address 14188 * - MULTICAST_SW_PEER_ID 14189 * Bits 31:16 14190 * Purpose: The multicast peer ID (index) 14191 * Value: set to HTT_INVALID_PEER if not valid 14192 * - HW_PEER_ID / AST_INDEX 14193 * Bits 15:0 14194 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 14195 * address, so for rx frames marked for rx --> tx forwarding, the 14196 * host can determine from the HW peer ID provided as meta-data with 14197 * the rx frame which peer the frame is supposed to be forwarded to. 14198 * - CACHE_SET_NUM 14199 * Bits 19:16 14200 * Purpose: Cache Set Number for AST_INDEX 14201 * Cache set number that should be used to cache the index based 14202 * search results, for address and flow search. 14203 * This value should be equal to LSB 4 bits of the hash value 14204 * of match data, in case of search index points to an entry which 14205 * may be used in content based search also. The value can be 14206 * anything when the entry pointed by search index will not be 14207 * used for content based search. 14208 * - HTT_MSDU_IDX_VALID_MASK 14209 * Bits 31:24 14210 * Purpose: Shows MSDU indexes valid mask for AST_INDEX 14211 * - ONCHIP_AST_IDX / RESERVED 14212 * Bits 15:0 14213 * Purpose: This field is valid only when split AST feature is enabled. 14214 * The ONCHIP_AST_VALID flag identifies whether this field is valid. 14215 * If valid, identifies the HW peer ID corresponding to the peer MAC 14216 * address, this ast_idx is used for LMAC modules for RXPCU. 14217 * - NEXT_HOP 14218 * Bits 16 14219 * Purpose: Flag indicates next_hop AST entry used for WDS 14220 * (Wireless Distribution System). 14221 * - ONCHIP_AST_VALID 14222 * Bits 17 14223 * Purpose: Flag indicates valid data behind of the ONCHIP_AST_IDX field 14224 * - EXT_AST_VALID 14225 * Bits 18 14226 * Purpose: Flag indicates valid data behind of the EXT_AST_INDEX field 14227 * - EXT_AST_INDEX 14228 * Bits 15:0 14229 * Purpose: This field describes Extended AST index 14230 * Valid if EXT_AST_VALID flag set 14231 * - HTT_MSDU_IDX_VALID_MASK_EXT 14232 * Bits 31:24 14233 * Purpose: Shows MSDU indexes valid mask for EXT_AST_INDEX 14234 */ 14235 /* dword 0 */ 14236 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_M 0xffff0000 14237 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_S 16 14238 #define HTT_RX_PEER_MAP_V3_VDEV_ID_M 0x0000ff00 14239 #define HTT_RX_PEER_MAP_V3_VDEV_ID_S 8 14240 /* dword 1 */ 14241 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_M 0xffffffff 14242 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_S 0 14243 /* dword 2 */ 14244 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_M 0x0000ffff 14245 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_S 0 14246 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M 0xffff0000 14247 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S 16 14248 /* dword 3 */ 14249 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M 0xff000000 14250 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S 24 14251 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M 0x000f0000 14252 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S 16 14253 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_M 0x0000ffff 14254 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_S 0 14255 /* dword 4 */ 14256 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M 0x00040000 14257 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S 18 14258 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M 0x00020000 14259 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S 17 14260 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_M 0x00010000 14261 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_S 16 14262 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M 0x0000ffff 14263 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S 0 14264 /* dword 5 */ 14265 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M 0xff000000 14266 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S 24 14267 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M 0x0000ffff 14268 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S 0 14269 14270 #define HTT_RX_PEER_MAP_V3_VDEV_ID_SET(word, value) \ 14271 do { \ 14272 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_VDEV_ID, value); \ 14273 (word) |= (value) << HTT_RX_PEER_MAP_V3_VDEV_ID_S; \ 14274 } while (0) 14275 #define HTT_RX_PEER_MAP_V3_VDEV_ID_GET(word) \ 14276 (((word) & HTT_RX_PEER_MAP_V3_VDEV_ID_M) >> HTT_RX_PEER_MAP_V3_VDEV_ID_S) 14277 14278 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_SET(word, value) \ 14279 do { \ 14280 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_SW_PEER_ID, value); \ 14281 (word) |= (value) << HTT_RX_PEER_MAP_V3_SW_PEER_ID_S; \ 14282 } while (0) 14283 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_GET(word) \ 14284 (((word) & HTT_RX_PEER_MAP_V3_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_SW_PEER_ID_S) 14285 14286 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_SET(word, value) \ 14287 do { \ 14288 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID, value); \ 14289 (word) |= (value) << HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S; \ 14290 } while (0) 14291 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_GET(word) \ 14292 (((word) & HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S) 14293 14294 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_SET(word, value) \ 14295 do { \ 14296 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_HW_PEER_ID, value); \ 14297 (word) |= (value) << HTT_RX_PEER_MAP_V3_HW_PEER_ID_S; \ 14298 } while (0) 14299 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_GET(word) \ 14300 (((word) & HTT_RX_PEER_MAP_V3_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_HW_PEER_ID_S) 14301 14302 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_SET(word, value) \ 14303 do { \ 14304 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_CACHE_SET_NUM, value); \ 14305 (word) |= (value) << HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S; \ 14306 } while (0) 14307 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_GET(word) \ 14308 (((word) & HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M) >> HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S) 14309 14310 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_SET(word, value) \ 14311 do { \ 14312 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST, value); \ 14313 (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S; \ 14314 } while (0) 14315 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_GET(word) \ 14316 (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S) 14317 14318 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_SET(word, value) \ 14319 do { \ 14320 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX, value); \ 14321 (word) |= (value) << HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S; \ 14322 } while (0) 14323 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_GET(word) \ 14324 (((word) & HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S) 14325 14326 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_SET(word, value) \ 14327 do { \ 14328 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_NEXT_HOP, value); \ 14329 (word) |= (value) << HTT_RX_PEER_MAP_V3_NEXT_HOP_S; \ 14330 } while (0) 14331 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_GET(word) \ 14332 (((word) & HTT_RX_PEER_MAP_V3_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V3_NEXT_HOP_S) 14333 14334 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_SET(word, value) \ 14335 do { \ 14336 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG, value); \ 14337 (word) |= (value) << HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S; \ 14338 } while (0) 14339 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_GET(word) \ 14340 (((word) & HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S) 14341 14342 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_SET(word, value) \ 14343 do { \ 14344 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG, value); \ 14345 (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S; \ 14346 } while (0) 14347 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_GET(word) \ 14348 (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S) 14349 14350 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_SET(word, value) \ 14351 do { \ 14352 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_IDX, value); \ 14353 (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S; \ 14354 } while (0) 14355 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_GET(word) \ 14356 (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S) 14357 14358 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_SET(word, value) \ 14359 do { \ 14360 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST, value); \ 14361 (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S; \ 14362 } while (0) 14363 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_GET(word) \ 14364 (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S) 14365 14366 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_OFFSET 4 /* bytes */ 14367 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_OFFSET 8 /* bytes */ 14368 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_OFFSET 12 /* bytes */ 14369 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_OFFSET 12 /* bytes */ 14370 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_OFFSET 12 /* bytes */ 14371 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_OFFSET 16 /* bytes */ 14372 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_OFFSET 16 /* bytes */ 14373 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_OFFSET 16 /* bytes */ 14374 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_OFFSET 16 /* bytes */ 14375 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_OFFSET 20 /* bytes */ 14376 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_OFFSET 20 /* bytes */ 14377 14378 #define HTT_RX_PEER_MAP_V3_BYTES 32 14379 14380 /** 14381 * @brief target -> host rx peer unmap V2 message definition 14382 * 14383 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 14384 * 14385 * The following diagram shows the format of the rx peer unmap message sent 14386 * from the target to the host. 14387 * 14388 * |31 24|23 16|15 8|7 0| 14389 * |-----------------------------------------------------------------------| 14390 * | SW peer ID | VDEV ID | msg type | 14391 * |-----------------------------------------------------------------------| 14392 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 14393 * |-----------------------------------------------------------------------| 14394 * | Reserved_17_31 | Next Hop | MAC addr 5 | MAC addr 4 | 14395 * |-----------------------------------------------------------------------| 14396 * | Peer Delete Duration | 14397 * |-----------------------------------------------------------------------| 14398 * | Reserved_0 | WDS Free Count | 14399 * |-----------------------------------------------------------------------| 14400 * | Reserved_1 | 14401 * |-----------------------------------------------------------------------| 14402 * | Reserved_2 | 14403 * |-----------------------------------------------------------------------| 14404 * 14405 * 14406 * The following field definitions describe the format of the rx peer unmap 14407 * messages sent from the target to the host. 14408 * - MSG_TYPE 14409 * Bits 7:0 14410 * Purpose: identifies this as an rx peer unmap v2 message 14411 * Value: peer unmap v2 -> 0x1f (HTT_T2H_MSG_TYPE_PEER_UNMAP_V2) 14412 * - VDEV_ID 14413 * Bits 15:8 14414 * Purpose: Indicates which virtual device the peer is associated 14415 * with. 14416 * Value: vdev ID (used in the host to look up the vdev object) 14417 * - SW_PEER_ID 14418 * Bits 31:16 14419 * Purpose: The peer ID (index) that WAL is freeing 14420 * Value: (rx) peer ID 14421 * - MAC_ADDR_L32 14422 * Bits 31:0 14423 * Purpose: Identifies which peer node the peer ID is for. 14424 * Value: lower 4 bytes of peer node's MAC address 14425 * - MAC_ADDR_U16 14426 * Bits 15:0 14427 * Purpose: Identifies which peer node the peer ID is for. 14428 * Value: upper 2 bytes of peer node's MAC address 14429 * - NEXT_HOP 14430 * Bits 16 14431 * Purpose: Bit indicates next_hop AST entry used for WDS 14432 * (Wireless Distribution System). 14433 * - PEER_DELETE_DURATION 14434 * Bits 31:0 14435 * Purpose: Time taken to delete peer, in msec, 14436 * Used for monitoring / debugging PEER delete response delay 14437 * - PEER_WDS_FREE_COUNT 14438 * Bits 15:0 14439 * Purpose: Count of WDS entries deleted associated to peer deleted 14440 */ 14441 14442 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_M HTT_RX_PEER_MAP_V2_VDEV_ID_M 14443 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_S HTT_RX_PEER_MAP_V2_VDEV_ID_S 14444 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_M HTT_RX_PEER_MAP_V2_SW_PEER_ID_M 14445 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_S HTT_RX_PEER_MAP_V2_SW_PEER_ID_S 14446 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_M HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M 14447 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_S HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S 14448 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_M HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M 14449 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_S HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S 14450 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_M HTT_RX_PEER_MAP_V2_NEXT_HOP_M 14451 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_S HTT_RX_PEER_MAP_V2_NEXT_HOP_S 14452 14453 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M 0xffffffff 14454 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S 0 14455 14456 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M 0x0000ffff 14457 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S 0 14458 14459 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_SET HTT_RX_PEER_MAP_V2_VDEV_ID_SET 14460 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_GET HTT_RX_PEER_MAP_V2_VDEV_ID_GET 14461 14462 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_SET HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET 14463 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_GET HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET 14464 14465 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_SET HTT_RX_PEER_MAP_V2_NEXT_HOP_SET 14466 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_GET HTT_RX_PEER_MAP_V2_NEXT_HOP_GET 14467 14468 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_SET(word, value) \ 14469 do { \ 14470 HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION, value); \ 14471 (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S; \ 14472 } while (0) 14473 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_GET(word) \ 14474 (((word) & HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M) >> HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S) 14475 14476 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_SET(word, value) \ 14477 do { \ 14478 HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT, value); \ 14479 (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S; \ 14480 } while (0) 14481 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_GET(word) \ 14482 (((word) & HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M) >> HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S) 14483 14484 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_OFFSET 4 /* bytes */ 14485 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_OFFSET 8 /* bytes */ 14486 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_OFFSET 12 /* bytes */ 14487 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_OFFSET 16 /* bytes */ 14488 14489 #define HTT_RX_PEER_UNMAP_V2_BYTES 28 14490 14491 /** 14492 * @brief target -> host rx peer mlo map message definition 14493 * 14494 * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP 14495 * 14496 * @details 14497 * The following diagram shows the format of the rx mlo peer map message sent 14498 * from the target to the host. This layout assumes the target operates 14499 * as little-endian. 14500 * 14501 * MCC: 14502 * One HTT_MLO_PEER_MAP is sent after PEER_ASSOC received on first LINK for both STA and SAP. 14503 * 14504 * WIN: 14505 * One HTT_MLO_PEER_MAP is sent after peers are created on all the links for both AP and STA. 14506 * It will be sent on the Assoc Link. 14507 * 14508 * This message always contains a MLO peer ID. The main purpose of the 14509 * MLO peer ID is to tell the host what peer ID rx packets will be tagged 14510 * with, so that the host can use that MLO peer ID to determine which peer 14511 * transmitted the rx frame. 14512 * 14513 * |31 |29 27|26 24|23 20|19 17|16|15 8|7 0| 14514 * |-------------------------------------------------------------------------| 14515 * |RSVD | PRC |NUMLINK| MLO peer ID | msg type | 14516 * |-------------------------------------------------------------------------| 14517 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 14518 * |-------------------------------------------------------------------------| 14519 * | RSVD_16_31 | MAC addr 5 | MAC addr 4 | 14520 * |-------------------------------------------------------------------------| 14521 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 | 14522 * |-------------------------------------------------------------------------| 14523 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 | 14524 * |-------------------------------------------------------------------------| 14525 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 | 14526 * |-------------------------------------------------------------------------| 14527 * |RSVD | 14528 * |-------------------------------------------------------------------------| 14529 * |RSVD | 14530 * |-------------------------------------------------------------------------| 14531 * | htt_tlv_hdr_t | 14532 * |-------------------------------------------------------------------------| 14533 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 14534 * |-------------------------------------------------------------------------| 14535 * | htt_tlv_hdr_t | 14536 * |-------------------------------------------------------------------------| 14537 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 14538 * |-------------------------------------------------------------------------| 14539 * | htt_tlv_hdr_t | 14540 * |-------------------------------------------------------------------------| 14541 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 14542 * |-------------------------------------------------------------------------| 14543 * 14544 * Where: 14545 * PRC - Primary REO CHIPID - 3 Bits Bit24,25,26 14546 * NUMLINK - NUM_LOGICAL_LINKS - 3 Bits Bit27,28,29 14547 * V (valid) - 1 Bit Bit17 14548 * CHIPID - 3 Bits 14549 * TIDMASK - 8 Bits 14550 * CACHE_SET_NUM - 8 Bits 14551 * 14552 * The following field definitions describe the format of the rx MLO peer map 14553 * messages sent from the target to the host. 14554 * - MSG_TYPE 14555 * Bits 7:0 14556 * Purpose: identifies this as an rx mlo peer map message 14557 * Value: 0x29 (HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP) 14558 * 14559 * - MLO_PEER_ID 14560 * Bits 23:8 14561 * Purpose: The MLO peer ID (index). 14562 * For MCC, FW will allocate it. For WIN, Host will allocate it. 14563 * Value: MLO peer ID 14564 * 14565 * - NUMLINK 14566 * Bits: 26:24 (3Bits) 14567 * Purpose: Indicate the max number of logical links supported per client. 14568 * Value: number of logical links 14569 * 14570 * - PRC 14571 * Bits: 29:27 (3Bits) 14572 * Purpose: Indicate the Primary REO CHIPID. The ID can be used to indicate 14573 * if there is migration of the primary chip. 14574 * Value: Primary REO CHIPID 14575 * 14576 * - MAC_ADDR_L32 14577 * Bits 31:0 14578 * Purpose: Identifies which mlo peer node the mlo peer ID is for. 14579 * Value: lower 4 bytes of peer node's MAC address 14580 * 14581 * - MAC_ADDR_U16 14582 * Bits 15:0 14583 * Purpose: Identifies which peer node the peer ID is for. 14584 * Value: upper 2 bytes of peer node's MAC address 14585 * 14586 * - PRIMARY_TCL_AST_IDX 14587 * Bits 15:0 14588 * Purpose: Primary TCL AST index for this peer. 14589 * 14590 * - V 14591 * 1 Bit Position 16 14592 * Purpose: If the ast idx is valid. 14593 * 14594 * - CHIPID 14595 * Bits 19:17 14596 * Purpose: Identifies which chip id of PRIMARY_TCL_AST_IDX 14597 * 14598 * - TIDMASK 14599 * Bits 27:20 14600 * Purpose: LINK to TID mapping for PRIMARY_TCL_AST_IDX 14601 * 14602 * - CACHE_SET_NUM 14603 * Bits 31:28 14604 * Purpose: Cache Set Number for PRIMARY_TCL_AST_IDX 14605 * Cache set number that should be used to cache the index based 14606 * search results, for address and flow search. 14607 * This value should be equal to LSB four bits of the hash value 14608 * of match data, in case of search index points to an entry which 14609 * may be used in content based search also. The value can be 14610 * anything when the entry pointed by search index will not be 14611 * used for content based search. 14612 * 14613 * - htt_tlv_hdr_t 14614 * Purpose: Provide link specific chip,vdev and sw_peer IDs 14615 * 14616 * Bits 11:0 14617 * Purpose: tag equal to MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS. 14618 * 14619 * Bits 23:12 14620 * Purpose: Length, Length of the value that follows the header 14621 * 14622 * Bits 31:28 14623 * Purpose: Reserved. 14624 * 14625 * 14626 * - SW_PEER_ID 14627 * Bits 15:0 14628 * Purpose: The peer ID (index) that WAL is allocating 14629 * Value: (rx) peer ID 14630 * 14631 * - VDEV_ID 14632 * Bits 23:16 14633 * Purpose: Indicates which virtual device the peer is associated with. 14634 * Value: vdev ID (used in the host to look up the vdev object) 14635 * 14636 * - CHIPID 14637 * Bits 26:24 14638 * Purpose: Indicates which Chip id the peer is associated with. 14639 * Value: chip ID (Provided by Host as part of QMI exchange) 14640 */ 14641 typedef enum { 14642 MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS, 14643 } MLO_PEER_MAP_TLV_TAG_ID; 14644 14645 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M 0x00ffff00 14646 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S 8 14647 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M 0x07000000 14648 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S 24 14649 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M 0x38000000 14650 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S 27 14651 14652 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_M 0xffffffff 14653 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_S 0 14654 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_M 0x0000ffff 14655 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_S 0 14656 14657 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M 0x0000ffff 14658 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S 0 14659 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M 0x00010000 14660 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S 16 14661 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M 0x000E0000 14662 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S 17 14663 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M 0x00F00000 14664 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S 20 14665 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M 0xF0000000 14666 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S 28 14667 14668 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_M 0x00000fff 14669 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_S 0 14670 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M 0x00fff000 14671 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S 12 14672 14673 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M 0x0000ffff 14674 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S 0 14675 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_M 0x00ff0000 14676 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_S 16 14677 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_M 0x07000000 14678 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_S 24 14679 14680 14681 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET(word, value) \ 14682 do { \ 14683 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_MLO_PEER_ID, value); \ 14684 (word) |= (value) << HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S; \ 14685 } while (0) 14686 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET(word) \ 14687 (((word) & HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S) 14688 14689 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_SET(word, value) \ 14690 do { \ 14691 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS, value); \ 14692 (word) |= (value) << HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S; \ 14693 } while (0) 14694 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_GET(word) \ 14695 (((word) & HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M) >> HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S) 14696 14697 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_SET(word, value) \ 14698 do { \ 14699 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID, value); \ 14700 (word) |= (value) << HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S; \ 14701 } while (0) 14702 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \ 14703 (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S) 14704 14705 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_SET(word, value) \ 14706 do { \ 14707 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX, value); \ 14708 (word) |= (value) << HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S; \ 14709 } while (0) 14710 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_GET(word) \ 14711 (((word) & HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S) 14712 14713 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_SET(word, value) \ 14714 do { \ 14715 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG, value); \ 14716 (word) |= (value) << HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S; \ 14717 } while (0) 14718 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_GET(word) \ 14719 (((word) & HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M) >> HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S) 14720 14721 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_SET(word, value) \ 14722 do { \ 14723 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX, value); \ 14724 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S; \ 14725 } while (0) 14726 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_GET(word) \ 14727 (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S) 14728 14729 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_SET(word, value) \ 14730 do { \ 14731 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX, value); \ 14732 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S; \ 14733 } while (0) 14734 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_GET(word) \ 14735 (((word) & HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S) 14736 14737 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_SET(word, value) \ 14738 do { \ 14739 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX, value); \ 14740 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S; \ 14741 } while (0) 14742 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_GET(word) \ 14743 (((word) & HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S) 14744 14745 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_SET(word, value) \ 14746 do { \ 14747 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_TAG, value); \ 14748 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_TAG_S; \ 14749 } while (0) 14750 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_GET(word) \ 14751 (((word) & HTT_RX_MLO_PEER_MAP_TLV_TAG_M) >> HTT_RX_MLO_PEER_MAP_TLV_TAG_S) 14752 14753 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_SET(word, value) \ 14754 do { \ 14755 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_LENGTH, value); \ 14756 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S; \ 14757 } while (0) 14758 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_GET(word) \ 14759 (((word) & HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M) >> HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S) 14760 14761 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_SET(word, value) \ 14762 do { \ 14763 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_SW_PEER_ID, value); \ 14764 (word) |= (value) << HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S; \ 14765 } while (0) 14766 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_GET(word) \ 14767 (((word) & HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S) 14768 14769 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_SET(word, value) \ 14770 do { \ 14771 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_VDEV_ID, value); \ 14772 (word) |= (value) << HTT_RX_MLO_PEER_MAP_VDEV_ID_S; \ 14773 } while (0) 14774 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_GET(word) \ 14775 (((word) & HTT_RX_MLO_PEER_MAP_VDEV_ID_M) >> HTT_RX_MLO_PEER_MAP_VDEV_ID_S) 14776 14777 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_SET(word, value) \ 14778 do { \ 14779 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID, value); \ 14780 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_S; \ 14781 } while (0) 14782 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_GET(word) \ 14783 (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_S) 14784 14785 14786 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ 14787 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_0_OFFSET 12 /* bytes */ 14788 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_1_OFFSET 16 /* bytes */ 14789 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_2_OFFSET 20 /* bytes */ 14790 #define HTT_RX_MLO_PEER_MAP_TLV_OFFSET 32 /* bytes */ 14791 14792 #define HTT_RX_MLO_PEER_MAP_FIXED_BYTES 8*4 /* 8 Dwords. Does not include the TLV header and the TLV */ 14793 14794 14795 /* MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP 14796 * 14797 * The following diagram shows the format of the rx mlo peer unmap message sent 14798 * from the target to the host. 14799 * 14800 * |31 24|23 16|15 8|7 0| 14801 * |-----------------------------------------------------------------------| 14802 * | RSVD_24_31 | MLO peer ID | msg type | 14803 * |-----------------------------------------------------------------------| 14804 */ 14805 14806 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_M HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M 14807 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_S HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S 14808 14809 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_SET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET 14810 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_GET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET 14811 14812 /** 14813 * @brief target -> host peer extended event for additional information 14814 * 14815 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT 14816 * 14817 * @details 14818 * The following diagram shows the format of the peer extended message sent 14819 * from the target to the host. This layout assumes the target operates 14820 * as little-endian. 14821 * 14822 * This message always contains a SW peer ID. The main purpose of the 14823 * SW peer ID is to tell the host what peer ID logical link id will be tagged 14824 * with, so that the host can use that peer ID to determine which link 14825 * transmitted the rx/tx frame. 14826 * 14827 * This message also contains MLO logical link id assigned to peer 14828 * with sw_peer_id if it is valid ML link peer. 14829 * 14830 * 14831 * |31 28|27 24|23 20|19|18 16|15 8|7 0| 14832 * |---------------------------------------------------------------------------| 14833 * | VDEV_ID | SW peer ID | msg type | 14834 * |---------------------------------------------------------------------------| 14835 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 14836 * |---------------------------------------------------------------------------| 14837 * | Reserved |V | LINK ID | MAC addr 5 | MAC addr 4 | 14838 * |---------------------------------------------------------------------------| 14839 * | Reserved | 14840 * |---------------------------------------------------------------------------| 14841 * | Reserved | 14842 * |---------------------------------------------------------------------------| 14843 * 14844 * Where: 14845 * LINK_ID (LOGICAL) - 3 Bits Bit16,17,18 of 3rd byte 14846 * V (valid) - 1 Bit Bit19 of 3rd byte 14847 * 14848 * The following field definitions describe the format of the rx peer extended 14849 * event messages sent from the target to the host. 14850 * MSG_TYPE 14851 * Bits 7:0 14852 * Purpose: identifies this as an rx MLO peer extended information message 14853 * Value: 0x39 (HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT) 14854 * - PEER_ID (a.k.a. SW_PEER_ID) 14855 * Bits 8:23 14856 * Purpose: The peer ID (index) that WAL has allocated 14857 * Value: (rx) peer ID 14858 * - VDEV_ID 14859 * Bits 24:31 14860 * Purpose: Gives the vdev id of peer with peer_id as above. 14861 * Value: VDEV ID of wal_peer 14862 * 14863 * - MAC_ADDR_L32 14864 * Bits 31:0 14865 * Purpose: Identifies which peer node the peer ID is for. 14866 * Value: lower 4 bytes of peer node's MAC address 14867 * 14868 * - MAC_ADDR_U16 14869 * Bits 15:0 14870 * Purpose: Identifies which peer node the peer ID is for. 14871 * Value: upper 2 bytes of peer node's MAC address 14872 * Rest all bits are reserved for future expansion 14873 * - LOGICAL_LINK_ID 14874 * Bits 18:16 14875 * Purpose: Gives the logical link id of peer with peer_id as above. This 14876 * field should be taken alongwith LOGICAL_LINK_ID_VALID 14877 * Value: Logical link id used by wal_peer 14878 * - LOGICAL_LINK_ID_VALID 14879 * Bit 19 14880 * Purpose: Clarifies whether the logical link id of peer with peer_id as 14881 * is valid or not 14882 * Value: 0/1 indicating LOGICAL_LINK_ID is valid or not 14883 */ 14884 #define HTT_RX_PEER_EXTENDED_PEER_ID_M 0x00ffff00 14885 #define HTT_RX_PEER_EXTENDED_PEER_ID_S 8 14886 #define HTT_RX_PEER_EXTENDED_VDEV_ID_M 0xff000000 14887 #define HTT_RX_PEER_EXTENDED_VDEV_ID_S 24 14888 14889 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_M 0xffffffff 14890 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_S 0 14891 14892 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_M 0x0000ffff 14893 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_S 0 14894 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M 0x00070000 14895 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S 16 14896 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M 0x00080000 14897 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S 19 14898 14899 14900 #define HTT_RX_PEER_EXTENDED_PEER_ID_SET(word, value) \ 14901 do { \ 14902 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ 14903 (word) |= (value) << HTT_RX_PEER_EXTENDED_PEER_ID_S; \ 14904 } while (0) 14905 #define HTT_RX_PEER_EXTENDED_PEER_ID_GET(word) \ 14906 (((word) & HTT_RX_PEER_EXTENDED_PEER_ID_M) >> HTT_RX_PEER_EXTENDED_PEER_ID_S) 14907 14908 #define HTT_RX_PEER_EXTENDED_VDEV_ID_SET(word, value) \ 14909 do { \ 14910 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_VDEV_ID, value); \ 14911 (word) |= (value) << HTT_RX_PEER_EXTENDED_VDEV_ID_S; \ 14912 } while (0) 14913 #define HTT_RX_PEER_EXTENDED_VDEV_ID_GET(word) \ 14914 (((word) & HTT_RX_PEER_EXTENDED_VDEV_ID_M) >> HTT_RX_PEER_EXTENDED_VDEV_ID_S) 14915 14916 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_SET(word, value) \ 14917 do { \ 14918 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID, value); \ 14919 (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S; \ 14920 } while (0) 14921 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_GET(word) \ 14922 (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S) 14923 14924 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_SET(word, value) \ 14925 do { \ 14926 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID, value); \ 14927 (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S; \ 14928 } while (0) 14929 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_GET(word) \ 14930 (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S) 14931 14932 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_OFFSET 4 /* bytes */ 14933 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_OFFSET 8 /* bytes */ 14934 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_OFFSET 8 /* bytes */ 14935 14936 #define HTT_RX_PEER_EXTENDED_EVENT_BYTES 20 /* bytes */ 14937 14938 /** 14939 * @brief target -> host message specifying security parameters 14940 * 14941 * MSG_TYPE => HTT_T2H_MSG_TYPE_SEC_IND 14942 * 14943 * @details 14944 * The following diagram shows the format of the security specification 14945 * message sent from the target to the host. 14946 * This security specification message tells the host whether a PN check is 14947 * necessary on rx data frames, and if so, how large the PN counter is. 14948 * This message also tells the host about the security processing to apply 14949 * to defragmented rx frames - specifically, whether a Message Integrity 14950 * Check is required, and the Michael key to use. 14951 * 14952 * |31 24|23 16|15|14 8|7 0| 14953 * |-----------------------------------------------------------------------| 14954 * | peer ID | U| security type | msg type | 14955 * |-----------------------------------------------------------------------| 14956 * | Michael Key K0 | 14957 * |-----------------------------------------------------------------------| 14958 * | Michael Key K1 | 14959 * |-----------------------------------------------------------------------| 14960 * | WAPI RSC Low0 | 14961 * |-----------------------------------------------------------------------| 14962 * | WAPI RSC Low1 | 14963 * |-----------------------------------------------------------------------| 14964 * | WAPI RSC Hi0 | 14965 * |-----------------------------------------------------------------------| 14966 * | WAPI RSC Hi1 | 14967 * |-----------------------------------------------------------------------| 14968 * 14969 * The following field definitions describe the format of the security 14970 * indication message sent from the target to the host. 14971 * - MSG_TYPE 14972 * Bits 7:0 14973 * Purpose: identifies this as a security specification message 14974 * Value: 0xb (HTT_T2H_MSG_TYPE_SEC_IND) 14975 * - SEC_TYPE 14976 * Bits 14:8 14977 * Purpose: specifies which type of security applies to the peer 14978 * Value: htt_sec_type enum value 14979 * - UNICAST 14980 * Bit 15 14981 * Purpose: whether this security is applied to unicast or multicast data 14982 * Value: 1 -> unicast, 0 -> multicast 14983 * - PEER_ID 14984 * Bits 31:16 14985 * Purpose: The ID number for the peer the security specification is for 14986 * Value: peer ID 14987 * - MICHAEL_KEY_K0 14988 * Bits 31:0 14989 * Purpose: 4-byte word that forms the 1st half of the TKIP Michael key 14990 * Value: Michael Key K0 (if security type is TKIP) 14991 * - MICHAEL_KEY_K1 14992 * Bits 31:0 14993 * Purpose: 4-byte word that forms the 2nd half of the TKIP Michael key 14994 * Value: Michael Key K1 (if security type is TKIP) 14995 * - WAPI_RSC_LOW0 14996 * Bits 31:0 14997 * Purpose: 4-byte word that forms the 1st quarter of the 16 byte WAPI RSC 14998 * Value: WAPI RSC Low0 (if security type is WAPI) 14999 * - WAPI_RSC_LOW1 15000 * Bits 31:0 15001 * Purpose: 4-byte word that forms the 2nd quarter of the 16 byte WAPI RSC 15002 * Value: WAPI RSC Low1 (if security type is WAPI) 15003 * - WAPI_RSC_HI0 15004 * Bits 31:0 15005 * Purpose: 4-byte word that forms the 3rd quarter of the 16 byte WAPI RSC 15006 * Value: WAPI RSC Hi0 (if security type is WAPI) 15007 * - WAPI_RSC_HI1 15008 * Bits 31:0 15009 * Purpose: 4-byte word that forms the 4th quarter of the 16 byte WAPI RSC 15010 * Value: WAPI RSC Hi1 (if security type is WAPI) 15011 */ 15012 15013 #define HTT_SEC_IND_SEC_TYPE_M 0x00007f00 15014 #define HTT_SEC_IND_SEC_TYPE_S 8 15015 #define HTT_SEC_IND_UNICAST_M 0x00008000 15016 #define HTT_SEC_IND_UNICAST_S 15 15017 #define HTT_SEC_IND_PEER_ID_M 0xffff0000 15018 #define HTT_SEC_IND_PEER_ID_S 16 15019 15020 #define HTT_SEC_IND_SEC_TYPE_SET(word, value) \ 15021 do { \ 15022 HTT_CHECK_SET_VAL(HTT_SEC_IND_SEC_TYPE, value); \ 15023 (word) |= (value) << HTT_SEC_IND_SEC_TYPE_S; \ 15024 } while (0) 15025 #define HTT_SEC_IND_SEC_TYPE_GET(word) \ 15026 (((word) & HTT_SEC_IND_SEC_TYPE_M) >> HTT_SEC_IND_SEC_TYPE_S) 15027 15028 #define HTT_SEC_IND_UNICAST_SET(word, value) \ 15029 do { \ 15030 HTT_CHECK_SET_VAL(HTT_SEC_IND_UNICAST, value); \ 15031 (word) |= (value) << HTT_SEC_IND_UNICAST_S; \ 15032 } while (0) 15033 #define HTT_SEC_IND_UNICAST_GET(word) \ 15034 (((word) & HTT_SEC_IND_UNICAST_M) >> HTT_SEC_IND_UNICAST_S) 15035 15036 #define HTT_SEC_IND_PEER_ID_SET(word, value) \ 15037 do { \ 15038 HTT_CHECK_SET_VAL(HTT_SEC_IND_PEER_ID, value); \ 15039 (word) |= (value) << HTT_SEC_IND_PEER_ID_S; \ 15040 } while (0) 15041 #define HTT_SEC_IND_PEER_ID_GET(word) \ 15042 (((word) & HTT_SEC_IND_PEER_ID_M) >> HTT_SEC_IND_PEER_ID_S) 15043 15044 15045 #define HTT_SEC_IND_BYTES 28 15046 15047 15048 /** 15049 * @brief target -> host rx ADDBA / DELBA message definitions 15050 * 15051 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA 15052 * 15053 * @details 15054 * The following diagram shows the format of the rx ADDBA message sent 15055 * from the target to the host: 15056 * 15057 * |31 20|19 16|15 8|7 0| 15058 * |---------------------------------------------------------------------| 15059 * | peer ID | TID | window size | msg type | 15060 * |---------------------------------------------------------------------| 15061 * 15062 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA 15063 * 15064 * The following diagram shows the format of the rx DELBA message sent 15065 * from the target to the host: 15066 * 15067 * |31 20|19 16|15 10|9 8|7 0| 15068 * |---------------------------------------------------------------------| 15069 * | peer ID | TID | window size | IR| msg type | 15070 * |---------------------------------------------------------------------| 15071 * 15072 * The following field definitions describe the format of the rx ADDBA 15073 * and DELBA messages sent from the target to the host. 15074 * - MSG_TYPE 15075 * Bits 7:0 15076 * Purpose: identifies this as an rx ADDBA or DELBA message 15077 * Value: ADDBA -> 0x5 (HTT_T2H_MSG_TYPE_RX_ADDBA), 15078 * DELBA -> 0x6 (HTT_T2H_MSG_TYPE_RX_DELBA) 15079 * - IR (initiator / recipient) 15080 * Bits 9:8 (DELBA only) 15081 * Purpose: specify whether the DELBA handshake was initiated by the 15082 * local STA/AP, or by the peer STA/AP 15083 * Value: 15084 * 0 - unspecified 15085 * 1 - initiator (a.k.a. originator) 15086 * 2 - recipient (a.k.a. responder) 15087 * 3 - unused / reserved 15088 * - WIN_SIZE 15089 * Bits 15:8 for ADDBA, bits 15:10 for DELBA 15090 * Purpose: Specifies the length of the block ack window (max = 64). 15091 * Value: 15092 * block ack window length specified by the received ADDBA/DELBA 15093 * management message. 15094 * - TID 15095 * Bits 19:16 15096 * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for. 15097 * Value: 15098 * TID specified by the received ADDBA or DELBA management message. 15099 * - PEER_ID 15100 * Bits 31:20 15101 * Purpose: Identifies which peer sent the ADDBA / DELBA. 15102 * Value: 15103 * ID (hash value) used by the host for fast, direct lookup of 15104 * host SW peer info, including rx reorder states. 15105 */ 15106 #define HTT_RX_ADDBA_WIN_SIZE_M 0xff00 15107 #define HTT_RX_ADDBA_WIN_SIZE_S 8 15108 #define HTT_RX_ADDBA_TID_M 0xf0000 15109 #define HTT_RX_ADDBA_TID_S 16 15110 #define HTT_RX_ADDBA_PEER_ID_M 0xfff00000 15111 #define HTT_RX_ADDBA_PEER_ID_S 20 15112 15113 #define HTT_RX_ADDBA_WIN_SIZE_SET(word, value) \ 15114 do { \ 15115 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_WIN_SIZE, value); \ 15116 (word) |= (value) << HTT_RX_ADDBA_WIN_SIZE_S; \ 15117 } while (0) 15118 #define HTT_RX_ADDBA_WIN_SIZE_GET(word) \ 15119 (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) 15120 15121 #define HTT_RX_ADDBA_TID_SET(word, value) \ 15122 do { \ 15123 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_TID, value); \ 15124 (word) |= (value) << HTT_RX_ADDBA_TID_S; \ 15125 } while (0) 15126 #define HTT_RX_ADDBA_TID_GET(word) \ 15127 (((word) & HTT_RX_ADDBA_TID_M) >> HTT_RX_ADDBA_TID_S) 15128 15129 #define HTT_RX_ADDBA_PEER_ID_SET(word, value) \ 15130 do { \ 15131 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_PEER_ID, value); \ 15132 (word) |= (value) << HTT_RX_ADDBA_PEER_ID_S; \ 15133 } while (0) 15134 #define HTT_RX_ADDBA_PEER_ID_GET(word) \ 15135 (((word) & HTT_RX_ADDBA_PEER_ID_M) >> HTT_RX_ADDBA_PEER_ID_S) 15136 15137 #define HTT_RX_ADDBA_BYTES 4 15138 15139 15140 #define HTT_RX_DELBA_INITIATOR_M 0x00000300 15141 #define HTT_RX_DELBA_INITIATOR_S 8 15142 #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00 15143 #define HTT_RX_DELBA_WIN_SIZE_S 10 15144 #define HTT_RX_DELBA_TID_M HTT_RX_ADDBA_TID_M 15145 #define HTT_RX_DELBA_TID_S HTT_RX_ADDBA_TID_S 15146 #define HTT_RX_DELBA_PEER_ID_M HTT_RX_ADDBA_PEER_ID_M 15147 #define HTT_RX_DELBA_PEER_ID_S HTT_RX_ADDBA_PEER_ID_S 15148 15149 #define HTT_RX_DELBA_TID_SET HTT_RX_ADDBA_TID_SET 15150 #define HTT_RX_DELBA_TID_GET HTT_RX_ADDBA_TID_GET 15151 #define HTT_RX_DELBA_PEER_ID_SET HTT_RX_ADDBA_PEER_ID_SET 15152 #define HTT_RX_DELBA_PEER_ID_GET HTT_RX_ADDBA_PEER_ID_GET 15153 15154 #define HTT_RX_DELBA_INITIATOR_SET(word, value) \ 15155 do { \ 15156 HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \ 15157 (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \ 15158 } while (0) 15159 #define HTT_RX_DELBA_INITIATOR_GET(word) \ 15160 (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S) 15161 15162 #define HTT_RX_DELBA_WIN_SIZE_SET(word, value) \ 15163 do { \ 15164 HTT_CHECK_SET_VAL(HTT_RX_DELBA_WIN_SIZE, value); \ 15165 (word) |= (value) << HTT_RX_DELBA_WIN_SIZE_S; \ 15166 } while (0) 15167 #define HTT_RX_DELBA_WIN_SIZE_GET(word) \ 15168 (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S) 15169 15170 #define HTT_RX_DELBA_BYTES 4 15171 15172 15173 /** 15174 * @brief target -> host rx ADDBA / DELBA message definitions 15175 * 15176 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN 15177 * 15178 * @details 15179 * The following diagram shows the format of the rx ADDBA extn message sent 15180 * from the target to the host: 15181 * 15182 * |31 20|19 16|15 13|12 8|7 0| 15183 * |---------------------------------------------------------------------| 15184 * | peer ID | TID | reserved | msg type | 15185 * |---------------------------------------------------------------------| 15186 * | reserved | window size | 15187 * |---------------------------------------------------------------------| 15188 * 15189 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA_EXTN 15190 * 15191 * The following diagram shows the format of the rx DELBA message sent 15192 * from the target to the host: 15193 * 15194 * |31 20|19 16|15 13|12 10|9 8|7 0| 15195 * |---------------------------------------------------------------------| 15196 * | peer ID | TID | reserved | IR| msg type | 15197 * |---------------------------------------------------------------------| 15198 * | reserved | window size | 15199 * |---------------------------------------------------------------------| 15200 * 15201 * The following field definitions describe the format of the rx ADDBA 15202 * and DELBA messages sent from the target to the host. 15203 * - MSG_TYPE 15204 * Bits 7:0 15205 * Purpose: identifies this as an rx ADDBA or DELBA message 15206 * Value: ADDBA -> 0x31 (HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN), 15207 * DELBA -> 0x32 (HTT_T2H_MSG_TYPE_RX_DELBA_EXTN) 15208 * - IR (initiator / recipient) 15209 * Bits 9:8 (DELBA only) 15210 * Purpose: specify whether the DELBA handshake was initiated by the 15211 * local STA/AP, or by the peer STA/AP 15212 * Value: 15213 * 0 - unspecified 15214 * 1 - initiator (a.k.a. originator) 15215 * 2 - recipient (a.k.a. responder) 15216 * 3 - unused / reserved 15217 * Value: 15218 * block ack window length specified by the received ADDBA/DELBA 15219 * management message. 15220 * - TID 15221 * Bits 19:16 15222 * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for. 15223 * Value: 15224 * TID specified by the received ADDBA or DELBA management message. 15225 * - PEER_ID 15226 * Bits 31:20 15227 * Purpose: Identifies which peer sent the ADDBA / DELBA. 15228 * Value: 15229 * ID (hash value) used by the host for fast, direct lookup of 15230 * host SW peer info, including rx reorder states. 15231 * == DWORD 1 15232 * - WIN_SIZE 15233 * Bits 12:0 for ADDBA, bits 12:0 for DELBA 15234 * Purpose: Specifies the length of the block ack window (max = 8191). 15235 */ 15236 15237 #define HTT_RX_ADDBA_EXTN_TID_M 0xf0000 15238 #define HTT_RX_ADDBA_EXTN_TID_S 16 15239 #define HTT_RX_ADDBA_EXTN_PEER_ID_M 0xfff00000 15240 #define HTT_RX_ADDBA_EXTN_PEER_ID_S 20 15241 15242 /*--- Dword 0 ---*/ 15243 #define HTT_RX_ADDBA_EXTN_TID_SET(word, value) \ 15244 do { \ 15245 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_TID, value); \ 15246 (word) |= (value) << HTT_RX_ADDBA_EXTN_TID_S; \ 15247 } while (0) 15248 #define HTT_RX_ADDBA_EXTN_TID_GET(word) \ 15249 (((word) & HTT_RX_ADDBA_EXTN_TID_M) >> HTT_RX_ADDBA_EXTN_TID_S) 15250 15251 #define HTT_RX_ADDBA_EXTN_PEER_ID_SET(word, value) \ 15252 do { \ 15253 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_PEER_ID, value); \ 15254 (word) |= (value) << HTT_RX_ADDBA_EXTN_PEER_ID_S; \ 15255 } while (0) 15256 #define HTT_RX_ADDBA_EXTN_PEER_ID_GET(word) \ 15257 (((word) & HTT_RX_ADDBA_EXTN_PEER_ID_M) >> HTT_RX_ADDBA_EXTN_PEER_ID_S) 15258 15259 /*--- Dword 1 ---*/ 15260 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_M 0x1fff 15261 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_S 0 15262 15263 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_SET(word, value) \ 15264 do { \ 15265 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_WIN_SIZE, value); \ 15266 (word) |= (value) << HTT_RX_ADDBA_EXTN_WIN_SIZE_S; \ 15267 } while (0) 15268 15269 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_GET(word) \ 15270 (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) 15271 15272 #define HTT_RX_ADDBA_EXTN_BYTES 8 15273 15274 15275 #define HTT_RX_DELBA_EXTN_INITIATOR_M 0x00000300 15276 #define HTT_RX_DELBA_EXTN_INITIATOR_S 8 15277 #define HTT_RX_DELBA_EXTN_TID_M 0xf0000 15278 #define HTT_RX_DELBA_EXTN_TID_S 16 15279 #define HTT_RX_DELBA_EXTN_PEER_ID_M 0xfff00000 15280 #define HTT_RX_DELBA_EXTN_PEER_ID_S 20 15281 15282 /*--- Dword 0 ---*/ 15283 #define HTT_RX_DELBA_INITIATOR_SET(word, value) \ 15284 do { \ 15285 HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \ 15286 (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \ 15287 } while (0) 15288 #define HTT_RX_DELBA_INITIATOR_GET(word) \ 15289 (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S) 15290 15291 #define HTT_RX_DELBA_EXTN_TID_SET(word, value) \ 15292 do { \ 15293 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_TID, value); \ 15294 (word) |= (value) << HTT_RX_DELBA_EXTN_TID_S; \ 15295 } while (0) 15296 #define HTT_RX_DELBA_EXTN_TID_GET(word) \ 15297 (((word) & HTT_RX_DELBA_EXTN_TID_M) >> HTT_RX_DELBA_EXTN_TID_S) 15298 15299 #define HTT_RX_DELBA_EXTN_PEER_ID_SET(word, value) \ 15300 do { \ 15301 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_PEER_ID, value); \ 15302 (word) |= (value) << HTT_RX_DELBA_EXTN_PEER_ID_S; \ 15303 } while (0) 15304 #define HTT_RX_DELBA_EXTN_PEER_ID_GET(word) \ 15305 (((word) & HTT_RX_DELBA_EXTN_PEER_ID_M) >> HTT_RX_DELBA_EXTN_PEER_ID_S) 15306 15307 /*--- Dword 1 ---*/ 15308 #define HTT_RX_DELBA_EXTN_WIN_SIZE_M 0x1fff 15309 #define HTT_RX_DELBA_EXTN_WIN_SIZE_S 0 15310 15311 #define HTT_RX_DELBA_EXTN_WIN_SIZE_SET(word, value) \ 15312 do { \ 15313 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_WIN_SIZE, value); \ 15314 (word) |= (value) << HTT_RX_DELBA_EXTN_WIN_SIZE_S; \ 15315 } while (0) 15316 #define HTT_RX_DELBA_EXTN_WIN_SIZE_GET(word) \ 15317 (((word) & HTT_RX_DELBA_EXTN_WIN_SIZE_M) >> HTT_RX_DELBA_EXTN_WIN_SIZE_S) 15318 15319 #define HTT_RX_DELBA_EXTN_BYTES 8 15320 15321 15322 /** 15323 * @brief tx queue group information element definition 15324 * 15325 * @details 15326 * The following diagram shows the format of the tx queue group 15327 * information element, which can be included in target --> host 15328 * messages to specify the number of tx "credits" (tx descriptors 15329 * for LL, or tx buffers for HL) available to a particular group 15330 * of host-side tx queues, and which host-side tx queues belong to 15331 * the group. 15332 * 15333 * |31|30 24|23 16|15|14|13 0| 15334 * |------------------------------------------------------------------------| 15335 * | X| reserved | tx queue grp ID | A| S| credit count | 15336 * |------------------------------------------------------------------------| 15337 * | vdev ID mask | AC mask | 15338 * |------------------------------------------------------------------------| 15339 * 15340 * The following definitions describe the fields within the tx queue group 15341 * information element: 15342 * - credit_count 15343 * Bits 13:1 15344 * Purpose: specify how many tx credits are available to the tx queue group 15345 * Value: An absolute or relative, positive or negative credit value 15346 * The 'A' bit specifies whether the value is absolute or relative. 15347 * The 'S' bit specifies whether the value is positive or negative. 15348 * A negative value can only be relative, not absolute. 15349 * An absolute value replaces any prior credit value the host has for 15350 * the tx queue group in question. 15351 * A relative value is added to the prior credit value the host has for 15352 * the tx queue group in question. 15353 * - sign 15354 * Bit 14 15355 * Purpose: specify whether the credit count is positive or negative 15356 * Value: 0 -> positive, 1 -> negative 15357 * - absolute 15358 * Bit 15 15359 * Purpose: specify whether the credit count is absolute or relative 15360 * Value: 0 -> relative, 1 -> absolute 15361 * - txq_group_id 15362 * Bits 23:16 15363 * Purpose: indicate which tx queue group's credit and/or membership are 15364 * being specified 15365 * Value: 0 to max_tx_queue_groups-1 15366 * - reserved 15367 * Bits 30:16 15368 * Value: 0x0 15369 * - eXtension 15370 * Bit 31 15371 * Purpose: specify whether another tx queue group info element follows 15372 * Value: 0 -> no more tx queue group information elements 15373 * 1 -> another tx queue group information element immediately follows 15374 * - ac_mask 15375 * Bits 15:0 15376 * Purpose: specify which Access Categories belong to the tx queue group 15377 * Value: bit-OR of masks for the ACs (WMM and extension) that belong to 15378 * the tx queue group. 15379 * The AC bit-mask values are obtained by left-shifting by the 15380 * corresponding HTT_AC_WMM enum values, e.g. (1 << HTT_AC_WMM_BE) == 0x1 15381 * - vdev_id_mask 15382 * Bits 31:16 15383 * Purpose: specify which vdev's tx queues belong to the tx queue group 15384 * Value: bit-OR of masks based on the IDs of the vdevs whose tx queues 15385 * belong to the tx queue group. 15386 * For example, if vdev IDs 1 and 4 belong to a tx queue group, the 15387 * vdev_id_mask would be (1 << 1) | (1 << 4) = 0x12 15388 */ 15389 PREPACK struct htt_txq_group { 15390 A_UINT32 15391 credit_count: 14, 15392 sign: 1, 15393 absolute: 1, 15394 tx_queue_group_id: 8, 15395 reserved0: 7, 15396 extension: 1; 15397 A_UINT32 15398 ac_mask: 16, 15399 vdev_id_mask: 16; 15400 } POSTPACK; 15401 15402 /* first word */ 15403 #define HTT_TXQ_GROUP_CREDIT_COUNT_S 0 15404 #define HTT_TXQ_GROUP_CREDIT_COUNT_M 0x00003fff 15405 #define HTT_TXQ_GROUP_SIGN_S 14 15406 #define HTT_TXQ_GROUP_SIGN_M 0x00004000 15407 #define HTT_TXQ_GROUP_ABS_S 15 15408 #define HTT_TXQ_GROUP_ABS_M 0x00008000 15409 #define HTT_TXQ_GROUP_ID_S 16 15410 #define HTT_TXQ_GROUP_ID_M 0x00ff0000 15411 #define HTT_TXQ_GROUP_EXT_S 31 15412 #define HTT_TXQ_GROUP_EXT_M 0x80000000 15413 /* second word */ 15414 #define HTT_TXQ_GROUP_AC_MASK_S 0 15415 #define HTT_TXQ_GROUP_AC_MASK_M 0x0000ffff 15416 #define HTT_TXQ_GROUP_VDEV_ID_MASK_S 16 15417 #define HTT_TXQ_GROUP_VDEV_ID_MASK_M 0xffff0000 15418 15419 #define HTT_TXQ_GROUP_CREDIT_COUNT_SET(_info, _val) \ 15420 do { \ 15421 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_CREDIT_COUNT, _val); \ 15422 ((_info) |= ((_val) << HTT_TXQ_GROUP_CREDIT_COUNT_S)); \ 15423 } while (0) 15424 #define HTT_TXQ_GROUP_CREDIT_COUNT_GET(_info) \ 15425 (((_info) & HTT_TXQ_GROUP_CREDIT_COUNT_M) >> HTT_TXQ_GROUP_CREDIT_COUNT_S) 15426 15427 #define HTT_TXQ_GROUP_SIGN_SET(_info, _val) \ 15428 do { \ 15429 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_SIGN, _val); \ 15430 ((_info) |= ((_val) << HTT_TXQ_GROUP_SIGN_S)); \ 15431 } while (0) 15432 #define HTT_TXQ_GROUP_SIGN_GET(_info) \ 15433 (((_info) & HTT_TXQ_GROUP_SIGN_M) >> HTT_TXQ_GROUP_SIGN_S) 15434 15435 #define HTT_TXQ_GROUP_ABS_SET(_info, _val) \ 15436 do { \ 15437 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ABS, _val); \ 15438 ((_info) |= ((_val) << HTT_TXQ_GROUP_ABS_S)); \ 15439 } while (0) 15440 #define HTT_TXQ_GROUP_ABS_GET(_info) \ 15441 (((_info) & HTT_TXQ_GROUP_ABS_M) >> HTT_TXQ_GROUP_ABS_S) 15442 15443 #define HTT_TXQ_GROUP_ID_SET(_info, _val) \ 15444 do { \ 15445 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ID, _val); \ 15446 ((_info) |= ((_val) << HTT_TXQ_GROUP_ID_S)); \ 15447 } while (0) 15448 #define HTT_TXQ_GROUP_ID_GET(_info) \ 15449 (((_info) & HTT_TXQ_GROUP_ID_M) >> HTT_TXQ_GROUP_ID_S) 15450 15451 #define HTT_TXQ_GROUP_EXT_SET(_info, _val) \ 15452 do { \ 15453 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_EXT, _val); \ 15454 ((_info) |= ((_val) << HTT_TXQ_GROUP_EXT_S)); \ 15455 } while (0) 15456 #define HTT_TXQ_GROUP_EXT_GET(_info) \ 15457 (((_info) & HTT_TXQ_GROUP_EXT_M) >> HTT_TXQ_GROUP_EXT_S) 15458 15459 #define HTT_TXQ_GROUP_AC_MASK_SET(_info, _val) \ 15460 do { \ 15461 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_AC_MASK, _val); \ 15462 ((_info) |= ((_val) << HTT_TXQ_GROUP_AC_MASK_S)); \ 15463 } while (0) 15464 #define HTT_TXQ_GROUP_AC_MASK_GET(_info) \ 15465 (((_info) & HTT_TXQ_GROUP_AC_MASK_M) >> HTT_TXQ_GROUP_AC_MASK_S) 15466 15467 #define HTT_TXQ_GROUP_VDEV_ID_MASK_SET(_info, _val) \ 15468 do { \ 15469 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_VDEV_ID_MASK, _val); \ 15470 ((_info) |= ((_val) << HTT_TXQ_GROUP_VDEV_ID_MASK_S)); \ 15471 } while (0) 15472 #define HTT_TXQ_GROUP_VDEV_ID_MASK_GET(_info) \ 15473 (((_info) & HTT_TXQ_GROUP_VDEV_ID_MASK_M) >> HTT_TXQ_GROUP_VDEV_ID_MASK_S) 15474 15475 /** 15476 * @brief target -> host TX completion indication message definition 15477 * 15478 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_COMPL_IND 15479 * 15480 * @details 15481 * The following diagram shows the format of the TX completion indication sent 15482 * from the target to the host 15483 * 15484 * |31 30|29|28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| 15485 * |-------------------------------------------------------------------| 15486 * header: |rsvd |A4|A3|A2|TP|A1|A0| num | t_i| tid |status| msg_type | 15487 * |-------------------------------------------------------------------| 15488 * payload:| MSDU1 ID | MSDU0 ID | 15489 * |-------------------------------------------------------------------| 15490 * : MSDU3 ID | MSDU2 ID : 15491 * |-------------------------------------------------------------------| 15492 * | struct htt_tx_compl_ind_append_retries | 15493 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 15494 * | struct htt_tx_compl_ind_append_tx_tstamp | 15495 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 15496 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | 15497 * |-------------------------------------------------------------------| 15498 * : MSDU3 ACK RSSI | MSDU2 ACK RSSI : 15499 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 15500 * | MSDU0 tx_tsf64_low | 15501 * |-------------------------------------------------------------------| 15502 * | MSDU0 tx_tsf64_high | 15503 * |-------------------------------------------------------------------| 15504 * | MSDU1 tx_tsf64_low | 15505 * |-------------------------------------------------------------------| 15506 * | MSDU1 tx_tsf64_high | 15507 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 15508 * | phy_timestamp | 15509 * |-------------------------------------------------------------------| 15510 * | rate specs (see below) | 15511 * |-------------------------------------------------------------------| 15512 * | seqctrl | framectrl | 15513 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 15514 * Where: 15515 * A0 = append (a.k.a. append0) 15516 * A1 = append1 15517 * TP = MSDU tx power presence 15518 * A2 = append2 15519 * A3 = append3 15520 * A4 = append4 15521 * 15522 * The following field definitions describe the format of the TX completion 15523 * indication sent from the target to the host 15524 * Header fields: 15525 * - msg_type 15526 * Bits 7:0 15527 * Purpose: identifies this as HTT TX completion indication 15528 * Value: 0x7 (HTT_T2H_MSG_TYPE_TX_COMPL_IND) 15529 * - status 15530 * Bits 10:8 15531 * Purpose: the TX completion status of payload fragmentations descriptors 15532 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD 15533 * - tid 15534 * Bits 14:11 15535 * Purpose: the tid associated with those fragmentation descriptors. It is 15536 * valid or not, depending on the tid_invalid bit. 15537 * Value: 0 to 15 15538 * - tid_invalid 15539 * Bits 15:15 15540 * Purpose: this bit indicates whether the tid field is valid or not 15541 * Value: 0 indicates valid; 1 indicates invalid 15542 * - num 15543 * Bits 23:16 15544 * Purpose: the number of payload in this indication 15545 * Value: 1 to 255 15546 * - append (a.k.a. append0) 15547 * Bits 24:24 15548 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains 15549 * the number of tx retries for one MSDU at the end of this message 15550 * Value: 0 indicates no appending; 1 indicates appending 15551 * - append1 15552 * Bits 25:25 15553 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which 15554 * contains the timestamp info for each TX msdu id in payload. 15555 * The order of the timestamps matches the order of the MSDU IDs. 15556 * Note that a big-endian host needs to account for the reordering 15557 * of MSDU IDs within each 4-byte MSDU ID pair (during endianness 15558 * conversion) when determining which tx timestamp corresponds to 15559 * which MSDU ID. 15560 * Value: 0 indicates no appending; 1 indicates appending 15561 * - msdu_tx_power_presence 15562 * Bits 26:26 15563 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report 15564 * for each MSDU referenced by the TX_COMPL_IND message. 15565 * The tx power is reported in 0.5 dBm units. 15566 * The order of the per-MSDU tx power reports matches the order 15567 * of the MSDU IDs. 15568 * Note that a big-endian host needs to account for the reordering 15569 * of MSDU IDs within each 4-byte MSDU ID pair (during endianness 15570 * conversion) when determining which Tx Power corresponds to 15571 * which MSDU ID. 15572 * Value: 0 indicates MSDU tx power reports are not appended, 15573 * 1 indicates MSDU tx power reports are appended 15574 * - append2 15575 * Bits 27:27 15576 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in 15577 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report 15578 * matches the order of the MSDU IDs. Although the ACK RSSI is the 15579 * same for all MSDUs within a single PPDU, the RSSI is duplicated 15580 * for each MSDU, for convenience. 15581 * The ACK RSSI values are valid when status is COMPLETE_OK (and 15582 * this append2 bit is set). 15583 * The ACK RSSI values are SNR in dB, i.e. are the RSSI in units of 15584 * dB above the noise floor. 15585 * Value: 0 indicates MSDU ACK RSSI values are not appended, 15586 * 1 indicates MSDU ACK RSSI values are appended. 15587 * - append3 15588 * Bits 28:28 15589 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tsf64 which 15590 * contains the tx tsf info based on wlan global TSF for 15591 * each TX msdu id in payload. 15592 * The order of the tx tsf matches the order of the MSDU IDs. 15593 * The struct htt_tx_compl_ind_append_tx_tsf64 contains two 32-bits 15594 * values to indicate the the lower 32 bits and higher 32 bits of 15595 * the tx tsf. 15596 * The tx_tsf64 here represents the time MSDU was acked and the 15597 * tx_tsf64 has microseconds units. 15598 * Value: 0 indicates no appending; 1 indicates appending 15599 * - append4 15600 * Bits 29:29 15601 * Purpose: Indicate whether data frame control fields and fields required 15602 * for radio tap header are appended for each MSDU in TX_COMP_IND 15603 * message. The order of the this message matches the order of 15604 * the MSDU IDs. 15605 * Value: 0 indicates frame control fields and fields required for 15606 * radio tap header values are not appended, 15607 * 1 indicates frame control fields and fields required for 15608 * radio tap header values are appended. 15609 * Payload fields: 15610 * - hmsdu_id 15611 * Bits 15:0 15612 * Purpose: this ID is used to track the Tx buffer in host 15613 * Value: 0 to "size of host MSDU descriptor pool - 1" 15614 */ 15615 15616 PREPACK struct htt_tx_data_hdr_information { 15617 A_UINT32 phy_timestamp_l32; /* word 0 [31:0] */ 15618 A_UINT32 /* word 1 */ 15619 /* preamble: 15620 * 0-OFDM, 15621 * 1-CCk, 15622 * 2-HT, 15623 * 3-VHT 15624 */ 15625 preamble: 2, /* [1:0] */ 15626 /* mcs: 15627 * In case of HT preamble interpret 15628 * MCS along with NSS. 15629 * Valid values for HT are 0 to 7. 15630 * HT mcs 0 with NSS 2 is mcs 8. 15631 * Valid values for VHT are 0 to 9. 15632 */ 15633 mcs: 4, /* [5:2] */ 15634 /* rate: 15635 * This is applicable only for 15636 * CCK and OFDM preamble type 15637 * rate 0: OFDM 48 Mbps, 15638 * 1: OFDM 24 Mbps, 15639 * 2: OFDM 12 Mbps 15640 * 3: OFDM 6 Mbps 15641 * 4: OFDM 54 Mbps 15642 * 5: OFDM 36 Mbps 15643 * 6: OFDM 18 Mbps 15644 * 7: OFDM 9 Mbps 15645 * rate 0: CCK 11 Mbps Long 15646 * 1: CCK 5.5 Mbps Long 15647 * 2: CCK 2 Mbps Long 15648 * 3: CCK 1 Mbps Long 15649 * 4: CCK 11 Mbps Short 15650 * 5: CCK 5.5 Mbps Short 15651 * 6: CCK 2 Mbps Short 15652 */ 15653 rate : 3, /* [ 8: 6] */ 15654 rssi : 8, /* [16: 9] units=dBm */ 15655 nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */ 15656 bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */ 15657 stbc : 1, /* [22] */ 15658 sgi : 1, /* [23] */ 15659 ldpc : 1, /* [24] */ 15660 beamformed: 1, /* [25] */ 15661 /* tx_retry_cnt: 15662 * Indicates retry count of data tx frames provided by the host. 15663 */ 15664 tx_retry_cnt: 6; /* [31:26] */ 15665 A_UINT32 /* word 2 */ 15666 framectrl:16, /* [15: 0] */ 15667 seqno:16; /* [31:16] */ 15668 } POSTPACK; 15669 15670 15671 #define HTT_TX_COMPL_IND_STATUS_S 8 15672 #define HTT_TX_COMPL_IND_STATUS_M 0x00000700 15673 #define HTT_TX_COMPL_IND_TID_S 11 15674 #define HTT_TX_COMPL_IND_TID_M 0x00007800 15675 #define HTT_TX_COMPL_IND_TID_INV_S 15 15676 #define HTT_TX_COMPL_IND_TID_INV_M 0x00008000 15677 #define HTT_TX_COMPL_IND_NUM_S 16 15678 #define HTT_TX_COMPL_IND_NUM_M 0x00ff0000 15679 #define HTT_TX_COMPL_IND_APPEND_S 24 15680 #define HTT_TX_COMPL_IND_APPEND_M 0x01000000 15681 #define HTT_TX_COMPL_IND_APPEND1_S 25 15682 #define HTT_TX_COMPL_IND_APPEND1_M 0x02000000 15683 #define HTT_TX_COMPL_IND_TX_POWER_S 26 15684 #define HTT_TX_COMPL_IND_TX_POWER_M 0x04000000 15685 #define HTT_TX_COMPL_IND_APPEND2_S 27 15686 #define HTT_TX_COMPL_IND_APPEND2_M 0x08000000 15687 #define HTT_TX_COMPL_IND_APPEND3_S 28 15688 #define HTT_TX_COMPL_IND_APPEND3_M 0x10000000 15689 #define HTT_TX_COMPL_IND_APPEND4_S 29 15690 #define HTT_TX_COMPL_IND_APPEND4_M 0x20000000 15691 15692 #define HTT_TX_COMPL_IND_STATUS_SET(_info, _val) \ 15693 do { \ 15694 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_STATUS, _val); \ 15695 ((_info) |= ((_val) << HTT_TX_COMPL_IND_STATUS_S)); \ 15696 } while (0) 15697 #define HTT_TX_COMPL_IND_STATUS_GET(_info) \ 15698 (((_info) & HTT_TX_COMPL_IND_STATUS_M) >> HTT_TX_COMPL_IND_STATUS_S) 15699 #define HTT_TX_COMPL_IND_NUM_SET(_info, _val) \ 15700 do { \ 15701 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_NUM, _val); \ 15702 ((_info) |= ((_val) << HTT_TX_COMPL_IND_NUM_S)); \ 15703 } while (0) 15704 #define HTT_TX_COMPL_IND_NUM_GET(_info) \ 15705 (((_info) & HTT_TX_COMPL_IND_NUM_M) >> HTT_TX_COMPL_IND_NUM_S) 15706 #define HTT_TX_COMPL_IND_TID_SET(_info, _val) \ 15707 do { \ 15708 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID, _val); \ 15709 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_S)); \ 15710 } while (0) 15711 #define HTT_TX_COMPL_IND_TID_GET(_info) \ 15712 (((_info) & HTT_TX_COMPL_IND_TID_M) >> HTT_TX_COMPL_IND_TID_S) 15713 #define HTT_TX_COMPL_IND_TID_INV_SET(_info, _val) \ 15714 do { \ 15715 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID_INV, _val); \ 15716 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_INV_S)); \ 15717 } while (0) 15718 #define HTT_TX_COMPL_IND_TID_INV_GET(_info) \ 15719 (((_info) & HTT_TX_COMPL_IND_TID_INV_M) >> \ 15720 HTT_TX_COMPL_IND_TID_INV_S) 15721 #define HTT_TX_COMPL_IND_APPEND_SET(_info, _val) \ 15722 do { \ 15723 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND, _val); \ 15724 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND_S)); \ 15725 } while (0) 15726 #define HTT_TX_COMPL_IND_APPEND_GET(_info) \ 15727 (((_info) & HTT_TX_COMPL_IND_APPEND_M) >> HTT_TX_COMPL_IND_APPEND_S) 15728 #define HTT_TX_COMPL_IND_APPEND1_SET(_info, _val) \ 15729 do { \ 15730 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND1, _val); \ 15731 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND1_S)); \ 15732 } while (0) 15733 #define HTT_TX_COMPL_IND_APPEND1_GET(_info) \ 15734 (((_info) & HTT_TX_COMPL_IND_APPEND1_M) >> HTT_TX_COMPL_IND_APPEND1_S) 15735 #define HTT_TX_COMPL_IND_TX_POWER_SET(_info, _val) \ 15736 do { \ 15737 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TX_POWER, _val); \ 15738 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TX_POWER_S)); \ 15739 } while (0) 15740 #define HTT_TX_COMPL_IND_TX_POWER_GET(_info) \ 15741 (((_info) & HTT_TX_COMPL_IND_TX_POWER_M) >> HTT_TX_COMPL_IND_TX_POWER_S) 15742 #define HTT_TX_COMPL_IND_APPEND2_SET(_info, _val) \ 15743 do { \ 15744 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND2, _val); \ 15745 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND2_S)); \ 15746 } while (0) 15747 #define HTT_TX_COMPL_IND_APPEND2_GET(_info) \ 15748 (((_info) & HTT_TX_COMPL_IND_APPEND2_M) >> HTT_TX_COMPL_IND_APPEND2_S) 15749 #define HTT_TX_COMPL_IND_APPEND3_SET(_info, _val) \ 15750 do { \ 15751 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND3, _val); \ 15752 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND3_S)); \ 15753 } while (0) 15754 #define HTT_TX_COMPL_IND_APPEND3_GET(_info) \ 15755 (((_info) & HTT_TX_COMPL_IND_APPEND3_M) >> HTT_TX_COMPL_IND_APPEND3_S) 15756 #define HTT_TX_COMPL_IND_APPEND4_SET(_info, _val) \ 15757 do { \ 15758 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND4, _val); \ 15759 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND4_S)); \ 15760 } while (0) 15761 #define HTT_TX_COMPL_IND_APPEND4_GET(_info) \ 15762 (((_info) & HTT_TX_COMPL_IND_APPEND4_M) >> HTT_TX_COMPL_IND_APPEND4_S) 15763 15764 #define HTT_TX_COMPL_INV_TX_POWER 0xffff 15765 15766 #define HTT_TX_COMPL_CTXT_SZ sizeof(A_UINT16) 15767 #define HTT_TX_COMPL_CTXT_NUM(_bytes) ((_bytes) >> 1) 15768 15769 #define HTT_TX_COMPL_INV_MSDU_ID 0xffff 15770 15771 #define HTT_TX_COMPL_IND_STAT_OK 0 15772 /* DISCARD: 15773 * current meaning: 15774 * MSDUs were queued for transmission but filtered by HW or SW 15775 * without any over the air attempts 15776 * legacy meaning (HL Rome): 15777 * MSDUs were discarded by the target FW without any over the air 15778 * attempts due to lack of space 15779 */ 15780 #define HTT_TX_COMPL_IND_STAT_DISCARD 1 15781 /* NO_ACK: 15782 * MSDUs were transmitted (repeatedly) but no ACK was received from the peer 15783 */ 15784 #define HTT_TX_COMPL_IND_STAT_NO_ACK 2 15785 /* POSTPONE: 15786 * temporarily-undeliverable MSDUs were deleted to free up space, but should 15787 * be downloaded again later (in the appropriate order), when they are 15788 * deliverable. 15789 */ 15790 #define HTT_TX_COMPL_IND_STAT_POSTPONE 3 15791 /* 15792 * The PEER_DEL tx completion status is used for HL cases 15793 * where the peer the frame is for has been deleted. 15794 * The host has already discarded its copy of the frame, but 15795 * it still needs the tx completion to restore its credit. 15796 */ 15797 #define HTT_TX_COMPL_IND_STAT_PEER_DEL 4 15798 /* DROP: MSDUs dropped due to lack of space (congestion control) */ 15799 #define HTT_TX_COMPL_IND_STAT_DROP 5 15800 #define HTT_TX_COMPL_IND_STAT_HOST_INSPECT 6 15801 15802 15803 #define HTT_TX_COMPL_IND_APPEND_SET_MORE_RETRY(f) ((f) |= 0x1) 15804 #define HTT_TX_COMPL_IND_APPEND_CLR_MORE_RETRY(f) ((f) &= (~0x1)) 15805 15806 PREPACK struct htt_tx_compl_ind_base { 15807 A_UINT32 hdr; 15808 A_UINT16 payload[1/*or more*/]; 15809 } POSTPACK; 15810 15811 PREPACK struct htt_tx_compl_ind_append_retries { 15812 A_UINT16 msdu_id; 15813 A_UINT8 tx_retries; 15814 A_UINT8 flag; /* Bit 0, 1: another append_retries struct is appended 15815 0: this is the last append_retries struct */ 15816 } POSTPACK; 15817 15818 PREPACK struct htt_tx_compl_ind_append_tx_tstamp { 15819 A_UINT32 timestamp[1/*or more*/]; 15820 } POSTPACK; 15821 15822 PREPACK struct htt_tx_compl_ind_append_tx_tsf64 { 15823 A_UINT32 tx_tsf64_low; 15824 A_UINT32 tx_tsf64_high; 15825 } POSTPACK; 15826 15827 /* htt_tx_data_hdr_information payload extension fields: */ 15828 15829 /* DWORD zero */ 15830 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M 0xffffffff 15831 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S 0 15832 15833 /* DWORD one */ 15834 #define HTT_FW_TX_DATA_HDR_PREAMBLE_M 0x00000003 15835 #define HTT_FW_TX_DATA_HDR_PREAMBLE_S 0 15836 #define HTT_FW_TX_DATA_HDR_MCS_M 0x0000003c 15837 #define HTT_FW_TX_DATA_HDR_MCS_S 2 15838 #define HTT_FW_TX_DATA_HDR_RATE_M 0x000001c0 15839 #define HTT_FW_TX_DATA_HDR_RATE_S 6 15840 #define HTT_FW_TX_DATA_HDR_RSSI_M 0x0001fe00 15841 #define HTT_FW_TX_DATA_HDR_RSSI_S 9 15842 #define HTT_FW_TX_DATA_HDR_NSS_M 0x00060000 15843 #define HTT_FW_TX_DATA_HDR_NSS_S 17 15844 #define HTT_FW_TX_DATA_HDR_BW_M 0x00380000 15845 #define HTT_FW_TX_DATA_HDR_BW_S 19 15846 #define HTT_FW_TX_DATA_HDR_STBC_M 0x00400000 15847 #define HTT_FW_TX_DATA_HDR_STBC_S 22 15848 #define HTT_FW_TX_DATA_HDR_SGI_M 0x00800000 15849 #define HTT_FW_TX_DATA_HDR_SGI_S 23 15850 #define HTT_FW_TX_DATA_HDR_LDPC_M 0x01000000 15851 #define HTT_FW_TX_DATA_HDR_LDPC_S 24 15852 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_M 0x02000000 15853 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_S 25 15854 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M 0xfc000000 15855 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S 26 15856 15857 /* DWORD two */ 15858 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_M 0x0000ffff 15859 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_S 0 15860 #define HTT_FW_TX_DATA_HDR_SEQNO_M 0xffff0000 15861 #define HTT_FW_TX_DATA_HDR_SEQNO_S 16 15862 15863 15864 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_SET(word, value) \ 15865 do { \ 15866 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32, value); \ 15867 (word) |= (value) << HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S; \ 15868 } while (0) 15869 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_GET(word) \ 15870 (((word) & HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M) >> HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S) 15871 15872 #define HTT_FW_TX_DATA_HDR_PREAMBLE_SET(word, value) \ 15873 do { \ 15874 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PREAMBLE, value); \ 15875 (word) |= (value) << HTT_FW_TX_DATA_HDR_PREAMBLE_S; \ 15876 } while (0) 15877 #define HTT_FW_TX_DATA_HDR_PREAMBLE_GET(word) \ 15878 (((word) & HTT_FW_TX_DATA_HDR_PREAMBLE_M) >> HTT_FW_TX_DATA_HDR_PREAMBLE_S) 15879 15880 #define HTT_FW_TX_DATA_HDR_MCS_SET(word, value) \ 15881 do { \ 15882 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_MCS, value); \ 15883 (word) |= (value) << HTT_FW_TX_DATA_HDR_MCS_S; \ 15884 } while (0) 15885 #define HTT_FW_TX_DATA_HDR_MCS_GET(word) \ 15886 (((word) & HTT_FW_TX_DATA_HDR_MCS_M) >> HTT_FW_TX_DATA_HDR_MCS_S) 15887 15888 #define HTT_FW_TX_DATA_HDR_RATE_SET(word, value) \ 15889 do { \ 15890 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RATE, value); \ 15891 (word) |= (value) << HTT_FW_TX_DATA_HDR_RATE_S; \ 15892 } while (0) 15893 #define HTT_FW_TX_DATA_HDR_RATE_GET(word) \ 15894 (((word) & HTT_FW_TX_DATA_HDR_RATE_M) >> HTT_FW_TX_DATA_HDR_RATE_S) 15895 15896 #define HTT_FW_TX_DATA_HDR_RSSI_SET(word, value) \ 15897 do { \ 15898 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RSSI, value); \ 15899 (word) |= (value) << HTT_FW_TX_DATA_HDR_RSSI_S; \ 15900 } while (0) 15901 #define HTT_FW_TX_DATA_HDR_RSSI_GET(word) \ 15902 (((word) & HTT_FW_TX_DATA_HDR_RSSI_M) >> HTT_FW_TX_DATA_HDR_RSSI_S) 15903 15904 15905 #define HTT_FW_TX_DATA_HDR_NSS_SET(word, value) \ 15906 do { \ 15907 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_NSS, value); \ 15908 (word) |= (value) << HTT_FW_TX_DATA_HDR_NSS_S; \ 15909 } while (0) 15910 #define HTT_FW_TX_DATA_HDR_NSS_GET(word) \ 15911 (((word) & HTT_FW_TX_DATA_HDR_NSS_M) >> HTT_FW_TX_DATA_HDR_NSS_S) 15912 15913 #define HTT_FW_TX_DATA_HDR_BW_SET(word, value) \ 15914 do { \ 15915 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BW, value); \ 15916 (word) |= (value) << HTT_FW_TX_DATA_HDR_BW_S; \ 15917 } while (0) 15918 #define HTT_FW_TX_DATA_HDR_BW_GET(word) \ 15919 (((word) & HTT_FW_TX_DATA_HDR_BW_M) >> HTT_FW_TX_DATA_HDR_BW_S) 15920 15921 15922 #define HTT_FW_TX_DATA_HDR_STBC_SET(word, value) \ 15923 do { \ 15924 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_STBC, value); \ 15925 (word) |= (value) << HTT_FW_TX_DATA_HDR_STBC_S; \ 15926 } while (0) 15927 #define HTT_FW_TX_DATA_HDR_STBC_GET(word) \ 15928 (((word) & HTT_FW_TX_DATA_HDR_STBC_M) >> HTT_FW_TX_DATA_HDR_STBC_S) 15929 15930 15931 #define HTT_FW_TX_DATA_HDR_SGI_SET(word, value) \ 15932 do { \ 15933 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SGI, value); \ 15934 (word) |= (value) << HTT_FW_TX_DATA_HDR_SGI_S; \ 15935 } while (0) 15936 #define HTT_FW_TX_DATA_HDR_SGI_GET(word) \ 15937 (((word) & HTT_FW_TX_DATA_HDR_SGI_M) >> HTT_FW_TX_DATA_HDR_SGI_S) 15938 15939 #define HTT_FW_TX_DATA_HDR_LDPC_SET(word, value) \ 15940 do { \ 15941 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_LDPC, value); \ 15942 (word) |= (value) << HTT_FW_TX_DATA_HDR_LDPC_S; \ 15943 } while (0) 15944 #define HTT_FW_TX_DATA_HDR_LDPC_GET(word) \ 15945 (((word) & HTT_FW_TX_DATA_HDR_LDPC_M) >> HTT_FW_TX_DATA_HDR_LDPC_S) 15946 15947 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_SET(word, value) \ 15948 do { \ 15949 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BEAMFORMED, value); \ 15950 (word) |= (value) << HTT_FW_TX_DATA_HDR_BEAMFORMED_S; \ 15951 } while (0) 15952 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_GET(word) \ 15953 (((word) & HTT_FW_TX_DATA_HDR_BEAMFORMED_M) >> HTT_FW_TX_DATA_HDR_BEAMFORMED_S) 15954 15955 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_SET(word, value) \ 15956 do { \ 15957 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_TX_RETRY_CNT, value); \ 15958 (word) |= (value) << HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S; \ 15959 } while (0) 15960 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_GET(word) \ 15961 (((word) & HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M) >> HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S) 15962 15963 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_SET(word, value) \ 15964 do { \ 15965 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_FRAMECTRL, value); \ 15966 (word) |= (value) << HTT_FW_TX_DATA_HDR_FRAMECTRL_S; \ 15967 } while (0) 15968 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_GET(word) \ 15969 (((word) & HTT_FW_TX_DATA_HDR_FRAMECTRL_M) >> HTT_FW_TX_DATA_HDR_FRAMECTRL_S) 15970 15971 15972 #define HTT_FW_TX_DATA_HDR_SEQNO_SET(word, value) \ 15973 do { \ 15974 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SEQNO, value); \ 15975 (word) |= (value) << HTT_FW_TX_DATA_HDR_SEQNO_S; \ 15976 } while (0) 15977 #define HTT_FW_TX_DATA_HDR_SEQNO_GET(word) \ 15978 (((word) & HTT_FW_TX_DATA_HDR_SEQNO_M) >> HTT_FW_TX_DATA_HDR_SEQNO_S) 15979 15980 15981 /** 15982 * @brief target -> host software UMAC TX completion indication message 15983 * 15984 * MSG_TYPE => HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND 15985 * 15986 * @details 15987 * The following diagram shows the format of the soft UMAC TX completion 15988 * indication sent from the target to the host 15989 * 15990 * |31 30|29|28|27|26 20|19 17|16|15 12|11|10| 9|8|7 4|3 1|0| 15991 * |-------------------------------------+----------------+------------| 15992 * hdr: | rsvd | msdu_cnt | msg_type | 15993 * pyld: |===================================================================| 15994 * MSDU 0| buf addr low (bits 31:0) | 15995 * |-----------------------------------------------+------+------------| 15996 * | SW buffer cookie | RS | buf addr hi| 15997 * |--------+--+--+-------------+--------+---------+------+------------| 15998 * | rsvd0 | M| V| tx count | TID | SW peer ID | 15999 * |--------+--+--+-------------+--------+----------------------+------| 16000 * | frametype | TQM status number | RELR | 16001 * |-----+-----+-----------------------------------+--+-+-+-----+------| 16002 * |rsvd1| buffer timestamp | A|L|F| ACK RSSI | 16003 * |-----+--+-------------------------+--+------+-----+--+-+-----+---+-| 16004 * | rsvd2 | tones in RU |OF|tx MCS|txSGI|LC|S|PKTYP|BW |I| 16005 * |--------+-------------------------+--+------+-----+--+-+-----+---+-| 16006 * | PPDU transmission TSF | 16007 * |-------------------------------------------------------------------| 16008 * | rsvd3 | 16009 * |===================================================================| 16010 * MSDU 1| buf addr low (bits 31:0) | 16011 * : ... : 16012 * | rsvd3 | 16013 * |===================================================================| 16014 * etc. 16015 * 16016 * Where: 16017 * RS = release source 16018 * V = valid 16019 * M = multicast 16020 * RELR = release reason 16021 * F = first MSDU 16022 * L = last MSDU 16023 * A = MSDU is part of A-MSDU 16024 * I = rate info valid 16025 * PKTYP = packet type 16026 * S = STBC 16027 * LC = LDPC 16028 * OF = OFDMA transmission 16029 */ 16030 typedef enum { 16031 /* 0 (REASON_FRAME_ACKED): 16032 * Corresponds to tqm_release_reason = <enum 0 tqm_rr_frame_acked>; 16033 * frame is removed because an ACK of BA for it was received. 16034 */ 16035 HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED, 16036 16037 /* 1 (REASON_REMOVE_CMD_FW): 16038 * Corresponds to tqm_release_reason = <enum 1 tqm_rr_rem_cmd_rem>; 16039 * frame is removed because a remove command of type "Remove_mpdus" 16040 * initiated by SW. 16041 */ 16042 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_FW, 16043 16044 /* 2 (REASON_REMOVE_CMD_TX): 16045 * Corresponds to tqm_release_reason = <enum 2 tqm_rr_rem_cmd_tx>; 16046 * frame is removed because a remove command of type 16047 * "Remove_transmitted_mpdus" initiated by SW. 16048 */ 16049 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX, 16050 16051 /* 3 (REASON_REMOVE_CMD_NOTX): 16052 * Corresponds to tqm_release_reason = <enum 3 tqm_rr_rem_cmd_notx>; 16053 * frame is removed because a remove command of type 16054 * "Remove_untransmitted_mpdus" initiated by SW. 16055 */ 16056 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX, 16057 16058 /* 4 (REASON_REMOVE_CMD_AGED): 16059 * Corresponds to tqm_release_reason = <enum 4 tqm_rr_rem_cmd_aged>; 16060 * frame is removed because a remove command of type "Remove_aged_mpdus" 16061 * or "Remove_aged_msdus" initiated by SW. 16062 */ 16063 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED, 16064 16065 /* 5 (RELEASE_FW_REASON1): 16066 * Corresponds to tqm_release_reason = <enum 5 tqm_fw_reason1>; 16067 * frame is removed because a remove command where fw indicated that 16068 * remove reason is fw_reason1. 16069 */ 16070 HTT_TX_MSDU_RELEASE_FW_REASON1, 16071 16072 /* 6 (RELEASE_FW_REASON2): 16073 * Corresponds to tqm_release_reason = <enum 6 tqm_fw_reason2>; 16074 * frame is removed because a remove command where fw indicated that 16075 * remove reason is fw_reason1. 16076 */ 16077 HTT_TX_MSDU_RELEASE_FW_REASON2, 16078 16079 /* 7 (RELEASE_FW_REASON3): 16080 * Corresponds to tqm_release_reason = <enum 7 tqm_fw_reason3>; 16081 * frame is removed because a remove command where fw indicated that 16082 * remove reason is fw_reason1. 16083 */ 16084 HTT_TX_MSDU_RELEASE_FW_REASON3, 16085 16086 /* 8 (REASON_REMOVE_CMD_DISABLEQ): 16087 * Corresponds to tqm_release_reason = <enum 8 tqm_rr_rem_cmd_disable_queue> 16088 * frame is removed because a remove command of type 16089 * "remove_mpdus_and_disable_queue" or "remove_msdus_and_disable_flow" 16090 * initiated by SW. 16091 */ 16092 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ, 16093 16094 /* 9 (REASON_DROP_MISC): 16095 * Corresponds to sw_release_reason = Packet dropped by FW due to 16096 * any discard reason that is not categorized as MSDU TTL expired. 16097 * Examples: TXDE ENQ layer dropped the packet due to peer delete, 16098 * tid delete, no resource credit available. 16099 */ 16100 HTT_TX_MSDU_RELEASE_REASON_DROP_MISC, 16101 16102 /* 10 (REASON_DROP_TTL): 16103 * Corresponds to sw_release_reason = Packet dropped by FW due to 16104 * discard reason that frame is not transmitted due to MSDU TTL expired. 16105 */ 16106 HTT_TX_MSDU_RELEASE_REASON_DROP_TTL, 16107 16108 /* 11 - available for use */ 16109 /* 12 - available for use */ 16110 /* 13 - available for use */ 16111 /* 14 - available for use */ 16112 /* 15 - available for use */ 16113 16114 HTT_TX_MSDU_RELEASE_REASON_MAX = 16 16115 } htt_t2h_tx_msdu_release_reason_e; 16116 16117 typedef enum { 16118 /* 0 (RELEASE_SOURCE_FW): 16119 * MSDU released by FW even before the frame was queued to TQM-L HW. 16120 */ 16121 HTT_TX_MSDU_RELEASE_SOURCE_FW, 16122 16123 /* 1 (RELEASE_SOURCE_TQM_LITE): 16124 * MSDU released by TQM-L HW. 16125 */ 16126 HTT_TX_MSDU_RELEASE_SOURCE_TQM_LITE, 16127 16128 HTT_TX_MSDU_RELEASE_SOURCE_MAX = 8 16129 } htt_t2h_tx_msdu_release_source_e; 16130 16131 struct htt_t2h_tx_buffer_addr_info { /* 2 words */ 16132 A_UINT32 buffer_addr_31_0 : 32; /* [31:0] */ 16133 A_UINT32 buffer_addr_39_32 : 8, /* [7:0] */ 16134 /* release_source: 16135 * holds a htt_t2h_tx_msdu_release_source_e enum value 16136 */ 16137 release_source : 3, /* [10:8] */ 16138 sw_buffer_cookie : 21; /* [31:11] */ 16139 /* NOTE: 16140 * To preserve backwards compatibility, 16141 * no new fields can be added in this struct. 16142 */ 16143 }; 16144 16145 /* member definitions of htt_t2h_tx_buffer_addr_info */ 16146 16147 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF 16148 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S 0 16149 16150 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \ 16151 do { \ 16152 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0, value); \ 16153 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S; \ 16154 } while (0) 16155 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \ 16156 (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S) 16157 16158 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF 16159 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S 0 16160 16161 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \ 16162 do { \ 16163 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32, value); \ 16164 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S; \ 16165 } while (0) 16166 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \ 16167 (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S) 16168 16169 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M 0x00000700 16170 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S 8 16171 16172 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_SET(word, value) \ 16173 do { \ 16174 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE, value); \ 16175 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S; \ 16176 } while (0) 16177 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(word) \ 16178 (((word) & HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M) >> HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S) 16179 16180 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF800 16181 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 11 16182 16183 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \ 16184 do { \ 16185 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \ 16186 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \ 16187 } while (0) 16188 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \ 16189 (((word) & HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S) 16190 16191 struct htt_t2h_tx_rate_stats_info { /* 2 words */ 16192 /* word 0 */ 16193 A_UINT32 16194 /* tx_rate_stats_info_valid: 16195 * Indicates if the tx rate stats below are valid. 16196 */ 16197 tx_rate_stats_info_valid : 1, /* [0] */ 16198 /* transmit_bw: 16199 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16200 * Indicates the BW of the upcoming transmission that shall likely 16201 * start in about 3 -4 us on the medium: 16202 * <enum 0 transmit_bw_20_MHz> 16203 * <enum 1 transmit_bw_40_MHz> 16204 * <enum 2 transmit_bw_80_MHz> 16205 * <enum 3 transmit_bw_160_MHz> 16206 * <enum 4 transmit_bw_320_MHz> 16207 */ 16208 transmit_bw : 3, /* [3:1] */ 16209 /* transmit_pkt_type: 16210 * same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16211 * Field filled in by PDG. 16212 * Not valid when in SW transmit mode 16213 * The packet type 16214 * <enum_type PKT_TYPE_ENUM> 16215 * Type: enum Definition Name: PKT_TYPE_ENUM 16216 * enum number enum name Description 16217 * ------------------------------------ 16218 * 0 dot11a 802.11a PPDU type 16219 * 1 dot11b 802.11b PPDU type 16220 * 2 dot11n_mm 802.11n Mixed Mode PPDU type 16221 * 3 dot11ac 802.11ac PPDU type 16222 * 4 dot11ax 802.11ax PPDU type 16223 * 5 dot11ba 802.11ba (WUR) PPDU type 16224 * 6 dot11be 802.11be PPDU type 16225 * 7 dot11az 802.11az (ranging) PPDU type 16226 */ 16227 transmit_pkt_type : 4, /* [7:4] */ 16228 /* transmit_stbc: 16229 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16230 * Field filled in by PDG. 16231 * Not valid when in SW transmit mode 16232 * When set, STBC transmission rate was used. 16233 */ 16234 transmit_stbc : 1, /* [8] */ 16235 /* transmit_ldpc: 16236 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16237 * Field filled in by PDG. 16238 * Not valid when in SW transmit mode 16239 * When set, use LDPC transmission rates 16240 */ 16241 transmit_ldpc : 1, /* [9] */ 16242 /* transmit_sgi: 16243 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16244 * Field filled in by PDG. 16245 * Not valid when in SW transmit mode 16246 * <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used for HE 16247 * <enum 1 0_4_us_sgi > Legacy short GI. Can also be used for HE 16248 * <enum 2 1_6_us_sgi > HE related GI 16249 * <enum 3 3_2_us_sgi > HE related GI 16250 * <legal 0 - 3> 16251 */ 16252 transmit_sgi : 2, /* [11:10] */ 16253 /* transmit_mcs: 16254 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16255 * Field filled in by PDG. 16256 * Not valid when in SW transmit mode 16257 * 16258 * For details, refer to MCS_TYPE description 16259 * <legal all> 16260 * Pkt_type Related definition of MCS_TYPE 16261 * dot11b This field is the rate: 16262 * 0: CCK 11 Mbps Long 16263 * 1: CCK 5.5 Mbps Long 16264 * 2: CCK 2 Mbps Long 16265 * 3: CCK 1 Mbps Long 16266 * 4: CCK 11 Mbps Short 16267 * 5: CCK 5.5 Mbps Short 16268 * 6: CCK 2 Mbps Short 16269 * NOTE: The numbering here is NOT the same as the as MAC gives 16270 * in the "rate" field in the SIG given to the PHY. 16271 * The MAC will do an internal translation. 16272 * 16273 * Dot11a This field is the rate: 16274 * 0: OFDM 48 Mbps 16275 * 1: OFDM 24 Mbps 16276 * 2: OFDM 12 Mbps 16277 * 3: OFDM 6 Mbps 16278 * 4: OFDM 54 Mbps 16279 * 5: OFDM 36 Mbps 16280 * 6: OFDM 18 Mbps 16281 * 7: OFDM 9 Mbps 16282 * NOTE: The numbering here is NOT the same as the as MAC gives 16283 * in the "rate" field in the SIG given to the PHY. 16284 * The MAC will do an internal translation. 16285 * 16286 * Dot11n_mm (mixed mode) This field represends the MCS. 16287 * 0: HT MCS 0 (BPSK 1/2) 16288 * 1: HT MCS 1 (QPSK 1/2) 16289 * 2: HT MCS 2 (QPSK 3/4) 16290 * 3: HT MCS 3 (16-QAM 1/2) 16291 * 4: HT MCS 4 (16-QAM 3/4) 16292 * 5: HT MCS 5 (64-QAM 2/3) 16293 * 6: HT MCS 6 (64-QAM 3/4) 16294 * 7: HT MCS 7 (64-QAM 5/6) 16295 * NOTE: To get higher MCS's use the nss field to indicate the 16296 * number of spatial streams. 16297 * 16298 * Dot11ac This field represends the MCS. 16299 * 0: VHT MCS 0 (BPSK 1/2) 16300 * 1: VHT MCS 1 (QPSK 1/2) 16301 * 2: VHT MCS 2 (QPSK 3/4) 16302 * 3: VHT MCS 3 (16-QAM 1/2) 16303 * 4: VHT MCS 4 (16-QAM 3/4) 16304 * 5: VHT MCS 5 (64-QAM 2/3) 16305 * 6: VHT MCS 6 (64-QAM 3/4) 16306 * 7: VHT MCS 7 (64-QAM 5/6) 16307 * 8: VHT MCS 8 (256-QAM 3/4) 16308 * 9: VHT MCS 9 (256-QAM 5/6) 16309 * 10: VHT MCS 10 (1024-QAM 3/4) 16310 * 11: VHT MCS 11 (1024-QAM 5/6) 16311 * NOTE: There are several illegal VHT rates due to fractional 16312 * number of bits per symbol. 16313 * Below are the illegal rates for 4 streams and lower: 16314 * 20 MHz, 1 stream, MCS 9 16315 * 20 MHz, 2 stream, MCS 9 16316 * 20 MHz, 4 stream, MCS 9 16317 * 80 MHz, 3 stream, MCS 6 16318 * 160 MHz, 3 stream, MCS 9 (Unsupported) 16319 * 160 MHz, 4 stream, MCS 7 (Unsupported) 16320 * 16321 * dot11ax This field represends the MCS. 16322 * 0: HE MCS 0 (BPSK 1/2) 16323 * 1: HE MCS 1 (QPSK 1/2) 16324 * 2: HE MCS 2 (QPSK 3/4) 16325 * 3: HE MCS 3 (16-QAM 1/2) 16326 * 4: HE MCS 4 (16-QAM 3/4) 16327 * 5: HE MCS 5 (64-QAM 2/3) 16328 * 6: HE MCS 6 (64-QAM 3/4) 16329 * 7: HE MCS 7 (64-QAM 5/6) 16330 * 8: HE MCS 8 (256-QAM 3/4) 16331 * 9: HE MCS 9 (256-QAM 5/6) 16332 * 10: HE MCS 10 (1024-QAM 3/4) 16333 * 11: HE MCS 11 (1024-QAM 5/6) 16334 * 12: HE MCS 12 (4096-QAM 3/4) 16335 * 13: HE MCS 13 (4096-QAM 5/6) 16336 * 16337 * dot11ba This field is the rate: 16338 * 0: LDR 16339 * 1: HDR 16340 * 2: Exclusive rate 16341 */ 16342 transmit_mcs : 4, /* [15:12] */ 16343 /* ofdma_transmission: 16344 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16345 * Field filled in by PDG. 16346 * Set when the transmission was an OFDMA transmission (DL or UL). 16347 * <legal all> 16348 */ 16349 ofdma_transmission : 1, /* [16] */ 16350 /* tones_in_ru: 16351 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 16352 * Field filled in by PDG. 16353 * Not valid when in SW transmit mode 16354 * The number of tones in the RU used. 16355 * <legal all> 16356 */ 16357 tones_in_ru : 12, /* [28:17] */ 16358 rsvd2 : 3; /* [31:29] */ 16359 16360 /* word 1 */ 16361 /* ppdu_transmission_tsf: 16362 * Based on a HWSCH configuration register setting, 16363 * this field either contains: 16364 * Lower 32 bits of the TSF, snapshot of this value when transmission 16365 * of the PPDU containing the frame finished. 16366 * OR 16367 * Lower 32 bits of the TSF, snapshot of this value when transmission 16368 * of the PPDU containing the frame started. 16369 * <legal all> 16370 */ 16371 A_UINT32 ppdu_transmission_tsf; 16372 16373 /* NOTE: 16374 * To preserve backwards compatibility, 16375 * no new fields can be added in this struct. 16376 */ 16377 }; 16378 16379 /* member definitions of htt_t2h_tx_rate_stats_info */ 16380 16381 #define HTT_TX_RATE_STATS_INFO_VALID_M 0x00000001 16382 #define HTT_TX_RATE_STATS_INFO_VALID_S 0 16383 16384 #define HTT_TX_RATE_STATS_INFO_VALID_SET(word, value) \ 16385 do { \ 16386 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_VALID, value); \ 16387 (word) |= (value) << HTT_TX_RATE_STATS_INFO_VALID_S; \ 16388 } while (0) 16389 #define HTT_TX_RATE_STATS_INFO_VALID_GET(word) \ 16390 (((word) & HTT_TX_RATE_STATS_INFO_VALID_M) >> HTT_TX_RATE_STATS_INFO_VALID_S) 16391 16392 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M 0x0000000E 16393 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S 1 16394 16395 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_SET(word, value) \ 16396 do { \ 16397 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_BW, value); \ 16398 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S; \ 16399 } while (0) 16400 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(word) \ 16401 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S) 16402 16403 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M 0x000000F0 16404 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S 4 16405 16406 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_SET(word, value) \ 16407 do { \ 16408 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE, value); \ 16409 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S; \ 16410 } while (0) 16411 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(word) \ 16412 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S) 16413 16414 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M 0x00000100 16415 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S 8 16416 16417 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_SET(word, value) \ 16418 do { \ 16419 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC, value); \ 16420 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S; \ 16421 } while (0) 16422 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(word) \ 16423 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S) 16424 16425 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M 0x00000200 16426 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S 9 16427 16428 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_SET(word, value) \ 16429 do { \ 16430 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC, value); \ 16431 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S; \ 16432 } while (0) 16433 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(word) \ 16434 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S) 16435 16436 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M 0x00000C00 16437 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S 10 16438 16439 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_SET(word, value) \ 16440 do { \ 16441 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI, value); \ 16442 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S; \ 16443 } while (0) 16444 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(word) \ 16445 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S) 16446 16447 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M 0x0000F000 16448 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S 12 16449 16450 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_SET(word, value) \ 16451 do { \ 16452 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS, value); \ 16453 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S; \ 16454 } while (0) 16455 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(word) \ 16456 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S) 16457 16458 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M 0x00010000 16459 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S 16 16460 16461 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_SET(word, value) \ 16462 do { \ 16463 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION, value); \ 16464 (word) |= (value) << HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S; \ 16465 } while (0) 16466 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(word) \ 16467 (((word) & HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M) >> HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S) 16468 16469 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M 0x1FFE0000 16470 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S 17 16471 16472 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_SET(word, value) \ 16473 do { \ 16474 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TONES_IN_RU, value); \ 16475 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S; \ 16476 } while (0) 16477 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(word) \ 16478 (((word) & HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M) >> HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S) 16479 16480 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M 0xFFFFFFFF 16481 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S 0 16482 16483 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_SET(word, value) \ 16484 do { \ 16485 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF, value); \ 16486 (word) |= (value) << HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S; \ 16487 } while (0) 16488 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(word) \ 16489 (((word) & HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M) >> HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S) 16490 16491 struct htt_t2h_tx_msdu_info { /* 8 words */ 16492 /* words 0 + 1 */ 16493 struct htt_t2h_tx_buffer_addr_info addr_info; 16494 16495 /* word 2 */ 16496 A_UINT32 16497 sw_peer_id : 16, 16498 tid : 4, 16499 transmit_cnt : 7, 16500 valid : 1, 16501 mcast : 1, 16502 rsvd0 : 3; 16503 16504 /* word 3 */ 16505 A_UINT32 16506 release_reason : 4, /* Refer to htt_t2h_tx_msdu_release_reason_e */ 16507 tqm_status_number : 24, 16508 frame_type : 4; /* holds htt_tx_wbm_status_frame_type value */ 16509 16510 /* word 4 */ 16511 A_UINT32 16512 /* ack_frame_rssi: 16513 * If this frame is removed as the result of the 16514 * reception of an ACK or BA, this field indicates 16515 * the RSSI of the received ACK or BA frame. 16516 * When the frame is removed as result of a direct 16517 * remove command from the SW, this field is set 16518 * to 0x0 (which is never a valid value when real 16519 * RSSI is available). 16520 * Units: dB w.r.t noise floor 16521 */ 16522 ack_frame_rssi : 8, 16523 first_msdu : 1, 16524 last_msdu : 1, 16525 msdu_part_of_amsdu : 1, 16526 buffer_timestamp : 19, /* units = TU = 1024 microseconds */ 16527 rsvd1 : 2; 16528 16529 /* words 5 + 6 */ 16530 struct htt_t2h_tx_rate_stats_info tx_rate_stats; 16531 16532 /* word 7 */ 16533 /* rsvd3: 16534 * backup reserved field to add new parameters if [rsvd0, rsvd1, rsvd2] 16535 * is not sufficient 16536 */ 16537 A_UINT32 rsvd3; 16538 16539 /* NOTE: 16540 * To preserve backwards compatibility, 16541 * no new fields can be added in this struct. 16542 */ 16543 }; 16544 16545 /* member definitions of htt_t2h_tx_msdu_info */ 16546 16547 #define HTT_TX_MSDU_INFO_SW_PEER_ID_M 0x0000FFFF 16548 #define HTT_TX_MSDU_INFO_SW_PEER_ID_S 0 16549 16550 #define HTT_TX_MSDU_INFO_SW_PEER_ID_SET(word, value) \ 16551 do { \ 16552 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_SW_PEER_ID, value); \ 16553 (word) |= (value) << HTT_TX_MSDU_INFO_SW_PEER_ID_S; \ 16554 } while (0) 16555 #define HTT_TX_MSDU_INFO_SW_PEER_ID_GET(word) \ 16556 (((word) & HTT_TX_MSDU_INFO_SW_PEER_ID_M) >> HTT_TX_MSDU_INFO_SW_PEER_ID_S) 16557 16558 #define HTT_TX_MSDU_INFO_TID_M 0x000F0000 16559 #define HTT_TX_MSDU_INFO_TID_S 16 16560 16561 #define HTT_TX_MSDU_INFO_TID_SET(word, value) \ 16562 do { \ 16563 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TID, value); \ 16564 (word) |= (value) << HTT_TX_MSDU_INFO_TID_S; \ 16565 } while (0) 16566 #define HTT_TX_MSDU_INFO_TID_GET(word) \ 16567 (((word) & HTT_TX_MSDU_INFO_TID_M) >> HTT_TX_MSDU_INFO_TID_S) 16568 16569 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_M 0x07F00000 16570 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_S 20 16571 16572 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_SET(word, value) \ 16573 do { \ 16574 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TRANSMIT_CNT, value); \ 16575 (word) |= (value) << HTT_TX_MSDU_INFO_TRANSMIT_CNT_S; \ 16576 } while (0) 16577 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(word) \ 16578 (((word) & HTT_TX_MSDU_INFO_TRANSMIT_CNT_M) >> HTT_TX_MSDU_INFO_TRANSMIT_CNT_S) 16579 16580 #define HTT_TX_MSDU_INFO_VALID_M 0x08000000 16581 #define HTT_TX_MSDU_INFO_VALID_S 27 16582 16583 #define HTT_TX_MSDU_INFO_VALID_SET(word, value) \ 16584 do { \ 16585 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_VALID, value); \ 16586 (word) |= (value) << HTT_TX_MSDU_INFO_VALID_S; \ 16587 } while (0) 16588 #define HTT_TX_MSDU_INFO_VALID_GET(word) \ 16589 (((word) & HTT_TX_MSDU_INFO_VALID_M) >> HTT_TX_MSDU_INFO_VALID_S) 16590 16591 #define HTT_TX_MSDU_INFO_MCAST_M 0x10000000 16592 #define HTT_TX_MSDU_INFO_MCAST_S 28 16593 16594 #define HTT_TX_MSDU_INFO_MCAST_SET(word, value) \ 16595 do { \ 16596 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MCAST, value); \ 16597 (word) |= (value) << HTT_TX_MSDU_INFO_MCAST_S; \ 16598 } while (0) 16599 #define HTT_TX_MSDU_INFO_MCAST_GET(word) \ 16600 (((word) & HTT_TX_MSDU_INFO_MCAST_M) >> HTT_TX_MSDU_INFO_MCAST_S) 16601 16602 #define HTT_TX_MSDU_INFO_RELEASE_REASON_M 0x0000000F 16603 #define HTT_TX_MSDU_INFO_RELEASE_REASON_S 0 16604 16605 #define HTT_TX_MSDU_INFO_RELEASE_REASON_SET(word, value) \ 16606 do { \ 16607 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_RELEASE_REASON, value); \ 16608 (word) |= (value) << HTT_TX_MSDU_INFO_RELEASE_REASON_S; \ 16609 } while (0) 16610 #define HTT_TX_MSDU_INFO_RELEASE_REASON_GET(word) \ 16611 (((word) & HTT_TX_MSDU_INFO_RELEASE_REASON_M) >> HTT_TX_MSDU_INFO_RELEASE_REASON_S) 16612 16613 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M 0x0FFFFFF0 16614 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S 4 16615 16616 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_SET(word, value) \ 16617 do { \ 16618 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER, value); \ 16619 (word) |= (value) << HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S; \ 16620 } while (0) 16621 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(word) \ 16622 (((word) & HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M) >> HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S) 16623 16624 #define HTT_TX_MSDU_INFO_FRAME_TYPE_M 0xF0000000 16625 #define HTT_TX_MSDU_INFO_FRAME_TYPE_S 28 16626 16627 #define HTT_TX_MSDU_INFO_FRAME_TYPE_SET(word, value) \ 16628 do { \ 16629 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FRAME_TYPE, value); \ 16630 (word) |= (value) << HTT_TX_MSDU_INFO_FRAME_TYPE_S; \ 16631 } while (0) 16632 #define HTT_TX_MSDU_INFO_FRAME_TYPE_GET(word) \ 16633 (((word) & HTT_TX_MSDU_INFO_FRAME_TYPE_M) >> HTT_TX_MSDU_INFO_FRAME_TYPE_S) 16634 16635 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M 0x000000FF 16636 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S 0 16637 16638 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_SET(word, value) \ 16639 do { \ 16640 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_ACK_FRAME_RSSI, value); \ 16641 (word) |= (value) << HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S; \ 16642 } while (0) 16643 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(word) \ 16644 (((word) & HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M) >> HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S) 16645 16646 #define HTT_TX_MSDU_INFO_FIRST_MSDU_M 0x00000100 16647 #define HTT_TX_MSDU_INFO_FIRST_MSDU_S 8 16648 16649 #define HTT_TX_MSDU_INFO_FIRST_MSDU_SET(word, value) \ 16650 do { \ 16651 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FIRST_MSDU, value); \ 16652 (word) |= (value) << HTT_TX_MSDU_INFO_FIRST_MSDU_S; \ 16653 } while (0) 16654 #define HTT_TX_MSDU_INFO_FIRST_MSDU_GET(word) \ 16655 (((word) & HTT_TX_MSDU_INFO_FIRST_MSDU_M) >> HTT_TX_MSDU_INFO_FIRST_MSDU_S) 16656 16657 #define HTT_TX_MSDU_INFO_LAST_MSDU_M 0x00000200 16658 #define HTT_TX_MSDU_INFO_LAST_MSDU_S 9 16659 16660 #define HTT_TX_MSDU_INFO_LAST_MSDU_SET(word, value) \ 16661 do { \ 16662 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_LAST_MSDU, value); \ 16663 (word) |= (value) << HTT_TX_MSDU_INFO_LAST_MSDU_S; \ 16664 } while (0) 16665 #define HTT_TX_MSDU_INFO_LAST_MSDU_GET(word) \ 16666 (((word) & HTT_TX_MSDU_INFO_LAST_MSDU_M) >> HTT_TX_MSDU_INFO_LAST_MSDU_S) 16667 16668 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M 0x00000400 16669 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S 10 16670 16671 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_SET(word, value) \ 16672 do { \ 16673 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU, value); \ 16674 (word) |= (value) << HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S; \ 16675 } while (0) 16676 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(word) \ 16677 (((word) & HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M) >> HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S) 16678 16679 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M 0x3FFFF800 16680 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S 11 16681 16682 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_SET(word, value) \ 16683 do { \ 16684 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP, value); \ 16685 (word) |= (value) << HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S; \ 16686 } while (0) 16687 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(word) \ 16688 (((word) & HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M) >> HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S) 16689 16690 struct htt_t2h_soft_umac_tx_compl_ind { 16691 A_UINT32 msg_type : 8, /* HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND */ 16692 msdu_cnt : 8, /* min: 0, max: 255 */ 16693 rsvd0 : 16; 16694 /* NOTE: 16695 * To preserve backwards compatibility, 16696 * no new fields can be added in this struct. 16697 */ 16698 /* 16699 * append here: 16700 * struct htt_t2h_tx_msdu_info payload[1(or more)] 16701 * for all the msdu's that are part of this completion. 16702 */ 16703 }; 16704 16705 /* member definitions of htt_t2h_soft_umac_tx_compl_ind */ 16706 16707 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M 0x0000FF00 16708 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S 8 16709 16710 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_SET(word, value) \ 16711 do { \ 16712 HTT_CHECK_SET_VAL(HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT, value); \ 16713 (word) |= (value) << HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S; \ 16714 } while (0) 16715 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_GET(word) \ 16716 (((word) & HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M) >> HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S) 16717 16718 16719 /** 16720 * @brief target -> host rate-control update indication message 16721 * 16722 * DEPRECATED (DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND) 16723 * 16724 * @details 16725 * The following diagram shows the format of the RC Update message 16726 * sent from the target to the host, while processing the tx-completion 16727 * of a transmitted PPDU. 16728 * 16729 * |31 24|23 16|15 8|7 0| 16730 * |-------------------------------------------------------------| 16731 * | peer ID | vdev ID | msg_type | 16732 * |-------------------------------------------------------------| 16733 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 16734 * |-------------------------------------------------------------| 16735 * | reserved | num elems | MAC addr 5 | MAC addr 4 | 16736 * |-------------------------------------------------------------| 16737 * | : | 16738 * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : 16739 * | : | 16740 * |-------------------------------------------------------------| 16741 * | : | 16742 * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : 16743 * | : | 16744 * |-------------------------------------------------------------| 16745 * : : 16746 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16747 * 16748 */ 16749 16750 typedef struct { 16751 A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ 16752 A_UINT32 rate_code_flags; 16753 A_UINT32 flags; /* Encodes information such as excessive 16754 retransmission, aggregate, some info 16755 from .11 frame control, 16756 STBC, LDPC, (SGI and Tx Chain Mask 16757 are encoded in ptx_rc->flags field), 16758 AMPDU truncation (BT/time based etc.), 16759 RTS/CTS attempt */ 16760 16761 A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ 16762 A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ 16763 A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ 16764 A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ 16765 A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */ 16766 A_UINT32 is_probe; /* Valid if probing. Else, 0 */ 16767 } HTT_RC_TX_DONE_PARAMS; 16768 16769 #define HTT_RC_UPDATE_CTXT_SZ (sizeof(HTT_RC_TX_DONE_PARAMS)) /* bytes */ 16770 #define HTT_RC_UPDATE_HDR_SZ (12) /* bytes */ 16771 16772 #define HTT_RC_UPDATE_MAC_ADDR_OFFSET (4) /* bytes */ 16773 #define HTT_RC_UPDATE_MAC_ADDR_LENGTH IEEE80211_ADDR_LEN /* bytes */ 16774 16775 #define HTT_RC_UPDATE_VDEVID_S 8 16776 #define HTT_RC_UPDATE_VDEVID_M 0xff00 16777 #define HTT_RC_UPDATE_PEERID_S 16 16778 #define HTT_RC_UPDATE_PEERID_M 0xffff0000 16779 16780 #define HTT_RC_UPDATE_NUM_ELEMS_S 16 16781 #define HTT_RC_UPDATE_NUM_ELEMS_M 0x00ff0000 16782 16783 #define HTT_RC_UPDATE_VDEVID_SET(_info, _val) \ 16784 do { \ 16785 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_VDEVID, _val); \ 16786 ((_info) |= ((_val) << HTT_RC_UPDATE_VDEVID_S)); \ 16787 } while (0) 16788 16789 #define HTT_RC_UPDATE_VDEVID_GET(_info) \ 16790 (((_info) & HTT_RC_UPDATE_VDEVID_M) >> HTT_RC_UPDATE_VDEVID_S) 16791 16792 #define HTT_RC_UPDATE_PEERID_SET(_info, _val) \ 16793 do { \ 16794 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_PEERID, _val); \ 16795 ((_info) |= ((_val) << HTT_RC_UPDATE_PEERID_S)); \ 16796 } while (0) 16797 16798 #define HTT_RC_UPDATE_PEERID_GET(_info) \ 16799 (((_info) & HTT_RC_UPDATE_PEERID_M) >> HTT_RC_UPDATE_PEERID_S) 16800 16801 #define HTT_RC_UPDATE_NUM_ELEMS_SET(_info, _val) \ 16802 do { \ 16803 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_NUM_ELEMS, _val); \ 16804 ((_info) |= ((_val) << HTT_RC_UPDATE_NUM_ELEMS_S)); \ 16805 } while (0) 16806 16807 #define HTT_RC_UPDATE_NUM_ELEMS_GET(_info) \ 16808 (((_info) & HTT_RC_UPDATE_NUM_ELEMS_M) >> HTT_RC_UPDATE_NUM_ELEMS_S) 16809 16810 /** 16811 * @brief target -> host rx fragment indication message definition 16812 * 16813 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FRAG_IND 16814 * 16815 * @details 16816 * The following field definitions describe the format of the rx fragment 16817 * indication message sent from the target to the host. 16818 * The rx fragment indication message shares the format of the 16819 * rx indication message, but not all fields from the rx indication message 16820 * are relevant to the rx fragment indication message. 16821 * 16822 * 16823 * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| 16824 * |-----------+-------------------+---------------------+-------------| 16825 * | peer ID | |FV| ext TID | msg type | 16826 * |-------------------------------------------------------------------| 16827 * | | flush | flush | 16828 * | | end | start | 16829 * | | seq num | seq num | 16830 * |-------------------------------------------------------------------| 16831 * | reserved | FW rx desc bytes | 16832 * |-------------------------------------------------------------------| 16833 * | | FW MSDU Rx | 16834 * | | desc B0 | 16835 * |-------------------------------------------------------------------| 16836 * Header fields: 16837 * - MSG_TYPE 16838 * Bits 7:0 16839 * Purpose: identifies this as an rx fragment indication message 16840 * Value: 0xa (HTT_T2H_MSG_TYPE_RX_FRAG_IND) 16841 * - EXT_TID 16842 * Bits 12:8 16843 * Purpose: identify the traffic ID of the rx data, including 16844 * special "extended" TID values for multicast, broadcast, and 16845 * non-QoS data frames 16846 * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS 16847 * - FLUSH_VALID (FV) 16848 * Bit 13 16849 * Purpose: indicate whether the flush IE (start/end sequence numbers) 16850 * is valid 16851 * Value: 16852 * 1 -> flush IE is valid and needs to be processed 16853 * 0 -> flush IE is not valid and should be ignored 16854 * - PEER_ID 16855 * Bits 31:16 16856 * Purpose: Identify, by ID, which peer sent the rx data 16857 * Value: ID of the peer who sent the rx data 16858 * - FLUSH_SEQ_NUM_START 16859 * Bits 5:0 16860 * Purpose: Indicate the start of a series of MPDUs to flush 16861 * Not all MPDUs within this series are necessarily valid - the host 16862 * must check each sequence number within this range to see if the 16863 * corresponding MPDU is actually present. 16864 * This field is only valid if the FV bit is set. 16865 * Value: 16866 * The sequence number for the first MPDUs to check to flush. 16867 * The sequence number is masked by 0x3f. 16868 * - FLUSH_SEQ_NUM_END 16869 * Bits 11:6 16870 * Purpose: Indicate the end of a series of MPDUs to flush 16871 * Value: 16872 * The sequence number one larger than the sequence number of the 16873 * last MPDU to check to flush. 16874 * The sequence number is masked by 0x3f. 16875 * Not all MPDUs within this series are necessarily valid - the host 16876 * must check each sequence number within this range to see if the 16877 * corresponding MPDU is actually present. 16878 * This field is only valid if the FV bit is set. 16879 * Rx descriptor fields: 16880 * - FW_RX_DESC_BYTES 16881 * Bits 15:0 16882 * Purpose: Indicate how many bytes in the Rx indication are used for 16883 * FW Rx descriptors 16884 * Value: 1 16885 */ 16886 #define HTT_RX_FRAG_IND_HDR_PREFIX_SIZE32 2 16887 16888 #define HTT_RX_FRAG_IND_FW_DESC_BYTE_OFFSET 12 16889 16890 #define HTT_RX_FRAG_IND_EXT_TID_SET HTT_RX_IND_EXT_TID_SET 16891 #define HTT_RX_FRAG_IND_EXT_TID_GET HTT_RX_IND_EXT_TID_GET 16892 16893 #define HTT_RX_FRAG_IND_PEER_ID_SET HTT_RX_IND_PEER_ID_SET 16894 #define HTT_RX_FRAG_IND_PEER_ID_GET HTT_RX_IND_PEER_ID_GET 16895 16896 #define HTT_RX_FRAG_IND_FLUSH_VALID_SET HTT_RX_IND_FLUSH_VALID_SET 16897 #define HTT_RX_FRAG_IND_FLUSH_VALID_GET HTT_RX_IND_FLUSH_VALID_GET 16898 16899 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_SET \ 16900 HTT_RX_IND_FLUSH_SEQ_NUM_START_SET 16901 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_GET \ 16902 HTT_RX_IND_FLUSH_SEQ_NUM_START_GET 16903 16904 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_SET \ 16905 HTT_RX_IND_FLUSH_SEQ_NUM_END_SET 16906 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_GET \ 16907 HTT_RX_IND_FLUSH_SEQ_NUM_END_GET 16908 16909 #define HTT_RX_FRAG_IND_FW_RX_DESC_BYTES_GET HTT_RX_IND_FW_RX_DESC_BYTES_GET 16910 16911 #define HTT_RX_FRAG_IND_BYTES \ 16912 (4 /* msg hdr */ + \ 16913 4 /* flush spec */ + \ 16914 4 /* (unused) FW rx desc bytes spec */ + \ 16915 4 /* FW rx desc */) 16916 16917 /** 16918 * @brief target -> host test message definition 16919 * 16920 * MSG_TYPE => HTT_T2H_MSG_TYPE_TEST 16921 * 16922 * @details 16923 * The following field definitions describe the format of the test 16924 * message sent from the target to the host. 16925 * The message consists of a 4-octet header, followed by a variable 16926 * number of 32-bit integer values, followed by a variable number 16927 * of 8-bit character values. 16928 * 16929 * |31 16|15 8|7 0| 16930 * |-----------------------------------------------------------| 16931 * | num chars | num ints | msg type | 16932 * |-----------------------------------------------------------| 16933 * | int 0 | 16934 * |-----------------------------------------------------------| 16935 * | int 1 | 16936 * |-----------------------------------------------------------| 16937 * | ... | 16938 * |-----------------------------------------------------------| 16939 * | char 3 | char 2 | char 1 | char 0 | 16940 * |-----------------------------------------------------------| 16941 * | | | ... | char 4 | 16942 * |-----------------------------------------------------------| 16943 * - MSG_TYPE 16944 * Bits 7:0 16945 * Purpose: identifies this as a test message 16946 * Value: HTT_MSG_TYPE_TEST 16947 * - NUM_INTS 16948 * Bits 15:8 16949 * Purpose: indicate how many 32-bit integers follow the message header 16950 * - NUM_CHARS 16951 * Bits 31:16 16952 * Purpose: indicate how many 8-bit characters follow the series of integers 16953 */ 16954 #define HTT_RX_TEST_NUM_INTS_M 0xff00 16955 #define HTT_RX_TEST_NUM_INTS_S 8 16956 #define HTT_RX_TEST_NUM_CHARS_M 0xffff0000 16957 #define HTT_RX_TEST_NUM_CHARS_S 16 16958 16959 #define HTT_RX_TEST_NUM_INTS_SET(word, value) \ 16960 do { \ 16961 HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_INTS, value); \ 16962 (word) |= (value) << HTT_RX_TEST_NUM_INTS_S; \ 16963 } while (0) 16964 #define HTT_RX_TEST_NUM_INTS_GET(word) \ 16965 (((word) & HTT_RX_TEST_NUM_INTS_M) >> HTT_RX_TEST_NUM_INTS_S) 16966 16967 #define HTT_RX_TEST_NUM_CHARS_SET(word, value) \ 16968 do { \ 16969 HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_CHARS, value); \ 16970 (word) |= (value) << HTT_RX_TEST_NUM_CHARS_S; \ 16971 } while (0) 16972 #define HTT_RX_TEST_NUM_CHARS_GET(word) \ 16973 (((word) & HTT_RX_TEST_NUM_CHARS_M) >> HTT_RX_TEST_NUM_CHARS_S) 16974 16975 /** 16976 * @brief target -> host packet log message 16977 * 16978 * MSG_TYPE => HTT_T2H_MSG_TYPE_PKTLOG 16979 * 16980 * @details 16981 * The following field definitions describe the format of the packet log 16982 * message sent from the target to the host. 16983 * The message consists of a 4-octet header,followed by a variable number 16984 * of 32-bit character values. 16985 * 16986 * |31 16|15 12|11 10|9 8|7 0| 16987 * |------------------------------------------------------------------| 16988 * | payload_size | rsvd |pdev_id|mac_id| msg type | 16989 * |------------------------------------------------------------------| 16990 * | payload | 16991 * |------------------------------------------------------------------| 16992 * - MSG_TYPE 16993 * Bits 7:0 16994 * Purpose: identifies this as a pktlog message 16995 * Value: 0x8 (HTT_T2H_MSG_TYPE_PKTLOG) 16996 * - mac_id 16997 * Bits 9:8 16998 * Purpose: identifies which MAC/PHY instance generated this pktlog info 16999 * Value: 0-3 17000 * - pdev_id 17001 * Bits 11:10 17002 * Purpose: pdev_id 17003 * Value: 0-3 17004 * 0 (for rings at SOC level), 17005 * 1/2/3 PDEV -> 0/1/2 17006 * - payload_size 17007 * Bits 31:16 17008 * Purpose: explicitly specify the payload size 17009 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 17010 */ 17011 PREPACK struct htt_pktlog_msg { 17012 A_UINT32 header; 17013 A_UINT32 payload[1/* or more */]; 17014 } POSTPACK; 17015 17016 #define HTT_T2H_PKTLOG_MAC_ID_M 0x00000300 17017 #define HTT_T2H_PKTLOG_MAC_ID_S 8 17018 17019 #define HTT_T2H_PKTLOG_PDEV_ID_M 0x00000C00 17020 #define HTT_T2H_PKTLOG_PDEV_ID_S 10 17021 17022 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_M 0xFFFF0000 17023 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_S 16 17024 17025 #define HTT_T2H_PKTLOG_MAC_ID_SET(word, value) \ 17026 do { \ 17027 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_MAC_ID, value); \ 17028 (word) |= (value) << HTT_T2H_PKTLOG_MAC_ID_S; \ 17029 } while (0) 17030 #define HTT_T2H_PKTLOG_MAC_ID_GET(word) \ 17031 (((word) & HTT_T2H_PKTLOG_MAC_ID_M) >> \ 17032 HTT_T2H_PKTLOG_MAC_ID_S) 17033 17034 #define HTT_T2H_PKTLOG_PDEV_ID_SET(word, value) \ 17035 do { \ 17036 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PDEV_ID, value); \ 17037 (word) |= (value) << HTT_T2H_PKTLOG_PDEV_ID_S; \ 17038 } while (0) 17039 #define HTT_T2H_PKTLOG_PDEV_ID_GET(word) \ 17040 (((word) & HTT_T2H_PKTLOG_PDEV_ID_M) >> \ 17041 HTT_T2H_PKTLOG_PDEV_ID_S) 17042 17043 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_SET(word, value) \ 17044 do { \ 17045 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PAYLOAD_SIZE, value); \ 17046 (word) |= (value) << HTT_T2H_PKTLOG_PAYLOAD_SIZE_S; \ 17047 } while (0) 17048 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_GET(word) \ 17049 (((word) & HTT_T2H_PKTLOG_PAYLOAD_SIZE_M) >> \ 17050 HTT_T2H_PKTLOG_PAYLOAD_SIZE_S) 17051 17052 /* 17053 * Rx reorder statistics 17054 * NB: all the fields must be defined in 4 octets size. 17055 */ 17056 struct rx_reorder_stats { 17057 /* Non QoS MPDUs received */ 17058 A_UINT32 deliver_non_qos; 17059 /* MPDUs received in-order */ 17060 A_UINT32 deliver_in_order; 17061 /* Flush due to reorder timer expired */ 17062 A_UINT32 deliver_flush_timeout; 17063 /* Flush due to move out of window */ 17064 A_UINT32 deliver_flush_oow; 17065 /* Flush due to DELBA */ 17066 A_UINT32 deliver_flush_delba; 17067 /* MPDUs dropped due to FCS error */ 17068 A_UINT32 fcs_error; 17069 /* MPDUs dropped due to monitor mode non-data packet */ 17070 A_UINT32 mgmt_ctrl; 17071 /* Unicast-data MPDUs dropped due to invalid peer */ 17072 A_UINT32 invalid_peer; 17073 /* MPDUs dropped due to duplication (non aggregation) */ 17074 A_UINT32 dup_non_aggr; 17075 /* MPDUs dropped due to processed before */ 17076 A_UINT32 dup_past; 17077 /* MPDUs dropped due to duplicate in reorder queue */ 17078 A_UINT32 dup_in_reorder; 17079 /* Reorder timeout happened */ 17080 A_UINT32 reorder_timeout; 17081 /* invalid bar ssn */ 17082 A_UINT32 invalid_bar_ssn; 17083 /* reorder reset due to bar ssn */ 17084 A_UINT32 ssn_reset; 17085 /* Flush due to delete peer */ 17086 A_UINT32 deliver_flush_delpeer; 17087 /* Flush due to offload*/ 17088 A_UINT32 deliver_flush_offload; 17089 /* Flush due to out of buffer*/ 17090 A_UINT32 deliver_flush_oob; 17091 /* MPDUs dropped due to PN check fail */ 17092 A_UINT32 pn_fail; 17093 /* MPDUs dropped due to unable to allocate memory */ 17094 A_UINT32 store_fail; 17095 /* Number of times the tid pool alloc succeeded */ 17096 A_UINT32 tid_pool_alloc_succ; 17097 /* Number of times the MPDU pool alloc succeeded */ 17098 A_UINT32 mpdu_pool_alloc_succ; 17099 /* Number of times the MSDU pool alloc succeeded */ 17100 A_UINT32 msdu_pool_alloc_succ; 17101 /* Number of times the tid pool alloc failed */ 17102 A_UINT32 tid_pool_alloc_fail; 17103 /* Number of times the MPDU pool alloc failed */ 17104 A_UINT32 mpdu_pool_alloc_fail; 17105 /* Number of times the MSDU pool alloc failed */ 17106 A_UINT32 msdu_pool_alloc_fail; 17107 /* Number of times the tid pool freed */ 17108 A_UINT32 tid_pool_free; 17109 /* Number of times the MPDU pool freed */ 17110 A_UINT32 mpdu_pool_free; 17111 /* Number of times the MSDU pool freed */ 17112 A_UINT32 msdu_pool_free; 17113 /* number of MSDUs undelivered to HTT and queued to Data Rx MSDU free list*/ 17114 A_UINT32 msdu_queued; 17115 /* Number of MSDUs released from Data Rx MSDU list to MAC ring */ 17116 A_UINT32 msdu_recycled; 17117 /* Number of MPDUs with invalid peer but A2 found in AST */ 17118 A_UINT32 invalid_peer_a2_in_ast; 17119 /* Number of MPDUs with invalid peer but A3 found in AST */ 17120 A_UINT32 invalid_peer_a3_in_ast; 17121 /* Number of MPDUs with invalid peer, Broadcast or Multicast frame */ 17122 A_UINT32 invalid_peer_bmc_mpdus; 17123 /* Number of MSDUs with err attention word */ 17124 A_UINT32 rxdesc_err_att; 17125 /* Number of MSDUs with flag of peer_idx_invalid */ 17126 A_UINT32 rxdesc_err_peer_idx_inv; 17127 /* Number of MSDUs with flag of peer_idx_timeout */ 17128 A_UINT32 rxdesc_err_peer_idx_to; 17129 /* Number of MSDUs with flag of overflow */ 17130 A_UINT32 rxdesc_err_ov; 17131 /* Number of MSDUs with flag of msdu_length_err */ 17132 A_UINT32 rxdesc_err_msdu_len; 17133 /* Number of MSDUs with flag of mpdu_length_err */ 17134 A_UINT32 rxdesc_err_mpdu_len; 17135 /* Number of MSDUs with flag of tkip_mic_err */ 17136 A_UINT32 rxdesc_err_tkip_mic; 17137 /* Number of MSDUs with flag of decrypt_err */ 17138 A_UINT32 rxdesc_err_decrypt; 17139 /* Number of MSDUs with flag of fcs_err */ 17140 A_UINT32 rxdesc_err_fcs; 17141 /* Number of Unicast (bc_mc bit is not set in attention word) 17142 * frames with invalid peer handler 17143 */ 17144 A_UINT32 rxdesc_uc_msdus_inv_peer; 17145 /* Number of unicast frame directly (direct bit is set in attention word) 17146 * to DUT with invalid peer handler 17147 */ 17148 A_UINT32 rxdesc_direct_msdus_inv_peer; 17149 /* Number of Broadcast/Multicast (bc_mc bit set in attention word) 17150 * frames with invalid peer handler 17151 */ 17152 A_UINT32 rxdesc_bmc_msdus_inv_peer; 17153 /* Number of MSDUs dropped due to no first MSDU flag */ 17154 A_UINT32 rxdesc_no_1st_msdu; 17155 /* Number of MSDUs dropped due to ring overflow */ 17156 A_UINT32 msdu_drop_ring_ov; 17157 /* Number of MSDUs dropped due to FC mismatch */ 17158 A_UINT32 msdu_drop_fc_mismatch; 17159 /* Number of MSDUs dropped due to mgt frame in Remote ring */ 17160 A_UINT32 msdu_drop_mgmt_remote_ring; 17161 /* Number of MSDUs dropped due to errors not reported in attention word */ 17162 A_UINT32 msdu_drop_misc; 17163 /* Number of MSDUs go to offload before reorder */ 17164 A_UINT32 offload_msdu_wal; 17165 /* Number of data frame dropped by offload after reorder */ 17166 A_UINT32 offload_msdu_reorder; 17167 /* Number of MPDUs with sequence number in the past and within the BA window */ 17168 A_UINT32 dup_past_within_window; 17169 /* Number of MPDUs with sequence number in the past and outside the BA window */ 17170 A_UINT32 dup_past_outside_window; 17171 /* Number of MSDUs with decrypt/MIC error */ 17172 A_UINT32 rxdesc_err_decrypt_mic; 17173 /* Number of data MSDUs received on both local and remote rings */ 17174 A_UINT32 data_msdus_on_both_rings; 17175 /* MPDUs never filled */ 17176 A_UINT32 holes_not_filled; 17177 }; 17178 17179 17180 /* 17181 * Rx Remote buffer statistics 17182 * NB: all the fields must be defined in 4 octets size. 17183 */ 17184 struct rx_remote_buffer_mgmt_stats { 17185 /* Total number of MSDUs reaped for Rx processing */ 17186 A_UINT32 remote_reaped; 17187 /* MSDUs recycled within firmware */ 17188 A_UINT32 remote_recycled; 17189 /* MSDUs stored by Data Rx */ 17190 A_UINT32 data_rx_msdus_stored; 17191 /* Number of HTT indications from WAL Rx MSDU */ 17192 A_UINT32 wal_rx_ind; 17193 /* Number of unconsumed HTT indications from WAL Rx MSDU */ 17194 A_UINT32 wal_rx_ind_unconsumed; 17195 /* Number of HTT indications from Data Rx MSDU */ 17196 A_UINT32 data_rx_ind; 17197 /* Number of unconsumed HTT indications from Data Rx MSDU */ 17198 A_UINT32 data_rx_ind_unconsumed; 17199 /* Number of HTT indications from ATHBUF */ 17200 A_UINT32 athbuf_rx_ind; 17201 /* Number of remote buffers requested for refill */ 17202 A_UINT32 refill_buf_req; 17203 /* Number of remote buffers filled by the host */ 17204 A_UINT32 refill_buf_rsp; 17205 /* Number of times MAC hw_index = f/w write_index */ 17206 A_INT32 mac_no_bufs; 17207 /* Number of times f/w write_index = f/w read_index for MAC Rx ring */ 17208 A_INT32 fw_indices_equal; 17209 /* Number of times f/w finds no buffers to post */ 17210 A_INT32 host_no_bufs; 17211 }; 17212 17213 /* 17214 * TXBF MU/SU packets and NDPA statistics 17215 * NB: all the fields must be defined in 4 octets size. 17216 */ 17217 struct rx_txbf_musu_ndpa_pkts_stats { 17218 A_UINT32 number_mu_pkts; /* number of TXBF MU packets received */ 17219 A_UINT32 number_su_pkts; /* number of TXBF SU packets received */ 17220 A_UINT32 txbf_directed_ndpa_count; /* number of TXBF directed NDPA */ 17221 A_UINT32 txbf_ndpa_retry_count; /* number of TXBF retried NDPA */ 17222 A_UINT32 txbf_total_ndpa_count; /* total number of TXBF NDPA */ 17223 17224 A_UINT32 reserved[3]; /* must be set to 0x0 */ 17225 }; 17226 17227 17228 /* 17229 * htt_dbg_stats_status - 17230 * present - The requested stats have been delivered in full. 17231 * This indicates that either the stats information was contained 17232 * in its entirety within this message, or else this message 17233 * completes the delivery of the requested stats info that was 17234 * partially delivered through earlier STATS_CONF messages. 17235 * partial - The requested stats have been delivered in part. 17236 * One or more subsequent STATS_CONF messages with the same 17237 * cookie value will be sent to deliver the remainder of the 17238 * information. 17239 * error - The requested stats could not be delivered, for example due 17240 * to a shortage of memory to construct a message holding the 17241 * requested stats. 17242 * invalid - The requested stat type is either not recognized, or the 17243 * target is configured to not gather the stats type in question. 17244 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17245 * series_done - This special value indicates that no further stats info 17246 * elements are present within a series of stats info elems 17247 * (within a stats upload confirmation message). 17248 */ 17249 enum htt_dbg_stats_status { 17250 HTT_DBG_STATS_STATUS_PRESENT = 0, 17251 HTT_DBG_STATS_STATUS_PARTIAL = 1, 17252 HTT_DBG_STATS_STATUS_ERROR = 2, 17253 HTT_DBG_STATS_STATUS_INVALID = 3, 17254 17255 17256 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 17257 }; 17258 17259 /** 17260 * @brief target -> host statistics upload 17261 * 17262 * MSG_TYPE => HTT_T2H_MSG_TYPE_STATS_CONF 17263 * 17264 * @details 17265 * The following field definitions describe the format of the HTT target 17266 * to host stats upload confirmation message. 17267 * The message contains a cookie echoed from the HTT host->target stats 17268 * upload request, which identifies which request the confirmation is 17269 * for, and a series of tag-length-value stats information elements. 17270 * The tag-length header for each stats info element also includes a 17271 * status field, to indicate whether the request for the stat type in 17272 * question was fully met, partially met, unable to be met, or invalid 17273 * (if the stat type in question is disabled in the target). 17274 * A special value of all 1's in this status field is used to indicate 17275 * the end of the series of stats info elements. 17276 * 17277 * 17278 * |31 16|15 8|7 5|4 0| 17279 * |------------------------------------------------------------| 17280 * | reserved | msg type | 17281 * |------------------------------------------------------------| 17282 * | cookie LSBs | 17283 * |------------------------------------------------------------| 17284 * | cookie MSBs | 17285 * |------------------------------------------------------------| 17286 * | stats entry length | reserved | S |stat type| 17287 * |------------------------------------------------------------| 17288 * | | 17289 * | type-specific stats info | 17290 * | | 17291 * |------------------------------------------------------------| 17292 * | stats entry length | reserved | S |stat type| 17293 * |------------------------------------------------------------| 17294 * | | 17295 * | type-specific stats info | 17296 * | | 17297 * |------------------------------------------------------------| 17298 * | n/a | reserved | 111 | n/a | 17299 * |------------------------------------------------------------| 17300 * Header fields: 17301 * - MSG_TYPE 17302 * Bits 7:0 17303 * Purpose: identifies this is a statistics upload confirmation message 17304 * Value: 0x9 (HTT_T2H_MSG_TYPE_STATS_CONF) 17305 * - COOKIE_LSBS 17306 * Bits 31:0 17307 * Purpose: Provide a mechanism to match a target->host stats confirmation 17308 * message with its preceding host->target stats request message. 17309 * Value: LSBs of the opaque cookie specified by the host-side requestor 17310 * - COOKIE_MSBS 17311 * Bits 31:0 17312 * Purpose: Provide a mechanism to match a target->host stats confirmation 17313 * message with its preceding host->target stats request message. 17314 * Value: MSBs of the opaque cookie specified by the host-side requestor 17315 * 17316 * Stats Information Element tag-length header fields: 17317 * - STAT_TYPE 17318 * Bits 4:0 17319 * Purpose: identifies the type of statistics info held in the 17320 * following information element 17321 * Value: htt_dbg_stats_type 17322 * - STATUS 17323 * Bits 7:5 17324 * Purpose: indicate whether the requested stats are present 17325 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 17326 * the completion of the stats entry series 17327 * - LENGTH 17328 * Bits 31:16 17329 * Purpose: indicate the stats information size 17330 * Value: This field specifies the number of bytes of stats information 17331 * that follows the element tag-length header. 17332 * It is expected but not required that this length is a multiple of 17333 * 4 bytes. Even if the length is not an integer multiple of 4, the 17334 * subsequent stats entry header will begin on a 4-byte aligned 17335 * boundary. 17336 */ 17337 #define HTT_T2H_STATS_COOKIE_SIZE 8 17338 17339 #define HTT_T2H_STATS_CONF_TAIL_SIZE 4 17340 17341 #define HTT_T2H_STATS_CONF_HDR_SIZE 4 17342 17343 #define HTT_T2H_STATS_CONF_TLV_HDR_SIZE 4 17344 17345 #define HTT_T2H_STATS_CONF_TLV_TYPE_M 0x0000001f 17346 #define HTT_T2H_STATS_CONF_TLV_TYPE_S 0 17347 #define HTT_T2H_STATS_CONF_TLV_STATUS_M 0x000000e0 17348 #define HTT_T2H_STATS_CONF_TLV_STATUS_S 5 17349 #define HTT_T2H_STATS_CONF_TLV_LENGTH_M 0xffff0000 17350 #define HTT_T2H_STATS_CONF_TLV_LENGTH_S 16 17351 17352 #define HTT_T2H_STATS_CONF_TLV_TYPE_SET(word, value) \ 17353 do { \ 17354 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_TYPE, value); \ 17355 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_TYPE_S; \ 17356 } while (0) 17357 #define HTT_T2H_STATS_CONF_TLV_TYPE_GET(word) \ 17358 (((word) & HTT_T2H_STATS_CONF_TLV_TYPE_M) >> \ 17359 HTT_T2H_STATS_CONF_TLV_TYPE_S) 17360 17361 #define HTT_T2H_STATS_CONF_TLV_STATUS_SET(word, value) \ 17362 do { \ 17363 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_STATUS, value); \ 17364 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_STATUS_S; \ 17365 } while (0) 17366 #define HTT_T2H_STATS_CONF_TLV_STATUS_GET(word) \ 17367 (((word) & HTT_T2H_STATS_CONF_TLV_STATUS_M) >> \ 17368 HTT_T2H_STATS_CONF_TLV_STATUS_S) 17369 17370 #define HTT_T2H_STATS_CONF_TLV_LENGTH_SET(word, value) \ 17371 do { \ 17372 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_LENGTH, value); \ 17373 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_LENGTH_S; \ 17374 } while (0) 17375 #define HTT_T2H_STATS_CONF_TLV_LENGTH_GET(word) \ 17376 (((word) & HTT_T2H_STATS_CONF_TLV_LENGTH_M) >> \ 17377 HTT_T2H_STATS_CONF_TLV_LENGTH_S) 17378 17379 #define HL_HTT_FW_RX_DESC_RSVD_SIZE 18 17380 #define HTT_MAX_AGGR 64 17381 #define HTT_HL_MAX_AGGR 18 17382 17383 /** 17384 * @brief host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 17385 * 17386 * MSG_TYPE => HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG 17387 * 17388 * @details 17389 * The following field definitions describe the format of the HTT host 17390 * to target frag_desc/msdu_ext bank configuration message. 17391 * The message contains the based address and the min and max id of the 17392 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 17393 * MSDU_EXT/FRAG_DESC. 17394 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 17395 * In peregrine the firmware will use fragment_desc_ptr but in WIFI2.0 17396 * the hardware does the mapping/translation. 17397 * 17398 * Total banks that can be configured is configured to 16. 17399 * 17400 * This should be called before any TX has be initiated by the HTT 17401 * 17402 * |31 16|15 8|7 5|4 0| 17403 * |------------------------------------------------------------| 17404 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 17405 * |------------------------------------------------------------| 17406 * | BANK0_BASE_ADDRESS (bits 31:0) | 17407 #if HTT_PADDR64 17408 * | BANK0_BASE_ADDRESS (bits 63:32) | 17409 #endif 17410 * |------------------------------------------------------------| 17411 * | ... | 17412 * |------------------------------------------------------------| 17413 * | BANK15_BASE_ADDRESS (bits 31:0) | 17414 #if HTT_PADDR64 17415 * | BANK15_BASE_ADDRESS (bits 63:32) | 17416 #endif 17417 * |------------------------------------------------------------| 17418 * | BANK0_MAX_ID | BANK0_MIN_ID | 17419 * |------------------------------------------------------------| 17420 * | ... | 17421 * |------------------------------------------------------------| 17422 * | BANK15_MAX_ID | BANK15_MIN_ID | 17423 * |------------------------------------------------------------| 17424 * Header fields: 17425 * - MSG_TYPE 17426 * Bits 7:0 17427 * Value: 0x6 (HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG) 17428 * for systems with 64-bit format for bus addresses: 17429 * - BANKx_BASE_ADDRESS_LO 17430 * Bits 31:0 17431 * Purpose: Provide a mechanism to specify the base address of the 17432 * MSDU_EXT bank physical/bus address. 17433 * Value: lower 4 bytes of MSDU_EXT bank physical / bus address 17434 * - BANKx_BASE_ADDRESS_HI 17435 * Bits 31:0 17436 * Purpose: Provide a mechanism to specify the base address of the 17437 * MSDU_EXT bank physical/bus address. 17438 * Value: higher 4 bytes of MSDU_EXT bank physical / bus address 17439 * for systems with 32-bit format for bus addresses: 17440 * - BANKx_BASE_ADDRESS 17441 * Bits 31:0 17442 * Purpose: Provide a mechanism to specify the base address of the 17443 * MSDU_EXT bank physical/bus address. 17444 * Value: MSDU_EXT bank physical / bus address 17445 * - BANKx_MIN_ID 17446 * Bits 15:0 17447 * Purpose: Provide a mechanism to specify the min index that needs to 17448 * mapped. 17449 * - BANKx_MAX_ID 17450 * Bits 31:16 17451 * Purpose: Provide a mechanism to specify the max index that needs to 17452 * mapped. 17453 * 17454 */ 17455 17456 /** @todo Compress the fields to fit MAX HTT Message size, until then configure to a 17457 * safe value. 17458 * @note MAX supported banks is 16. 17459 */ 17460 #define HTT_TX_MSDU_EXT_BANK_MAX 4 17461 17462 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_M 0x300 17463 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_S 8 17464 17465 #define HTT_H2T_FRAG_DESC_BANK_SWAP_M 0x400 17466 #define HTT_H2T_FRAG_DESC_BANK_SWAP_S 10 17467 17468 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M 0xff0000 17469 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S 16 17470 17471 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M 0xff000000 17472 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S 24 17473 17474 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M 0xffff 17475 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S 0 17476 17477 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M 0xffff0000 17478 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S 16 17479 17480 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_SET(word, value) \ 17481 do { \ 17482 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_PDEVID, value); \ 17483 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_PDEVID_S); \ 17484 } while (0) 17485 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_GET(word) \ 17486 (((word) & HTT_H2T_FRAG_DESC_BANK_PDEVID_M) >> HTT_H2T_FRAG_DESC_BANK_PDEVID_S) 17487 17488 #define HTT_H2T_FRAG_DESC_BANK_SWAP_SET(word, value) \ 17489 do { \ 17490 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_SWAP, value); \ 17491 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_SWAP_S); \ 17492 } while (0) 17493 #define HTT_H2T_FRAG_DESC_BANK_SWAP_GET(word) \ 17494 (((word) & HTT_H2T_FRAG_DESC_BANK_SWAP_M) >> HTT_H2T_FRAG_DESC_BANK_SWAP_S) 17495 17496 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_SET(word, value) \ 17497 do { \ 17498 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_NUM_BANKS, value); \ 17499 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S); \ 17500 } while (0) 17501 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_GET(word) \ 17502 (((word) & HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M) >> HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S) 17503 17504 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_SET(word, value) \ 17505 do { \ 17506 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_DESC_SIZE, value); \ 17507 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S); \ 17508 } while (0) 17509 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_GET(word) \ 17510 (((word) & HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M) >> HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S) 17511 17512 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_SET(word, value) \ 17513 do { \ 17514 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MIN_IDX, value); \ 17515 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S); \ 17516 } while (0) 17517 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_GET(word) \ 17518 (((word) & HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S) 17519 17520 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_SET(word, value) \ 17521 do { \ 17522 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MAX_IDX, value); \ 17523 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S); \ 17524 } while (0) 17525 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_GET(word) \ 17526 (((word) & HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S) 17527 17528 17529 /* 17530 * TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T: 17531 * This macro defines a htt_tx_frag_descXXX_bank_cfg_t in which any physical 17532 * addresses are stored in a XXX-bit field. 17533 * This macro is used to define both htt_tx_frag_desc32_bank_cfg_t and 17534 * htt_tx_frag_desc64_bank_cfg_t structs. 17535 */ 17536 #define TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T( \ 17537 _paddr_bits_, \ 17538 _paddr__bank_base_address_) \ 17539 PREPACK struct htt_tx_frag_desc ## _paddr_bits_ ## _bank_cfg_t { \ 17540 /** word 0 \ 17541 * msg_type: 8, \ 17542 * pdev_id: 2, \ 17543 * swap: 1, \ 17544 * reserved0: 5, \ 17545 * num_banks: 8, \ 17546 * desc_size: 8; \ 17547 */ \ 17548 A_UINT32 word0; \ 17549 /* \ 17550 * If bank_base_address is 64 bits, the upper / lower halves are stored \ 17551 * in little-endian order (bytes 0-3 in the first A_UINT32, bytes 4-7 in \ 17552 * the second A_UINT32). \ 17553 */ \ 17554 _paddr__bank_base_address_[HTT_TX_MSDU_EXT_BANK_MAX]; \ 17555 A_UINT32 bank_info[HTT_TX_MSDU_EXT_BANK_MAX]; \ 17556 } POSTPACK 17557 /* define htt_tx_frag_desc32_bank_cfg_t */ 17558 TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(32, HTT_VAR_PADDR32(bank_base_address)); 17559 /* define htt_tx_frag_desc64_bank_cfg_t */ 17560 TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); 17561 /* 17562 * Make htt_tx_frag_desc_bank_cfg_t be an alias for either 17563 * htt_tx_frag_desc32_bank_cfg_t or htt_tx_frag_desc64_bank_cfg_t 17564 */ 17565 #if HTT_PADDR64 17566 #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc64_bank_cfg_t 17567 #else 17568 #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc32_bank_cfg_t 17569 #endif 17570 17571 /** 17572 * @brief target -> host HTT TX Credit total count update message definition 17573 * 17574 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND 17575 * 17576 *|31 16|15|14 9| 8 |7 0 | 17577 *|---------------------+--+----------+-------+----------| 17578 *|cur htt credit delta | Q| reserved | sign | msg type | 17579 *|------------------------------------------------------| 17580 * 17581 * Header fields: 17582 * - MSG_TYPE 17583 * Bits 7:0 17584 * Purpose: identifies this as a htt tx credit delta update message 17585 * Value: 0xf (HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND) 17586 * - SIGN 17587 * Bits 8 17588 * identifies whether credit delta is positive or negative 17589 * Value: 17590 * - 0x0: credit delta is positive, rebalance in some buffers 17591 * - 0x1: credit delta is negative, rebalance out some buffers 17592 * - reserved 17593 * Bits 14:9 17594 * Value: 0x0 17595 * - TXQ_GRP 17596 * Bit 15 17597 * Purpose: indicates whether any tx queue group information elements 17598 * are appended to the tx credit update message 17599 * Value: 0 -> no tx queue group information element is present 17600 * 1 -> a tx queue group information element immediately follows 17601 * - DELTA_COUNT 17602 * Bits 31:16 17603 * Purpose: Specify current htt credit delta absolute count 17604 */ 17605 17606 #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100 17607 #define HTT_TX_CREDIT_SIGN_BIT_S 8 17608 #define HTT_TX_CREDIT_TXQ_GRP_M 0x00008000 17609 #define HTT_TX_CREDIT_TXQ_GRP_S 15 17610 #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000 17611 #define HTT_TX_CREDIT_DELTA_ABS_S 16 17612 17613 17614 #define HTT_TX_CREDIT_SIGN_BIT_SET(word, value) \ 17615 do { \ 17616 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_SIGN_BIT, value); \ 17617 (word) |= (value) << HTT_TX_CREDIT_SIGN_BIT_S; \ 17618 } while (0) 17619 17620 #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ 17621 (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) 17622 17623 #define HTT_TX_CREDIT_TXQ_GRP_SET(word, value) \ 17624 do { \ 17625 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_TXQ_GRP, value); \ 17626 (word) |= (value) << HTT_TX_CREDIT_TXQ_GRP_S; \ 17627 } while (0) 17628 17629 #define HTT_TX_CREDIT_TXQ_GRP_GET(word) \ 17630 (((word) & HTT_TX_CREDIT_TXQ_GRP_M) >> HTT_TX_CREDIT_TXQ_GRP_S) 17631 17632 #define HTT_TX_CREDIT_DELTA_ABS_SET(word, value) \ 17633 do { \ 17634 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_DELTA_ABS, value); \ 17635 (word) |= (value) << HTT_TX_CREDIT_DELTA_ABS_S; \ 17636 } while (0) 17637 17638 #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ 17639 (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) 17640 17641 17642 #define HTT_TX_CREDIT_MSG_BYTES 4 17643 17644 #define HTT_TX_CREDIT_SIGN_BIT_POSITIVE 0x0 17645 #define HTT_TX_CREDIT_SIGN_BIT_NEGATIVE 0x1 17646 17647 17648 /** 17649 * @brief HTT WDI_IPA Operation Response Message 17650 * 17651 * MSG_TYPE => HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE 17652 * 17653 * @details 17654 * HTT WDI_IPA Operation Response message is sent by target 17655 * to host confirming suspend or resume operation. 17656 * |31 24|23 16|15 8|7 0| 17657 * |----------------+----------------+----------------+----------------| 17658 * | op_code | Rsvd | msg_type | 17659 * |-------------------------------------------------------------------| 17660 * | Rsvd | Response len | 17661 * |-------------------------------------------------------------------| 17662 * | | 17663 * | Response-type specific info | 17664 * | | 17665 * | | 17666 * |-------------------------------------------------------------------| 17667 * Header fields: 17668 * - MSG_TYPE 17669 * Bits 7:0 17670 * Purpose: Identifies this as WDI_IPA Operation Response message 17671 * value: = 0x14 (HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE) 17672 * - OP_CODE 17673 * Bits 31:16 17674 * Purpose: Identifies the operation target is responding to (e.g. TX suspend) 17675 * value: = enum htt_wdi_ipa_op_code 17676 * - RSP_LEN 17677 * Bits 16:0 17678 * Purpose: length for the response-type specific info 17679 * value: = length in bytes for response-type specific info 17680 * For example, if OP_CODE == HTT_WDI_IPA_OPCODE_DBG_STATS, the 17681 * length value will be sizeof(struct wlan_wdi_ipa_dbg_stats_t). 17682 */ 17683 17684 PREPACK struct htt_wdi_ipa_op_response_t 17685 { 17686 /* DWORD 0: flags and meta-data */ 17687 A_UINT32 17688 msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ 17689 reserved1: 8, 17690 op_code: 16; 17691 A_UINT32 17692 rsp_len: 16, 17693 reserved2: 16; 17694 } POSTPACK; 17695 17696 #define HTT_WDI_IPA_OP_RESPONSE_SZ 8 /* bytes */ 17697 17698 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M 0xffff0000 17699 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S 16 17700 17701 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M 0x0000ffff 17702 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S 0 17703 17704 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_GET(_var) \ 17705 (((_var) & HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M) >> HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S) 17706 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_SET(_var, _val) \ 17707 do { \ 17708 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_OP_CODE, _val); \ 17709 ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)); \ 17710 } while (0) 17711 17712 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_GET(_var) \ 17713 (((_var) & HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M) >> HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S) 17714 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_SET(_var, _val) \ 17715 do { \ 17716 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_RSP_LEN, _val); \ 17717 ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)); \ 17718 } while (0) 17719 17720 17721 enum htt_phy_mode { 17722 htt_phy_mode_11a = 0, 17723 htt_phy_mode_11g = 1, 17724 htt_phy_mode_11b = 2, 17725 htt_phy_mode_11g_only = 3, 17726 htt_phy_mode_11na_ht20 = 4, 17727 htt_phy_mode_11ng_ht20 = 5, 17728 htt_phy_mode_11na_ht40 = 6, 17729 htt_phy_mode_11ng_ht40 = 7, 17730 htt_phy_mode_11ac_vht20 = 8, 17731 htt_phy_mode_11ac_vht40 = 9, 17732 htt_phy_mode_11ac_vht80 = 10, 17733 htt_phy_mode_11ac_vht20_2g = 11, 17734 htt_phy_mode_11ac_vht40_2g = 12, 17735 htt_phy_mode_11ac_vht80_2g = 13, 17736 htt_phy_mode_11ac_vht80_80 = 14, /* 80+80 */ 17737 htt_phy_mode_11ac_vht160 = 15, 17738 17739 htt_phy_mode_max, 17740 }; 17741 17742 /** 17743 * @brief target -> host HTT channel change indication 17744 * 17745 * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CHANGE 17746 * 17747 * @details 17748 * Specify when a channel change occurs. 17749 * This allows the host to precisely determine which rx frames arrived 17750 * on the old channel and which rx frames arrived on the new channel. 17751 * 17752 *|31 |7 0 | 17753 *|-------------------------------------------+----------| 17754 *| reserved | msg type | 17755 *|------------------------------------------------------| 17756 *| primary_chan_center_freq_mhz | 17757 *|------------------------------------------------------| 17758 *| contiguous_chan1_center_freq_mhz | 17759 *|------------------------------------------------------| 17760 *| contiguous_chan2_center_freq_mhz | 17761 *|------------------------------------------------------| 17762 *| phy_mode | 17763 *|------------------------------------------------------| 17764 * 17765 * Header fields: 17766 * - MSG_TYPE 17767 * Bits 7:0 17768 * Purpose: identifies this as a htt channel change indication message 17769 * Value: 0x15 (HTT_T2H_MSG_TYPE_CHAN_CHANGE) 17770 * - PRIMARY_CHAN_CENTER_FREQ_MHZ 17771 * Bits 31:0 17772 * Purpose: identify the (center of the) new 20 MHz primary channel 17773 * Value: center frequency of the 20 MHz primary channel, in MHz units 17774 * - CONTIG_CHAN1_CENTER_FREQ_MHZ 17775 * Bits 31:0 17776 * Purpose: identify the (center of the) contiguous frequency range 17777 * comprising the new channel. 17778 * For example, if the new channel is a 80 MHz channel extending 17779 * 60 MHz beyond the primary channel, this field would be 30 larger 17780 * than the primary channel center frequency field. 17781 * Value: center frequency of the contiguous frequency range comprising 17782 * the full channel in MHz units 17783 * (80+80 channels also use the CONTIG_CHAN2 field) 17784 * - CONTIG_CHAN2_CENTER_FREQ_MHZ 17785 * Bits 31:0 17786 * Purpose: Identify the (center of the) 80 MHz extension frequency range 17787 * within a VHT 80+80 channel. 17788 * This field is only relevant for VHT 80+80 channels. 17789 * Value: center frequency of the 80 MHz extension channel in a VHT 80+80 17790 * channel (arbitrary value for cases besides VHT 80+80) 17791 * - PHY_MODE 17792 * Bits 31:0 17793 * Purpose: specify the PHY channel's type (legacy vs. HT vs. VHT), width, 17794 * and band 17795 * Value: htt_phy_mode enum value 17796 */ 17797 17798 PREPACK struct htt_chan_change_t 17799 { 17800 /* DWORD 0: flags and meta-data */ 17801 A_UINT32 17802 msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ 17803 reserved1: 24; 17804 A_UINT32 primary_chan_center_freq_mhz; 17805 A_UINT32 contig_chan1_center_freq_mhz; 17806 A_UINT32 contig_chan2_center_freq_mhz; 17807 A_UINT32 phy_mode; 17808 } POSTPACK; 17809 /* 17810 * Due to historical / backwards-compatibility reasons, maintain the 17811 * below htt_chan_change_msg struct definition, which needs to be 17812 * consistent with the above htt_chan_change_t struct definition 17813 * (aside from the htt_chan_change_t definition including the msg_type 17814 * dword within the message, and the htt_chan_change_msg only containing 17815 * the payload of the message that follows the msg_type dword). 17816 */ 17817 PREPACK struct htt_chan_change_msg { 17818 A_UINT32 chan_mhz; /* frequency in mhz */ 17819 A_UINT32 band_center_freq1; /* Center frequency 1 in MHz */ 17820 A_UINT32 band_center_freq2; /* Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/ 17821 A_UINT32 chan_mode; /* WLAN_PHY_MODE of the channel defined in wlan_defs.h */ 17822 } POSTPACK; 17823 17824 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M 0xffffffff 17825 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S 0 17826 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M 0xffffffff 17827 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S 0 17828 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M 0xffffffff 17829 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S 0 17830 #define HTT_CHAN_CHANGE_PHY_MODE_M 0xffffffff 17831 #define HTT_CHAN_CHANGE_PHY_MODE_S 0 17832 17833 17834 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_SET(word, value) \ 17835 do { \ 17836 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ, value);\ 17837 (word) |= (value) << HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S; \ 17838 } while (0) 17839 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_GET(word) \ 17840 (((word) & HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M) \ 17841 >> HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S) 17842 17843 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_SET(word, value) \ 17844 do { \ 17845 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ, value);\ 17846 (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S; \ 17847 } while (0) 17848 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_GET(word) \ 17849 (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M) \ 17850 >> HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S) 17851 17852 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_SET(word, value) \ 17853 do { \ 17854 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ, value);\ 17855 (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S; \ 17856 } while (0) 17857 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_GET(word) \ 17858 (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M) \ 17859 >> HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S) 17860 17861 #define HTT_CHAN_CHANGE_PHY_MODE_SET(word, value) \ 17862 do { \ 17863 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PHY_MODE, value);\ 17864 (word) |= (value) << HTT_CHAN_CHANGE_PHY_MODE_S; \ 17865 } while (0) 17866 #define HTT_CHAN_CHANGE_PHY_MODE_GET(word) \ 17867 (((word) & HTT_CHAN_CHANGE_PHY_MODE_M) \ 17868 >> HTT_CHAN_CHANGE_PHY_MODE_S) 17869 17870 #define HTT_CHAN_CHANGE_BYTES sizeof(struct htt_chan_change_t) 17871 17872 17873 /** 17874 * @brief rx offload packet error message 17875 * 17876 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR 17877 * 17878 * @details 17879 * HTT_RX_OFLD_PKT_ERR message is sent by target to host to indicate err 17880 * of target payload like mic err. 17881 * 17882 * |31 24|23 16|15 8|7 0| 17883 * |----------------+----------------+----------------+----------------| 17884 * | tid | vdev_id | msg_sub_type | msg_type | 17885 * |-------------------------------------------------------------------| 17886 * : (sub-type dependent content) : 17887 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: 17888 * Header fields: 17889 * - msg_type 17890 * Bits 7:0 17891 * Purpose: Identifies this as HTT_RX_OFLD_PKT_ERR message 17892 * value: 0x16 (HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR) 17893 * - msg_sub_type 17894 * Bits 15:8 17895 * Purpose: Identifies which type of rx error is reported by this message 17896 * value: htt_rx_ofld_pkt_err_type 17897 * - vdev_id 17898 * Bits 23:16 17899 * Purpose: Identifies which vdev received the erroneous rx frame 17900 * value: 17901 * - tid 17902 * Bits 31:24 17903 * Purpose: Identifies the traffic type of the rx frame 17904 * value: 17905 * 17906 * - The payload fields used if the sub-type == MIC error are shown below. 17907 * Note - MIC err is per MSDU, while PN is per MPDU. 17908 * The FW will discard the whole MPDU if any MSDU within the MPDU is marked 17909 * with MIC err in A-MSDU case, so FW will send only one HTT message 17910 * with the PN of this MPDU attached to indicate MIC err for one MPDU 17911 * instead of sending separate HTT messages for each wrong MSDU within 17912 * the MPDU. 17913 * 17914 * |31 24|23 16|15 8|7 0| 17915 * |----------------+----------------+----------------+----------------| 17916 * | Rsvd | key_id | peer_id | 17917 * |-------------------------------------------------------------------| 17918 * | receiver MAC addr 31:0 | 17919 * |-------------------------------------------------------------------| 17920 * | Rsvd | receiver MAC addr 47:32 | 17921 * |-------------------------------------------------------------------| 17922 * | transmitter MAC addr 31:0 | 17923 * |-------------------------------------------------------------------| 17924 * | Rsvd | transmitter MAC addr 47:32 | 17925 * |-------------------------------------------------------------------| 17926 * | PN 31:0 | 17927 * |-------------------------------------------------------------------| 17928 * | Rsvd | PN 47:32 | 17929 * |-------------------------------------------------------------------| 17930 * - peer_id 17931 * Bits 15:0 17932 * Purpose: identifies which peer is frame is from 17933 * value: 17934 * - key_id 17935 * Bits 23:16 17936 * Purpose: identifies key_id of rx frame 17937 * value: 17938 * - RA_31_0 (receiver MAC addr 31:0) 17939 * Bits 31:0 17940 * Purpose: identifies by MAC address which vdev received the frame 17941 * value: MAC address lower 4 bytes 17942 * - RA_47_32 (receiver MAC addr 47:32) 17943 * Bits 15:0 17944 * Purpose: identifies by MAC address which vdev received the frame 17945 * value: MAC address upper 2 bytes 17946 * - TA_31_0 (transmitter MAC addr 31:0) 17947 * Bits 31:0 17948 * Purpose: identifies by MAC address which peer transmitted the frame 17949 * value: MAC address lower 4 bytes 17950 * - TA_47_32 (transmitter MAC addr 47:32) 17951 * Bits 15:0 17952 * Purpose: identifies by MAC address which peer transmitted the frame 17953 * value: MAC address upper 2 bytes 17954 * - PN_31_0 17955 * Bits 31:0 17956 * Purpose: Identifies pn of rx frame 17957 * value: PN lower 4 bytes 17958 * - PN_47_32 17959 * Bits 15:0 17960 * Purpose: Identifies pn of rx frame 17961 * value: 17962 * TKIP or CCMP: PN upper 2 bytes 17963 * WAPI: PN bytes 6:5 (bytes 15:7 not included in this message) 17964 */ 17965 17966 enum htt_rx_ofld_pkt_err_type { 17967 HTT_RX_OFLD_PKT_ERR_TYPE_NONE = 0, 17968 HTT_RX_OFLD_PKT_ERR_TYPE_MIC_ERR, 17969 }; 17970 17971 /* definition for HTT_RX_OFLD_PKT_ERR msg hdr */ 17972 #define HTT_RX_OFLD_PKT_ERR_HDR_BYTES 4 17973 17974 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M 0x0000ff00 17975 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S 8 17976 17977 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_M 0x00ff0000 17978 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_S 16 17979 17980 #define HTT_RX_OFLD_PKT_ERR_TID_M 0xff000000 17981 #define HTT_RX_OFLD_PKT_ERR_TID_S 24 17982 17983 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_GET(_var) \ 17984 (((_var) & HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M) \ 17985 >> HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S) 17986 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_SET(_var, _val) \ 17987 do { \ 17988 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE, _val); \ 17989 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)); \ 17990 } while (0) 17991 17992 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_GET(_var) \ 17993 (((_var) & HTT_RX_OFLD_PKT_ERR_VDEV_ID_M) >> HTT_RX_OFLD_PKT_ERR_VDEV_ID_S) 17994 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_SET(_var, _val) \ 17995 do { \ 17996 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_VDEV_ID, _val); \ 17997 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)); \ 17998 } while (0) 17999 18000 #define HTT_RX_OFLD_PKT_ERR_TID_GET(_var) \ 18001 (((_var) & HTT_RX_OFLD_PKT_ERR_TID_M) >> HTT_RX_OFLD_PKT_ERR_TID_S) 18002 #define HTT_RX_OFLD_PKT_ERR_TID_SET(_var, _val) \ 18003 do { \ 18004 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_TID, _val); \ 18005 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_TID_S)); \ 18006 } while (0) 18007 18008 /* definition for HTT_RX_OFLD_PKT_ERR_MIC_ERR msg sub-type payload */ 18009 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_BYTES 28 18010 18011 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M 0x0000ffff 18012 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S 0 18013 18014 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M 0x00ff0000 18015 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S 16 18016 18017 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M 0xffffffff 18018 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S 0 18019 18020 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M 0x0000ffff 18021 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S 0 18022 18023 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M 0xffffffff 18024 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S 0 18025 18026 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M 0x0000ffff 18027 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S 0 18028 18029 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M 0xffffffff 18030 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S 0 18031 18032 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M 0x0000ffff 18033 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S 0 18034 18035 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_GET(_var) \ 18036 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M) >> \ 18037 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S) 18038 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_SET(_var, _val) \ 18039 do { \ 18040 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID, _val); \ 18041 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)); \ 18042 } while (0) 18043 18044 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_GET(_var) \ 18045 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M) >> \ 18046 HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S) 18047 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_SET(_var, _val) \ 18048 do { \ 18049 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID, _val); \ 18050 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)); \ 18051 } while (0) 18052 18053 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_GET(_var) \ 18054 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M) >> \ 18055 HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S) 18056 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_SET(_var, _val) \ 18057 do { \ 18058 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0, _val); \ 18059 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)); \ 18060 } while (0) 18061 18062 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_GET(_var) \ 18063 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M) >> \ 18064 HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S) 18065 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_SET(_var, _val) \ 18066 do { \ 18067 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32, _val); \ 18068 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)); \ 18069 } while (0) 18070 18071 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_GET(_var) \ 18072 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M) >> \ 18073 HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S) 18074 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_SET(_var, _val) \ 18075 do { \ 18076 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0, _val); \ 18077 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)); \ 18078 } while (0) 18079 18080 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_GET(_var) \ 18081 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M) >> \ 18082 HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S) 18083 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_SET(_var, _val) \ 18084 do { \ 18085 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32, _val); \ 18086 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)); \ 18087 } while (0) 18088 18089 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_GET(_var) \ 18090 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M) >> \ 18091 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S) 18092 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_SET(_var, _val) \ 18093 do { \ 18094 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0, _val); \ 18095 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)); \ 18096 } while (0) 18097 18098 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_GET(_var) \ 18099 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M) >> \ 18100 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S) 18101 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_SET(_var, _val) \ 18102 do { \ 18103 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32, _val); \ 18104 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)); \ 18105 } while (0) 18106 18107 /** 18108 * @brief target -> host peer rate report message 18109 * 18110 * MSG_TYPE => HTT_T2H_MSG_TYPE_RATE_REPORT 18111 * 18112 * @details 18113 * HTT_T2H_MSG_TYPE_RATE_REPORT message is sent by target to host to indicate the 18114 * justified rate of all the peers. 18115 * 18116 * |31 24|23 16|15 8|7 0| 18117 * |----------------+----------------+----------------+----------------| 18118 * | peer_count | | msg_type | 18119 * |-------------------------------------------------------------------| 18120 * : Payload (variant number of peer rate report) : 18121 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: 18122 * Header fields: 18123 * - msg_type 18124 * Bits 7:0 18125 * Purpose: Identifies this as HTT_T2H_MSG_TYPE_RATE_REPORT message. 18126 * value: 0x17 (HTT_T2H_MSG_TYPE_RATE_REPORT) 18127 * - reserved 18128 * Bits 15:8 18129 * Purpose: 18130 * value: 18131 * - peer_count 18132 * Bits 31:16 18133 * Purpose: Specify how many peer rate report elements are present in the payload. 18134 * value: 18135 * 18136 * Payload: 18137 * There are variant number of peer rate report follow the first 32 bits. 18138 * The peer rate report is defined as follows. 18139 * 18140 * |31 20|19 16|15 0| 18141 * |-----------------------+---------+---------------------------------|- 18142 * | reserved | phy | peer_id | \ 18143 * |-------------------------------------------------------------------| -> report #0 18144 * | rate | / 18145 * |-----------------------+---------+---------------------------------|- 18146 * | reserved | phy | peer_id | \ 18147 * |-------------------------------------------------------------------| -> report #1 18148 * | rate | / 18149 * |-----------------------+---------+---------------------------------|- 18150 * | reserved | phy | peer_id | \ 18151 * |-------------------------------------------------------------------| -> report #2 18152 * | rate | / 18153 * |-------------------------------------------------------------------|- 18154 * : : 18155 * : : 18156 * : : 18157 * :-------------------------------------------------------------------: 18158 * 18159 * - peer_id 18160 * Bits 15:0 18161 * Purpose: identify the peer 18162 * value: 18163 * - phy 18164 * Bits 19:16 18165 * Purpose: identify which phy is in use 18166 * value: 0=11b, 1=11a/g, 2=11n, 3=11ac. 18167 * Please see enum htt_peer_report_phy_type for detail. 18168 * - reserved 18169 * Bits 31:20 18170 * Purpose: 18171 * value: 18172 * - rate 18173 * Bits 31:0 18174 * Purpose: represent the justified rate of the peer specified by peer_id 18175 * value: 18176 */ 18177 18178 enum htt_peer_rate_report_phy_type { 18179 HTT_PEER_RATE_REPORT_11B = 0, 18180 HTT_PEER_RATE_REPORT_11A_G, 18181 HTT_PEER_RATE_REPORT_11N, 18182 HTT_PEER_RATE_REPORT_11AC, 18183 }; 18184 18185 #define HTT_PEER_RATE_REPORT_SIZE 8 18186 18187 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M 0xffff0000 18188 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S 16 18189 18190 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_M 0x0000ffff 18191 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_S 0 18192 18193 #define HTT_PEER_RATE_REPORT_MSG_PHY_M 0x000f0000 18194 #define HTT_PEER_RATE_REPORT_MSG_PHY_S 16 18195 18196 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_GET(_var) \ 18197 (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M) \ 18198 >> HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S) 18199 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_SET(_var, _val) \ 18200 do { \ 18201 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_COUNT, _val); \ 18202 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)); \ 18203 } while (0) 18204 18205 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_GET(_var) \ 18206 (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_ID_M) \ 18207 >> HTT_PEER_RATE_REPORT_MSG_PEER_ID_S) 18208 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_SET(_var, _val) \ 18209 do { \ 18210 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_ID, _val); \ 18211 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)); \ 18212 } while (0) 18213 18214 #define HTT_PEER_RATE_REPORT_MSG_PHY_GET(_var) \ 18215 (((_var) & HTT_PEER_RATE_REPORT_MSG_PHY_M) \ 18216 >> HTT_PEER_RATE_REPORT_MSG_PHY_S) 18217 #define HTT_PEER_RATE_REPORT_MSG_PHY_SET(_var, _val) \ 18218 do { \ 18219 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PHY, _val); \ 18220 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PHY_S)); \ 18221 } while (0) 18222 18223 /** 18224 * @brief target -> host flow pool map message 18225 * 18226 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_MAP 18227 * 18228 * @details 18229 * HTT_T2H_MSG_TYPE_FLOW_POOL_MAP message is sent by the target when setting up 18230 * a flow of descriptors. 18231 * 18232 * This message is in TLV format and indicates the parameters to be setup a 18233 * flow in the host. Each entry indicates that a particular flow ID is ready to 18234 * receive descriptors from a specified pool. 18235 * 18236 * The message would appear as follows: 18237 * 18238 * |31 24|23 16|15 8|7 0| 18239 * |----------------+----------------+----------------+----------------| 18240 * header | reserved | num_flows | msg_type | 18241 * |-------------------------------------------------------------------| 18242 * | | 18243 * : payload : 18244 * | | 18245 * |-------------------------------------------------------------------| 18246 * 18247 * The header field is one DWORD long and is interpreted as follows: 18248 * b'0:7 - msg_type: Set to 0x18 (HTT_T2H_MSG_TYPE_FLOW_POOL_MAP) 18249 * b'8-15 - num_flows: This will indicate the number of flows being setup in 18250 * this message 18251 * b'16-31 - reserved: These bits are reserved for future use 18252 * 18253 * Payload: 18254 * The payload would contain multiple objects of the following structure. Each 18255 * object represents a flow. 18256 * 18257 * |31 24|23 16|15 8|7 0| 18258 * |----------------+----------------+----------------+----------------| 18259 * header | reserved | num_flows | msg_type | 18260 * |-------------------------------------------------------------------| 18261 * payload0| flow_type | 18262 * |-------------------------------------------------------------------| 18263 * | flow_id | 18264 * |-------------------------------------------------------------------| 18265 * | reserved0 | flow_pool_id | 18266 * |-------------------------------------------------------------------| 18267 * | reserved1 | flow_pool_size | 18268 * |-------------------------------------------------------------------| 18269 * | reserved2 | 18270 * |-------------------------------------------------------------------| 18271 * payload1| flow_type | 18272 * |-------------------------------------------------------------------| 18273 * | flow_id | 18274 * |-------------------------------------------------------------------| 18275 * | reserved0 | flow_pool_id | 18276 * |-------------------------------------------------------------------| 18277 * | reserved1 | flow_pool_size | 18278 * |-------------------------------------------------------------------| 18279 * | reserved2 | 18280 * |-------------------------------------------------------------------| 18281 * | . | 18282 * | . | 18283 * | . | 18284 * |-------------------------------------------------------------------| 18285 * 18286 * Each payload is 5 DWORDS long and is interpreted as follows: 18287 * dword0 - b'0:31 - flow_type: This indicates the type of the entity to which 18288 * this flow is associated. It can be VDEV, peer, 18289 * or tid (AC). Based on enum htt_flow_type. 18290 * 18291 * dword1 - b'0:31 - flow_id: Identifier for the flow corresponding to this 18292 * object. For flow_type vdev it is set to the 18293 * vdevid, for peer it is peerid and for tid, it is 18294 * tid_num. 18295 * 18296 * dword2 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being used 18297 * in the host for this flow 18298 * b'16:31 - reserved0: This field in reserved for the future. In case 18299 * we have a hierarchical implementation (HCM) of 18300 * pools, it can be used to indicate the ID of the 18301 * parent-pool. 18302 * 18303 * dword3 - b'0:15 - flow_pool_size: Size of the pool in number of descriptors. 18304 * Descriptors for this flow will be 18305 * allocated from this pool in the host. 18306 * b'16:31 - reserved1: This field in reserved for the future. In case 18307 * we have a hierarchical implementation of pools, 18308 * it can be used to indicate the max number of 18309 * descriptors in the pool. The b'0:15 can be used 18310 * to indicate min number of descriptors in the 18311 * HCM scheme. 18312 * 18313 * dword4 - b'0:31 - reserved2: This field in reserved for the future. In case 18314 * we have a hierarchical implementation of pools, 18315 * b'0:15 can be used to indicate the 18316 * priority-based borrowing (PBB) threshold of 18317 * the flow's pool. The b'16:31 are still left 18318 * reserved. 18319 */ 18320 18321 enum htt_flow_type { 18322 FLOW_TYPE_VDEV = 0, 18323 /* Insert new flow types above this line */ 18324 }; 18325 18326 PREPACK struct htt_flow_pool_map_payload_t { 18327 A_UINT32 flow_type; 18328 A_UINT32 flow_id; 18329 A_UINT32 flow_pool_id:16, 18330 reserved0:16; 18331 A_UINT32 flow_pool_size:16, 18332 reserved1:16; 18333 A_UINT32 reserved2; 18334 } POSTPACK; 18335 18336 #define HTT_FLOW_POOL_MAP_HEADER_SZ (sizeof(A_UINT32)) 18337 18338 #define HTT_FLOW_POOL_MAP_PAYLOAD_SZ \ 18339 (sizeof(struct htt_flow_pool_map_payload_t)) 18340 18341 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_M 0x0000ff00 18342 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_S 8 18343 18344 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_M 0xffffffff 18345 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_S 0 18346 18347 #define HTT_FLOW_POOL_MAP_FLOW_ID_M 0xffffffff 18348 #define HTT_FLOW_POOL_MAP_FLOW_ID_S 0 18349 18350 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M 0x0000ffff 18351 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S 0 18352 18353 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M 0x0000ffff 18354 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S 0 18355 18356 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_GET(_var) \ 18357 (((_var) & HTT_FLOW_POOL_MAP_NUM_FLOWS_M) >> HTT_FLOW_POOL_MAP_NUM_FLOWS_S) 18358 18359 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_GET(_var) \ 18360 (((_var) & HTT_FLOW_POOL_MAP_FLOW_TYPE_M) >> HTT_FLOW_POOL_MAP_FLOW_TYPE_S) 18361 18362 #define HTT_FLOW_POOL_MAP_FLOW_ID_GET(_var) \ 18363 (((_var) & HTT_FLOW_POOL_MAP_FLOW_ID_M) >> HTT_FLOW_POOL_MAP_FLOW_ID_S) 18364 18365 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_GET(_var) \ 18366 (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M) >> \ 18367 HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S) 18368 18369 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_GET(_var) \ 18370 (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M) >> \ 18371 HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S) 18372 18373 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_SET(_var, _val) \ 18374 do { \ 18375 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_NUM_FLOWS, _val); \ 18376 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_NUM_FLOWS_S)); \ 18377 } while (0) 18378 18379 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_SET(_var, _val) \ 18380 do { \ 18381 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_TYPE, _val); \ 18382 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_TYPE_S)); \ 18383 } while (0) 18384 18385 #define HTT_FLOW_POOL_MAP_FLOW_ID_SET(_var, _val) \ 18386 do { \ 18387 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_ID, _val); \ 18388 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_ID_S)); \ 18389 } while (0) 18390 18391 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_SET(_var, _val) \ 18392 do { \ 18393 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_ID, _val); \ 18394 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)); \ 18395 } while (0) 18396 18397 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_SET(_var, _val) \ 18398 do { \ 18399 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE, _val); \ 18400 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)); \ 18401 } while (0) 18402 18403 /** 18404 * @brief target -> host flow pool unmap message 18405 * 18406 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP 18407 * 18408 * @details 18409 * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP message is sent by the target when tearing 18410 * down a flow of descriptors. 18411 * This message indicates that for the flow (whose ID is provided) is wanting 18412 * to stop receiving descriptors. This flow ID corresponds to the ID of the 18413 * pool of descriptors from where descriptors are being allocated for this 18414 * flow. When a flow (and its pool) are unmapped, all the child-pools will also 18415 * be unmapped by the host. 18416 * 18417 * The message would appear as follows: 18418 * 18419 * |31 24|23 16|15 8|7 0| 18420 * |----------------+----------------+----------------+----------------| 18421 * | reserved0 | msg_type | 18422 * |-------------------------------------------------------------------| 18423 * | flow_type | 18424 * |-------------------------------------------------------------------| 18425 * | flow_id | 18426 * |-------------------------------------------------------------------| 18427 * | reserved1 | flow_pool_id | 18428 * |-------------------------------------------------------------------| 18429 * 18430 * The message is interpreted as follows: 18431 * dword0 - b'0:7 - msg_type: This will be set to 0x19 18432 * (HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP) 18433 * b'8:31 - reserved0: Reserved for future use 18434 * 18435 * dword1 - b'0:31 - flow_type: This indicates the type of the entity to which 18436 * this flow is associated. It can be VDEV, peer, 18437 * or tid (AC). Based on enum htt_flow_type. 18438 * 18439 * dword2 - b'0:31 - flow_id: Identifier for the flow corresponding to this 18440 * object. For flow_type vdev it is set to the 18441 * vdevid, for peer it is peerid and for tid, it is 18442 * tid_num. 18443 * 18444 * dword3 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being 18445 * used in the host for this flow 18446 * b'16:31 - reserved0: This field in reserved for the future. 18447 * 18448 */ 18449 18450 PREPACK struct htt_flow_pool_unmap_t { 18451 A_UINT32 msg_type:8, 18452 reserved0:24; 18453 A_UINT32 flow_type; 18454 A_UINT32 flow_id; 18455 A_UINT32 flow_pool_id:16, 18456 reserved1:16; 18457 } POSTPACK; 18458 18459 #define HTT_FLOW_POOL_UNMAP_SZ (sizeof(struct htt_flow_pool_unmap_t)) 18460 18461 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M 0xffffffff 18462 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S 0 18463 18464 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_M 0xffffffff 18465 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_S 0 18466 18467 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M 0x0000ffff 18468 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S 0 18469 18470 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_GET(_var) \ 18471 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M) >> \ 18472 HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S) 18473 18474 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_GET(_var) \ 18475 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_ID_M) >> HTT_FLOW_POOL_UNMAP_FLOW_ID_S) 18476 18477 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_GET(_var) \ 18478 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M) >> \ 18479 HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S) 18480 18481 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_SET(_var, _val) \ 18482 do { \ 18483 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_TYPE, _val); \ 18484 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)); \ 18485 } while (0) 18486 18487 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_SET(_var, _val) \ 18488 do { \ 18489 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_ID, _val); \ 18490 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_ID_S)); \ 18491 } while (0) 18492 18493 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_SET(_var, _val) \ 18494 do { \ 18495 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID, _val); \ 18496 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)); \ 18497 } while (0) 18498 18499 18500 /** 18501 * @brief target -> host SRING setup done message 18502 * 18503 * MSG_TYPE => HTT_T2H_MSG_TYPE_SRING_SETUP_DONE 18504 * 18505 * @details 18506 * HTT_T2H_MSG_TYPE_SRING_SETUP_DONE message is sent by the target when 18507 * SRNG ring setup is done 18508 * 18509 * This message indicates whether the last setup operation is successful. 18510 * It will be sent to host when host set respose_required bit in 18511 * HTT_H2T_MSG_TYPE_SRING_SETUP. 18512 * The message would appear as follows: 18513 * 18514 * |31 24|23 16|15 8|7 0| 18515 * |--------------- +----------------+----------------+----------------| 18516 * | setup_status | ring_id | pdev_id | msg_type | 18517 * |-------------------------------------------------------------------| 18518 * 18519 * The message is interpreted as follows: 18520 * dword0 - b'0:7 - msg_type: This will be set to 0x1a 18521 * (HTT_T2H_MSG_TYPE_SRING_SETUP_DONE) 18522 * b'8:15 - pdev_id: 18523 * 0 (for rings at SOC/UMAC level), 18524 * 1/2/3 mac id (for rings at LMAC level) 18525 * b'16:23 - ring_id: Identify the ring which is set up 18526 * More details can be got from enum htt_srng_ring_id 18527 * b'24:31 - setup_status: Indicate status of setup operation 18528 * Refer to htt_ring_setup_status 18529 */ 18530 18531 PREPACK struct htt_sring_setup_done_t { 18532 A_UINT32 msg_type: 8, 18533 pdev_id: 8, 18534 ring_id: 8, 18535 setup_status: 8; 18536 } POSTPACK; 18537 18538 enum htt_ring_setup_status { 18539 htt_ring_setup_status_ok = 0, 18540 htt_ring_setup_status_error, 18541 }; 18542 18543 #define HTT_SRING_SETUP_DONE_SZ (sizeof(struct htt_sring_setup_done_t)) 18544 18545 #define HTT_SRING_SETUP_DONE_PDEV_ID_M 0x0000ff00 18546 #define HTT_SRING_SETUP_DONE_PDEV_ID_S 8 18547 #define HTT_SRING_SETUP_DONE_PDEV_ID_GET(_var) \ 18548 (((_var) & HTT_SRING_SETUP_DONE_PDEV_ID_M) >> \ 18549 HTT_SRING_SETUP_DONE_PDEV_ID_S) 18550 #define HTT_SRING_SETUP_DONE_PDEV_ID_SET(_var, _val) \ 18551 do { \ 18552 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_PDEV_ID, _val); \ 18553 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ 18554 } while (0) 18555 18556 #define HTT_SRING_SETUP_DONE_RING_ID_M 0x00ff0000 18557 #define HTT_SRING_SETUP_DONE_RING_ID_S 16 18558 #define HTT_SRING_SETUP_DONE_RING_ID_GET(_var) \ 18559 (((_var) & HTT_SRING_SETUP_DONE_RING_ID_M) >> \ 18560 HTT_SRING_SETUP_DONE_RING_ID_S) 18561 #define HTT_SRING_SETUP_DONE_RING_ID_SET(_var, _val) \ 18562 do { \ 18563 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_RING_ID, _val); \ 18564 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_RING_ID_S)); \ 18565 } while (0) 18566 18567 #define HTT_SRING_SETUP_DONE_STATUS_M 0xff000000 18568 #define HTT_SRING_SETUP_DONE_STATUS_S 24 18569 #define HTT_SRING_SETUP_DONE_STATUS_GET(_var) \ 18570 (((_var) & HTT_SRING_SETUP_DONE_STATUS_M) >> \ 18571 HTT_SRING_SETUP_DONE_STATUS_S) 18572 #define HTT_SRING_SETUP_DONE_STATUS_SET(_var, _val) \ 18573 do { \ 18574 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_STATUS, _val); \ 18575 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_STATUS_S)); \ 18576 } while (0) 18577 18578 18579 /** 18580 * @brief target -> flow map flow info 18581 * 18582 * MSG_TYPE => HTT_T2H_MSG_TYPE_MAP_FLOW_INFO 18583 * 18584 * @details 18585 * HTT TX map flow entry with tqm flow pointer 18586 * Sent from firmware to host to add tqm flow pointer in corresponding 18587 * flow search entry. Flow metadata is replayed back to host as part of this 18588 * struct to enable host to find the specific flow search entry 18589 * 18590 * The message would appear as follows: 18591 * 18592 * |31 28|27 18|17 14|13 8|7 0| 18593 * |-------+------------------------------------------+----------------| 18594 * | rsvd0 | fse_hsh_idx | msg_type | 18595 * |-------------------------------------------------------------------| 18596 * | rsvd1 | tid | peer_id | 18597 * |-------------------------------------------------------------------| 18598 * | tqm_flow_pntr_lo | 18599 * |-------------------------------------------------------------------| 18600 * | tqm_flow_pntr_hi | 18601 * |-------------------------------------------------------------------| 18602 * | fse_meta_data | 18603 * |-------------------------------------------------------------------| 18604 * 18605 * The message is interpreted as follows: 18606 * 18607 * dword0 - b'0:7 - msg_type: This will be set to 0x1b 18608 * (HTT_T2H_MSG_TYPE_MAP_FLOW_INFO) 18609 * 18610 * dword0 - b'8:27 - fse_hsh_idx: Flow search table index provided by host 18611 * for this flow entry 18612 * 18613 * dword0 - b'28:31 - rsvd0: Reserved for future use 18614 * 18615 * dword1 - b'0:13 - peer_id: Software peer id given by host during association 18616 * 18617 * dword1 - b'14:17 - tid 18618 * 18619 * dword1 - b'18:31 - rsvd1: Reserved for future use 18620 * 18621 * dword2 - b'0:31 - tqm_flow_pntr_lo: Lower 32 bits of TQM flow pointer 18622 * 18623 * dword3 - b'0:31 - tqm_flow_pntr_hi: Higher 32 bits of TQM flow pointer 18624 * 18625 * dword4 - b'0:31 - fse_meta_data: Replay back TX flow search metadata 18626 * given by host 18627 */ 18628 PREPACK struct htt_tx_map_flow_info { 18629 A_UINT32 18630 msg_type: 8, 18631 fse_hsh_idx: 20, 18632 rsvd0: 4; 18633 A_UINT32 18634 peer_id: 14, 18635 tid: 4, 18636 rsvd1: 14; 18637 A_UINT32 tqm_flow_pntr_lo; 18638 A_UINT32 tqm_flow_pntr_hi; 18639 struct htt_tx_flow_metadata fse_meta_data; 18640 } POSTPACK; 18641 18642 /* DWORD 0 */ 18643 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M 0x0fffff00 18644 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S 8 18645 18646 /* DWORD 1 */ 18647 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_M 0x00003fff 18648 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_S 0 18649 #define HTT_TX_MAP_FLOW_INFO_TID_M 0x0003c000 18650 #define HTT_TX_MAP_FLOW_INFO_TID_S 14 18651 18652 /* DWORD 0 */ 18653 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_GET(_var) \ 18654 (((_var) & HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M) >> \ 18655 HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S) 18656 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_SET(_var, _val) \ 18657 do { \ 18658 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX, _val); \ 18659 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S)); \ 18660 } while (0) 18661 18662 /* DWORD 1 */ 18663 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_GET(_var) \ 18664 (((_var) & HTT_TX_MAP_FLOW_INFO_PEER_ID_M) >> \ 18665 HTT_TX_MAP_FLOW_INFO_PEER_ID_S) 18666 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_SET(_var, _val) \ 18667 do { \ 18668 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_PEER_ID_IDX, _val); \ 18669 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_PEER_ID_S)); \ 18670 } while (0) 18671 18672 #define HTT_TX_MAP_FLOW_INFO_TID_GET(_var) \ 18673 (((_var) & HTT_TX_MAP_FLOW_INFO_TID_M) >> \ 18674 HTT_TX_MAP_FLOW_INFO_TID_S) 18675 #define HTT_TX_MAP_FLOW_INFO_TID_SET(_var, _val) \ 18676 do { \ 18677 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_TID_IDX, _val); \ 18678 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_TID_S)); \ 18679 } while (0) 18680 18681 18682 /* 18683 * htt_dbg_ext_stats_status - 18684 * present - The requested stats have been delivered in full. 18685 * This indicates that either the stats information was contained 18686 * in its entirety within this message, or else this message 18687 * completes the delivery of the requested stats info that was 18688 * partially delivered through earlier STATS_CONF messages. 18689 * partial - The requested stats have been delivered in part. 18690 * One or more subsequent STATS_CONF messages with the same 18691 * cookie value will be sent to deliver the remainder of the 18692 * information. 18693 * error - The requested stats could not be delivered, for example due 18694 * to a shortage of memory to construct a message holding the 18695 * requested stats. 18696 * invalid - The requested stat type is either not recognized, or the 18697 * target is configured to not gather the stats type in question. 18698 */ 18699 enum htt_dbg_ext_stats_status { 18700 HTT_DBG_EXT_STATS_STATUS_PRESENT = 0, 18701 HTT_DBG_EXT_STATS_STATUS_PARTIAL = 1, 18702 HTT_DBG_EXT_STATS_STATUS_ERROR = 2, 18703 HTT_DBG_EXT_STATS_STATUS_INVALID = 3, 18704 }; 18705 18706 /** 18707 * @brief target -> host ppdu stats upload 18708 * 18709 * MSG_TYPE => HTT_T2H_MSG_TYPE_PPDU_STATS_IND 18710 * 18711 * @details 18712 * The following field definitions describe the format of the HTT target 18713 * to host ppdu stats indication message. 18714 * 18715 * 18716 * |31 24|23 16|15 12|11 10|9 8|7 0 | 18717 * |-----------------------------+-------+-------+--------+---------------| 18718 * | payload_size | rsvd |pdev_id|mac_id | msg type | 18719 * |-------------+---------------+-------+-------+--------+---------------| 18720 * | tgt_private | ppdu_id | 18721 * |-------------+--------------------------------------------------------| 18722 * | Timestamp in us | 18723 * |----------------------------------------------------------------------| 18724 * | reserved | 18725 * |----------------------------------------------------------------------| 18726 * | type-specific stats info | 18727 * | (see htt_ppdu_stats.h) | 18728 * |----------------------------------------------------------------------| 18729 * Header fields: 18730 * - MSG_TYPE 18731 * Bits 7:0 18732 * Purpose: Identifies this is a PPDU STATS indication 18733 * message. 18734 * Value: 0x1d (HTT_T2H_MSG_TYPE_PPDU_STATS_IND) 18735 * - mac_id 18736 * Bits 9:8 18737 * Purpose: mac_id of this ppdu_id 18738 * Value: 0-3 18739 * - pdev_id 18740 * Bits 11:10 18741 * Purpose: pdev_id of this ppdu_id 18742 * Value: 0-3 18743 * 0 (for rings at SOC level), 18744 * 1/2/3 PDEV -> 0/1/2 18745 * - payload_size 18746 * Bits 31:16 18747 * Purpose: total tlv size 18748 * Value: payload_size in bytes 18749 */ 18750 #define HTT_T2H_PPDU_STATS_IND_HDR_SIZE 16 18751 18752 #define HTT_T2H_PPDU_STATS_MAC_ID_M 0x00000300 18753 #define HTT_T2H_PPDU_STATS_MAC_ID_S 8 18754 18755 #define HTT_T2H_PPDU_STATS_PDEV_ID_M 0x00000C00 18756 #define HTT_T2H_PPDU_STATS_PDEV_ID_S 10 18757 18758 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000 18759 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16 18760 18761 #define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF 18762 #define HTT_T2H_PPDU_STATS_PPDU_ID_S 0 18763 /* bits 31:24 are used by the target for internal purposes */ 18764 18765 #define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \ 18766 do { \ 18767 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_MAC_ID, value); \ 18768 (word) |= (value) << HTT_T2H_PPDU_STATS_MAC_ID_S; \ 18769 } while (0) 18770 #define HTT_T2H_PPDU_STATS_MAC_ID_GET(word) \ 18771 (((word) & HTT_T2H_PPDU_STATS_MAC_ID_M) >> \ 18772 HTT_T2H_PPDU_STATS_MAC_ID_S) 18773 18774 #define HTT_T2H_PPDU_STATS_PDEV_ID_SET(word, value) \ 18775 do { \ 18776 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PDEV_ID, value); \ 18777 (word) |= (value) << HTT_T2H_PPDU_STATS_PDEV_ID_S; \ 18778 } while (0) 18779 #define HTT_T2H_PPDU_STATS_PDEV_ID_GET(word) \ 18780 (((word) & HTT_T2H_PPDU_STATS_PDEV_ID_M) >> \ 18781 HTT_T2H_PPDU_STATS_PDEV_ID_S) 18782 18783 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_SET(word, value) \ 18784 do { \ 18785 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PAYLOAD_SIZE, value); \ 18786 (word) |= (value) << HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S; \ 18787 } while (0) 18788 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_GET(word) \ 18789 (((word) & HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M) >> \ 18790 HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S) 18791 18792 #define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \ 18793 do { \ 18794 /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \ 18795 (word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \ 18796 } while (0) 18797 #define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \ 18798 (((word) & HTT_T2H_PPDU_STATS_PPDU_ID_M) >> \ 18799 HTT_T2H_PPDU_STATS_PPDU_ID_S) 18800 18801 /* htt_t2h_ppdu_stats_ind_hdr_t 18802 * This struct contains the fields within the header of the 18803 * HTT_T2H_PPDU_STATS_IND message, preceding the type-specific 18804 * stats info. 18805 * This struct assumes little-endian layout, and thus is only 18806 * suitable for use within processors known to be little-endian 18807 * (such as the target). 18808 * In contrast, the above macros provide endian-portable methods 18809 * to get and set the bitfields within this PPDU_STATS_IND header. 18810 */ 18811 typedef struct { 18812 A_UINT32 msg_type: 8, /* bits 7:0 */ 18813 mac_id: 2, /* bits 9:8 */ 18814 pdev_id: 2, /* bits 11:10 */ 18815 reserved1: 4, /* bits 15:12 */ 18816 payload_size: 16; /* bits 31:16 */ 18817 A_UINT32 ppdu_id; 18818 A_UINT32 timestamp_us; 18819 A_UINT32 reserved2; 18820 } htt_t2h_ppdu_stats_ind_hdr_t; 18821 18822 /** 18823 * @brief target -> host extended statistics upload 18824 * 18825 * MSG_TYPE => HTT_T2H_MSG_TYPE_EXT_STATS_CONF 18826 * 18827 * @details 18828 * The following field definitions describe the format of the HTT target 18829 * to host stats upload confirmation message. 18830 * The message contains a cookie echoed from the HTT host->target stats 18831 * upload request, which identifies which request the confirmation is 18832 * for, and a single stats can span over multiple HTT stats indication 18833 * due to the HTT message size limitation so every HTT ext stats indication 18834 * will have tag-length-value stats information elements. 18835 * The tag-length header for each HTT stats IND message also includes a 18836 * status field, to indicate whether the request for the stat type in 18837 * question was fully met, partially met, unable to be met, or invalid 18838 * (if the stat type in question is disabled in the target). 18839 * A Done bit 1's indicate the end of the of stats info elements. 18840 * 18841 * 18842 * |31 16|15 12|11|10 8|7 5|4 0| 18843 * |--------------------------------------------------------------| 18844 * | reserved | msg type | 18845 * |--------------------------------------------------------------| 18846 * | cookie LSBs | 18847 * |--------------------------------------------------------------| 18848 * | cookie MSBs | 18849 * |--------------------------------------------------------------| 18850 * | stats entry length | rsvd | D| S | stat type | 18851 * |--------------------------------------------------------------| 18852 * | type-specific stats info | 18853 * | (see htt_stats.h) | 18854 * |--------------------------------------------------------------| 18855 * Header fields: 18856 * - MSG_TYPE 18857 * Bits 7:0 18858 * Purpose: Identifies this is a extended statistics upload confirmation 18859 * message. 18860 * Value: 0x1c (HTT_T2H_MSG_TYPE_EXT_STATS_CONF) 18861 * - COOKIE_LSBS 18862 * Bits 31:0 18863 * Purpose: Provide a mechanism to match a target->host stats confirmation 18864 * message with its preceding host->target stats request message. 18865 * Value: LSBs of the opaque cookie specified by the host-side requestor 18866 * - COOKIE_MSBS 18867 * Bits 31:0 18868 * Purpose: Provide a mechanism to match a target->host stats confirmation 18869 * message with its preceding host->target stats request message. 18870 * Value: MSBs of the opaque cookie specified by the host-side requestor 18871 * 18872 * Stats Information Element tag-length header fields: 18873 * - STAT_TYPE 18874 * Bits 7:0 18875 * Purpose: identifies the type of statistics info held in the 18876 * following information element 18877 * Value: htt_dbg_ext_stats_type 18878 * - STATUS 18879 * Bits 10:8 18880 * Purpose: indicate whether the requested stats are present 18881 * Value: htt_dbg_ext_stats_status 18882 * - DONE 18883 * Bits 11 18884 * Purpose: 18885 * Indicates the completion of the stats entry, this will be the last 18886 * stats conf HTT segment for the requested stats type. 18887 * Value: 18888 * 0 -> the stats retrieval is ongoing 18889 * 1 -> the stats retrieval is complete 18890 * - LENGTH 18891 * Bits 31:16 18892 * Purpose: indicate the stats information size 18893 * Value: This field specifies the number of bytes of stats information 18894 * that follows the element tag-length header. 18895 * It is expected but not required that this length is a multiple of 18896 * 4 bytes. 18897 */ 18898 #define HTT_T2H_EXT_STATS_COOKIE_SIZE 8 18899 18900 #define HTT_T2H_EXT_STATS_CONF_HDR_SIZE 4 18901 18902 #define HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE 4 18903 18904 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M 0x000000ff 18905 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S 0 18906 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M 0x00000700 18907 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S 8 18908 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_M 0x00000800 18909 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_S 11 18910 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M 0xffff0000 18911 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S 16 18912 18913 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_SET(word, value) \ 18914 do { \ 18915 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_TYPE, value); \ 18916 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S; \ 18917 } while (0) 18918 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_GET(word) \ 18919 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M) >> \ 18920 HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S) 18921 18922 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_SET(word, value) \ 18923 do { \ 18924 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_STATUS, value); \ 18925 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S; \ 18926 } while (0) 18927 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_GET(word) \ 18928 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M) >> \ 18929 HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S) 18930 18931 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_SET(word, value) \ 18932 do { \ 18933 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_DONE, value); \ 18934 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_DONE_S; \ 18935 } while (0) 18936 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_GET(word) \ 18937 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_DONE_M) >> \ 18938 HTT_T2H_EXT_STATS_CONF_TLV_DONE_S) 18939 18940 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_SET(word, value) \ 18941 do { \ 18942 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_LENGTH, value); \ 18943 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S; \ 18944 } while (0) 18945 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_GET(word) \ 18946 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M) >> \ 18947 HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S) 18948 18949 18950 /** 18951 * @brief target -> host streaming statistics upload 18952 * 18953 * MSG_TYPE => HTT_T2H_MSG_TYPE_STREAMING_STATS_IND 18954 * 18955 * @details 18956 * The following field definitions describe the format of the HTT target 18957 * to host streaming stats upload indication message. 18958 * The host can use a STREAMING_STATS_REQ message to enable the target to 18959 * produce an ongoing series of STREAMING_STATS_IND messages, and can also 18960 * use the STREAMING_STATS_REQ message to halt the target's production of 18961 * STREAMING_STATS_IND messages. 18962 * The STREAMING_STATS_IND message contains a payload of TLVs containing 18963 * the stats enabled by the host's STREAMING_STATS_REQ message. 18964 * 18965 * |31 8|7 0| 18966 * |--------------------------------------------------------------| 18967 * | reserved | msg type | 18968 * |--------------------------------------------------------------| 18969 * | type-specific stats info | 18970 * | (see htt_stats.h) | 18971 * |--------------------------------------------------------------| 18972 * Header fields: 18973 * - MSG_TYPE 18974 * Bits 7:0 18975 * Purpose: Identifies this as a streaming statistics upload indication 18976 * message. 18977 * Value: 0x2f (HTT_T2H_MSG_TYPE_STREAMING_STATS_IND) 18978 */ 18979 18980 #define HTT_T2H_STREAMING_STATS_IND_HDR_SIZE 4 18981 18982 18983 typedef enum { 18984 HTT_PEER_TYPE_DEFAULT = 0, /* Generic/Non-BSS/Self Peer */ 18985 HTT_PEER_TYPE_BSS = 1, /* Peer is BSS Peer entry */ 18986 HTT_PEER_TYPE_TDLS = 2, /* Peer is a TDLS Peer */ 18987 HTT_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */ 18988 HTT_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ 18989 HTT_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ 18990 /* Reserved from 128 - 255 for target internal use.*/ 18991 HTT_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ 18992 } HTT_PEER_TYPE; 18993 18994 /** macro to convert MAC address from char array to HTT word format */ 18995 #define HTT_CHAR_ARRAY_TO_MAC_ADDR(c_macaddr, phtt_mac_addr) do { \ 18996 (phtt_mac_addr)->mac_addr31to0 = \ 18997 (((c_macaddr)[0] << 0) | \ 18998 ((c_macaddr)[1] << 8) | \ 18999 ((c_macaddr)[2] << 16) | \ 19000 ((c_macaddr)[3] << 24)); \ 19001 (phtt_mac_addr)->mac_addr47to32 = ((c_macaddr)[4] | ((c_macaddr)[5] << 8));\ 19002 } while (0) 19003 19004 /** 19005 * @brief target -> host monitor mac header indication message 19006 * 19007 * MSG_TYPE => HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND 19008 * 19009 * @details 19010 * The following diagram shows the format of the monitor mac header message 19011 * sent from the target to the host. 19012 * This message is primarily sent when promiscuous rx mode is enabled. 19013 * One message is sent per rx PPDU. 19014 * 19015 * |31 24|23 16|15 8|7 0| 19016 * |-------------------------------------------------------------| 19017 * | peer_id | reserved0 | msg_type | 19018 * |-------------------------------------------------------------| 19019 * | reserved1 | num_mpdu | 19020 * |-------------------------------------------------------------| 19021 * | struct hw_rx_desc | 19022 * | (see wal_rx_desc.h) | 19023 * |-------------------------------------------------------------| 19024 * | struct ieee80211_frame_addr4 | 19025 * | (see ieee80211_defs.h) | 19026 * |-------------------------------------------------------------| 19027 * | struct ieee80211_frame_addr4 | 19028 * | (see ieee80211_defs.h) | 19029 * |-------------------------------------------------------------| 19030 * | ...... | 19031 * |-------------------------------------------------------------| 19032 * 19033 * Header fields: 19034 * - msg_type 19035 * Bits 7:0 19036 * Purpose: Identifies this is a monitor mac header indication message. 19037 * Value: 0x20 (HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND) 19038 * - peer_id 19039 * Bits 31:16 19040 * Purpose: Software peer id given by host during association, 19041 * During promiscuous mode, the peer ID will be invalid (0xFF) 19042 * for rx PPDUs received from unassociated peers. 19043 * Value: peer ID (for associated peers) or 0xFF (for unassociated peers) 19044 * - num_mpdu 19045 * Bits 15:0 19046 * Purpose: The number of MPDU frame headers (struct ieee80211_frame_addr4) 19047 * delivered within the message. 19048 * Value: 1 to 32 19049 * num_mpdu is limited to a maximum value of 32, due to buffer 19050 * size limits. For PPDUs with more than 32 MPDUs, only the 19051 * ieee80211_frame_addr4 headers from the first 32 MPDUs within 19052 * the PPDU will be provided. 19053 */ 19054 #define HTT_T2H_MONITOR_MAC_HEADER_IND_HDR_SIZE 8 19055 19056 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M 0xFFFF0000 19057 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S 16 19058 19059 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M 0x0000FFFF 19060 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S 0 19061 19062 19063 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_SET(word, value) \ 19064 do { \ 19065 HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_PEER_ID, value); \ 19066 (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S; \ 19067 } while (0) 19068 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_GET(word) \ 19069 (((word) & HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M) >> \ 19070 HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S) 19071 19072 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_SET(word, value) \ 19073 do { \ 19074 HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU, value); \ 19075 (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S; \ 19076 } while (0) 19077 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_GET(word) \ 19078 (((word) & HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M) >> \ 19079 HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S) 19080 19081 /** 19082 * @brief target -> host flow pool resize Message 19083 * 19084 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE 19085 * 19086 * @details 19087 * HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE message is sent by the target when 19088 * the flow pool associated with the specified ID is resized 19089 * 19090 * The message would appear as follows: 19091 * 19092 * |31 16|15 8|7 0| 19093 * |---------------------------------+----------------+----------------| 19094 * | reserved0 | Msg type | 19095 * |-------------------------------------------------------------------| 19096 * | flow pool new size | flow pool ID | 19097 * |-------------------------------------------------------------------| 19098 * 19099 * The message is interpreted as follows: 19100 * b'0:7 - msg_type: This will be set to 0x21 19101 * (HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE) 19102 * 19103 * b'0:15 - flow pool ID: Existing flow pool ID 19104 * 19105 * b'16:31 - flow pool new size: new pool size for existing flow pool ID 19106 * 19107 */ 19108 19109 PREPACK struct htt_flow_pool_resize_t { 19110 A_UINT32 msg_type:8, 19111 reserved0:24; 19112 A_UINT32 flow_pool_id:16, 19113 flow_pool_new_size:16; 19114 } POSTPACK; 19115 19116 #define HTT_FLOW_POOL_RESIZE_SZ (sizeof(struct htt_flow_pool_resize_t)) 19117 19118 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M 0x0000ffff 19119 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S 0 19120 19121 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M 0xffff0000 19122 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S 16 19123 19124 19125 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_GET(_var) \ 19126 (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M) >> \ 19127 HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S) 19128 19129 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_SET(_var, _val) \ 19130 do { \ 19131 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID, _val); \ 19132 ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S)); \ 19133 } while (0) 19134 19135 19136 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_GET(_var) \ 19137 (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M) >> \ 19138 HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S) 19139 19140 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_SET(_var, _val) \ 19141 do { \ 19142 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE, _val); \ 19143 ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)); \ 19144 } while (0) 19145 19146 19147 19148 #define HTT_CFR_CAPTURE_MAGIC_PATTERN 0xCCCCCCCC 19149 #define HTT_CFR_CAPTURE_READ_INDEX_OFFSET 0 /* bytes */ 19150 #define HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES 4 19151 #define HTT_CFR_CAPTURE_WRITE_INDEX_OFFSET /* bytes */ \ 19152 (HTT_CFR_CAPTURE_READ_INDEX_OFFSET + HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES) 19153 #define HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES 4 19154 #define HTT_CFR_CAPTURE_SIZEOF_MAGIC_PATTERN_BYTES 4 19155 /* 19156 * The read and write indices point to the data within the host buffer. 19157 * Because the first 4 bytes of the host buffer is used for the read index and 19158 * the next 4 bytes for the write index, the data itself starts at offset 8. 19159 * The read index and write index are the byte offsets from the base of the 19160 * meta-data buffer, and thus have a minimum value of 8 rather than 0. 19161 * Refer the ASCII text picture below. 19162 */ 19163 #define HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX \ 19164 (HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES + \ 19165 HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES) 19166 19167 /* 19168 *************************************************************************** 19169 * 19170 * Layout when CFR capture message type is 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' 19171 * 19172 *************************************************************************** 19173 * 19174 * The memory allocated by WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID is used 19175 * in the below format. The HTT message 'htt_cfr_dump_compl_ind' is sent by 19176 * FW to Host whenever a CFR capture (CFR data1 or CFR data2 etc.,) is 19177 * written into the Host memory region mentioned below. 19178 * 19179 * Read index is updated by the Host. At any point of time, the read index will 19180 * indicate the index that will next be read by the Host. The read index is 19181 * in units of bytes offset from the base of the meta-data buffer. 19182 * 19183 * Write index is updated by the FW. At any point of time, the write index will 19184 * indicate from where the FW can start writing any new data. The write index is 19185 * in units of bytes offset from the base of the meta-data buffer. 19186 * 19187 * If the Host is not fast enough in reading the CFR data, any new capture data 19188 * would be dropped if there is no space left to write the new captures. 19189 * 19190 * The last 4 bytes of the memory region will have the magic pattern 19191 * HTT_CFR_CAPTURE_MAGIC_PATTERN. This can be used to ensure that the FW does 19192 * not overrun the host buffer. 19193 * 19194 * ,--------------------. read and write indices store the 19195 * | | byte offset from the base of the 19196 * | ,--------+--------. meta-data buffer to the next 19197 * | | | | location within the data buffer 19198 * | | v v that will be read / written 19199 * ************************************************************************ 19200 * * Read * Write * * Magic * 19201 * * index * index * CFR data1 ...... CFR data N * pattern * 19202 * * (4 bytes) * (4 bytes) * * (4 bytes)* 19203 * ************************************************************************ 19204 * |<---------- data buffer ---------->| 19205 * 19206 * |<----------------- meta-data buffer allocated in Host ----------------| 19207 * 19208 * Note: 19209 * - Considering the 4 bytes needed to store the Read index (R) and the 19210 * Write index (W), the initial value is as follows: 19211 * R = W = HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX 19212 * - Buffer empty condition: 19213 * R = W 19214 * 19215 * Regarding CFR data format: 19216 * -------------------------- 19217 * 19218 * Each CFR tone is stored in HW as 16-bits with the following format: 19219 * {bits[15:12], bits[11:6], bits[5:0]} = 19220 * {unsigned exponent (4 bits), 19221 * signed mantissa_real (6 bits), 19222 * signed mantissa_imag (6 bits)} 19223 * 19224 * CFR_real = mantissa_real * 2^(exponent-5) 19225 * CFR_imag = mantissa_imag * 2^(exponent-5) 19226 * 19227 * 19228 * The CFR data is written to the 16-bit unsigned output array (buff) in 19229 * ascending tone order. For example, the Legacy20 CFR is output as follows: 19230 * 19231 * buff[0]: [CFR_exp[-26], CFR_mant_real[-26], CFR_mant_imag[-26]] 19232 * buff[1]: [CFR_exp[-25], CFR_mant_real[-25], CFR_mant_imag[-25]] 19233 * . 19234 * . 19235 * . 19236 * buff[N-2]: [CFR_exp[25], CFR_mant_real[25], CFR_mant_imag[25]] 19237 * buff[N-1]: [CFR_exp[26], CFR_mant_real[26], CFR_mant_imag[26]] 19238 */ 19239 19240 /* Bandwidth of peer CFR captures */ 19241 typedef enum { 19242 HTT_PEER_CFR_CAPTURE_BW_20MHZ = 0, 19243 HTT_PEER_CFR_CAPTURE_BW_40MHZ = 1, 19244 HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2, 19245 HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3, 19246 HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, 19247 HTT_PEER_CFR_CAPTURE_BW_MAX, 19248 } HTT_PEER_CFR_CAPTURE_BW; 19249 19250 /* Mode of the peer CFR captures. The type of RX frame for which the CFR 19251 * was captured 19252 */ 19253 typedef enum { 19254 HTT_PEER_CFR_CAPTURE_MODE_LEGACY = 0, 19255 HTT_PEER_CFR_CAPTURE_MODE_DUP_LEGACY = 1, 19256 HTT_PEER_CFR_CAPTURE_MODE_HT = 2, 19257 HTT_PEER_CFR_CAPTURE_MODE_VHT = 3, 19258 HTT_PEER_CFR_CAPTURE_MODE_MAX, 19259 } HTT_PEER_CFR_CAPTURE_MODE; 19260 19261 typedef enum { 19262 /* This message type is currently used for the below purpose: 19263 * 19264 * - capture_method = WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME in the 19265 * wmi_peer_cfr_capture_cmd. 19266 * If payload_present bit is set to 0 then the associated memory region 19267 * gets allocated through WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID. 19268 * If payload_present bit is set to 1 then CFR dump is part of the HTT 19269 * message; the CFR dump will be present at the end of the message, 19270 * after the chan_phy_mode. 19271 */ 19272 HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 = 0x1, 19273 19274 /* Always keep this last */ 19275 HTT_PEER_CFR_CAPTURE_MSG_TYPE_MAX, 19276 } HTT_PEER_CFR_CAPTURE_MSG_TYPE; 19277 19278 /** 19279 * @brief target -> host CFR dump completion indication message definition 19280 * htt_cfr_dump_compl_ind when the version is HTT_PEER_CFR_CAPTURE_MSG_TYPE_1. 19281 * 19282 * MSG_TYPE => HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND 19283 * 19284 * @details 19285 * The following diagram shows the format of the Channel Frequency Response 19286 * (CFR) dump completion indication. This inidcation is sent to the Host when 19287 * the channel capture of a peer is copied by Firmware into the Host memory 19288 * 19289 * ************************************************************************** 19290 * 19291 * Message format when the CFR capture message type is 19292 * 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' 19293 * 19294 * ************************************************************************** 19295 * 19296 * |31 16|15 |8|7 0| 19297 * |----------------------------------------------------------------| 19298 * header: | reserved |P| msg_type | 19299 * word 0 | | | | 19300 * |----------------------------------------------------------------| 19301 * payload: | cfr_capture_msg_type | 19302 * word 1 | | 19303 * |----------------------------------------------------------------| 19304 * | vdev_id | captype | chbw | sts | mode | capbw |S| req_id | 19305 * word 2 | | | | | | | | | 19306 * |----------------------------------------------------------------| 19307 * | mac_addr31to0 | 19308 * word 3 | | 19309 * |----------------------------------------------------------------| 19310 * | unused / reserved | mac_addr47to32 | 19311 * word 4 | | | 19312 * |----------------------------------------------------------------| 19313 * | index | 19314 * word 5 | | 19315 * |----------------------------------------------------------------| 19316 * | length | 19317 * word 6 | | 19318 * |----------------------------------------------------------------| 19319 * | timestamp | 19320 * word 7 | | 19321 * |----------------------------------------------------------------| 19322 * | counter | 19323 * word 8 | | 19324 * |----------------------------------------------------------------| 19325 * | chan_mhz | 19326 * word 9 | | 19327 * |----------------------------------------------------------------| 19328 * | band_center_freq1 | 19329 * word 10 | | 19330 * |----------------------------------------------------------------| 19331 * | band_center_freq2 | 19332 * word 11 | | 19333 * |----------------------------------------------------------------| 19334 * | chan_phy_mode | 19335 * word 12 | | 19336 * |----------------------------------------------------------------| 19337 * where, 19338 * P - payload present bit (payload_present explained below) 19339 * req_id - memory request id (mem_req_id explained below) 19340 * S - status field (status explained below) 19341 * capbw - capture bandwidth (capture_bw explained below) 19342 * mode - mode of capture (mode explained below) 19343 * sts - space time streams (sts_count explained below) 19344 * chbw - channel bandwidth (channel_bw explained below) 19345 * captype - capture type (cap_type explained below) 19346 * 19347 * The following field definitions describe the format of the CFR dump 19348 * completion indication sent from the target to the host 19349 * 19350 * Header fields: 19351 * 19352 * Word 0 19353 * - msg_type 19354 * Bits 7:0 19355 * Purpose: Identifies this as CFR TX completion indication 19356 * Value: 0x22 (HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND) 19357 * - payload_present 19358 * Bit 8 19359 * Purpose: Identifies how CFR data is sent to host 19360 * Value: 0 - If CFR Payload is written to host memory 19361 * 1 - If CFR Payload is sent as part of HTT message 19362 * (This is the requirement for SDIO/USB where it is 19363 * not possible to write CFR data to host memory) 19364 * - reserved 19365 * Bits 31:9 19366 * Purpose: Reserved 19367 * Value: 0 19368 * 19369 * Payload fields: 19370 * 19371 * Word 1 19372 * - cfr_capture_msg_type 19373 * Bits 31:0 19374 * Purpose: Contains the type of the message HTT_PEER_CFR_CAPTURE_MSG_TYPE 19375 * to specify the format used for the remainder of the message 19376 * Value: HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 19377 * (currently only MSG_TYPE_1 is defined) 19378 * 19379 * Word 2 19380 * - mem_req_id 19381 * Bits 6:0 19382 * Purpose: Contain the mem request id of the region where the CFR capture 19383 * has been stored - of type WMI_HOST_MEM_REQ_ID 19384 * Value: WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID (if payload_present is 1, 19385 this value is invalid) 19386 * - status 19387 * Bit 7 19388 * Purpose: Boolean value carrying the status of the CFR capture of the peer 19389 * Value: 1 (True) - Successful; 0 (False) - Not successful 19390 * - capture_bw 19391 * Bits 10:8 19392 * Purpose: Carry the bandwidth of the CFR capture 19393 * Value: Bandwidth of the CFR capture of type HTT_PEER_CFR_CAPTURE_BW 19394 * - mode 19395 * Bits 13:11 19396 * Purpose: Carry the mode of the rx frame for which the CFR was captured 19397 * Value: Mode of the CFR capture of type HTT_PEER_CFR_CAPTURE_MODE 19398 * - sts_count 19399 * Bits 16:14 19400 * Purpose: Carry the number of space time streams 19401 * Value: Number of space time streams 19402 * - channel_bw 19403 * Bits 19:17 19404 * Purpose: Carry the bandwidth of the channel of the vdev performing the 19405 * measurement 19406 * Value: Bandwidth of the channel (of type HTT_PEER_CFR_CAPTURE_BW) 19407 * - cap_type 19408 * Bits 23:20 19409 * Purpose: Carry the type of the capture 19410 * Value: Capture type (of type WMI_PEER_CFR_CAPTURE_METHOD) 19411 * - vdev_id 19412 * Bits 31:24 19413 * Purpose: Carry the virtual device id 19414 * Value: vdev ID 19415 * 19416 * Word 3 19417 * - mac_addr31to0 19418 * Bits 31:0 19419 * Purpose: Contain the bits 31:0 of the peer MAC address 19420 * Value: Bits 31:0 of the peer MAC address 19421 * 19422 * Word 4 19423 * - mac_addr47to32 19424 * Bits 15:0 19425 * Purpose: Contain the bits 47:32 of the peer MAC address 19426 * Value: Bits 47:32 of the peer MAC address 19427 * 19428 * Word 5 19429 * - index 19430 * Bits 31:0 19431 * Purpose: Contain the index at which this CFR dump was written in the Host 19432 * allocated memory. This index is the number of bytes from the base address. 19433 * Value: Index position 19434 * 19435 * Word 6 19436 * - length 19437 * Bits 31:0 19438 * Purpose: Carry the length of the CFR capture of the peer, in bytes 19439 * Value: Length of the CFR capture of the peer 19440 * 19441 * Word 7 19442 * - timestamp 19443 * Bits 31:0 19444 * Purpose: Carry the time at which the CFR was captured in the hardware. The 19445 * clock used for this timestamp is private to the target and not visible to 19446 * the host i.e., Host can interpret only the relative timestamp deltas from 19447 * one message to the next, but can't interpret the absolute timestamp from a 19448 * single message. 19449 * Value: Timestamp in microseconds 19450 * 19451 * Word 8 19452 * - counter 19453 * Bits 31:0 19454 * Purpose: Carry the count of the current CFR capture from FW. This is 19455 * helpful to identify any drops in FW in any scenario (e.g., lack of space 19456 * in host memory) 19457 * Value: Count of the current CFR capture 19458 * 19459 * Word 9 19460 * - chan_mhz 19461 * Bits 31:0 19462 * Purpose: Carry the primary 20 MHz channel frequency in MHz of the VDEV 19463 * Value: Primary 20 channel frequency 19464 * 19465 * Word 10 19466 * - band_center_freq1 19467 * Bits 31:0 19468 * Purpose: Carry the center frequency 1 in MHz of the VDEV 19469 * Value: Center frequency 1 in MHz 19470 * 19471 * Word 11 19472 * - band_center_freq2 19473 * Bits 31:0 19474 * Purpose: Carry the center frequency 2 in MHz. valid only for 11acvht of 19475 * the VDEV 19476 * 80plus80 mode 19477 * Value: Center frequency 2 in MHz 19478 * 19479 * Word 12 19480 * - chan_phy_mode 19481 * Bits 31:0 19482 * Purpose: Carry the phy mode of the channel, of the VDEV 19483 * Value: WLAN_PHY_MODE of the channel defined in wlan_defs.h 19484 */ 19485 PREPACK struct htt_cfr_dump_ind_type_1 { 19486 A_UINT32 mem_req_id:7, 19487 status:1, 19488 capture_bw:3, 19489 mode:3, 19490 sts_count:3, 19491 channel_bw:3, 19492 cap_type:4, 19493 vdev_id:8; 19494 htt_mac_addr addr; 19495 A_UINT32 index; 19496 A_UINT32 length; 19497 A_UINT32 timestamp; 19498 A_UINT32 counter; 19499 struct htt_chan_change_msg chan; 19500 } POSTPACK; 19501 19502 PREPACK struct htt_cfr_dump_compl_ind { 19503 A_UINT32 msg_type; /* HTT_PEER_CFR_CAPTURE_MSG_TYPE */ 19504 union { 19505 /* Message format when msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 */ 19506 struct htt_cfr_dump_ind_type_1 htt_cfr_dump_compl_ind_type_1; 19507 /* If there is a need to change the memory layout and its associated 19508 * HTT indication format, a new CFR capture message type can be 19509 * introduced and added into this union. 19510 */ 19511 }; 19512 } POSTPACK; 19513 19514 /* 19515 * Get / set macros for the bit fields within WORD-1 of htt_cfr_dump_compl_ind, 19516 * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 19517 */ 19518 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M 0x00000100 19519 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S 8 19520 19521 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_SET(word, value) \ 19522 do { \ 19523 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID, value); \ 19524 (word) |= (value) << HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S; \ 19525 } while(0) 19526 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_GET(word) \ 19527 (((word) & HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M) >> \ 19528 HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S) 19529 19530 /* 19531 * Get / set macros for the bit fields within WORD-2 of htt_cfr_dump_compl_ind, 19532 * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 19533 */ 19534 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M 0X0000007F 19535 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S 0 19536 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_M 0X00000080 19537 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_S 7 19538 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M 0X00000700 19539 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S 8 19540 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_M 0X00003800 19541 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_S 11 19542 #define HTT_T2H_CFR_DUMP_TYPE1_STS_M 0X0001C000 19543 #define HTT_T2H_CFR_DUMP_TYPE1_STS_S 14 19544 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M 0X000E0000 19545 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S 17 19546 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M 0X00F00000 19547 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S 20 19548 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M 0XFF000000 19549 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S 24 19550 19551 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_SET(word, value) \ 19552 do { \ 19553 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID, value); \ 19554 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S; \ 19555 } while (0) 19556 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_GET(word) \ 19557 (((word) & HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M) >> \ 19558 HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S) 19559 19560 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_SET(word, value) \ 19561 do { \ 19562 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STATUS, value); \ 19563 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STATUS_S; \ 19564 } while (0) 19565 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_GET(word) \ 19566 (((word) & HTT_T2H_CFR_DUMP_TYPE1_STATUS_M) >> \ 19567 HTT_T2H_CFR_DUMP_TYPE1_STATUS_S) 19568 19569 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_SET(word, value) \ 19570 do { \ 19571 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_BW, value); \ 19572 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S; \ 19573 } while (0) 19574 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_GET(word) \ 19575 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M) >> \ 19576 HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S) 19577 19578 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_SET(word, value) \ 19579 do { \ 19580 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MODE, value); \ 19581 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MODE_S; \ 19582 } while (0) 19583 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_GET(word) \ 19584 (((word) & HTT_T2H_CFR_DUMP_TYPE1_MODE_M) >> \ 19585 HTT_T2H_CFR_DUMP_TYPE1_MODE_S) 19586 19587 #define HTT_T2H_CFR_DUMP_TYPE1_STS_SET(word, value) \ 19588 do { \ 19589 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STS, value); \ 19590 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STS_S; \ 19591 } while (0) 19592 #define HTT_T2H_CFR_DUMP_TYPE1_STS_GET(word) \ 19593 (((word) & HTT_T2H_CFR_DUMP_TYPE1_STS_M) >> \ 19594 HTT_T2H_CFR_DUMP_TYPE1_STS_S) 19595 19596 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_SET(word, value) \ 19597 do { \ 19598 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW, value); \ 19599 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S; \ 19600 } while (0) 19601 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_GET(word) \ 19602 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M) >> \ 19603 HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S) 19604 19605 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_SET(word, value) \ 19606 do { \ 19607 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE, value); \ 19608 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S; \ 19609 } while (0) 19610 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_GET(word) \ 19611 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M) >> \ 19612 HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S) 19613 19614 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_SET(word, value) \ 19615 do { \ 19616 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID, value); \ 19617 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S; \ 19618 } while (0) 19619 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_GET(word) \ 19620 (((word) & HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M) >> \ 19621 HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S) 19622 19623 19624 /** 19625 * @brief target -> host peer (PPDU) stats message 19626 * 19627 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_STATS_IND 19628 * 19629 * @details 19630 * This message is generated by FW when FW is sending stats to host 19631 * about one or more PPDUs that the FW has transmitted to one or more peers. 19632 * This message is sent autonomously by the target rather than upon request 19633 * by the host. 19634 * The following field definitions describe the format of the HTT target 19635 * to host peer stats indication message. 19636 * 19637 * The HTT_T2H PPDU_STATS_IND message has a header followed by one 19638 * or more PPDU stats records. 19639 * Each PPDU stats record uses a htt_tx_ppdu_stats_info TLV. 19640 * If the details of N PPDUS are sent in one PEER_STATS_IND message, 19641 * then the message would start with the 19642 * header, followed by N htt_tx_ppdu_stats_info structures, as depicted 19643 * below. 19644 * 19645 * |31 16|15|14|13 11|10 9|8|7 0| 19646 * |-------------------------------------------------------------| 19647 * | reserved |MSG_TYPE | 19648 * |-------------------------------------------------------------| 19649 * rec 0 | TLV header | 19650 * rec 0 |-------------------------------------------------------------| 19651 * rec 0 | ppdu successful bytes | 19652 * rec 0 |-------------------------------------------------------------| 19653 * rec 0 | ppdu retry bytes | 19654 * rec 0 |-------------------------------------------------------------| 19655 * rec 0 | ppdu failed bytes | 19656 * rec 0 |-------------------------------------------------------------| 19657 * rec 0 | peer id | S|SG| BW | BA |A|rate code| 19658 * rec 0 |-------------------------------------------------------------| 19659 * rec 0 | retried MSDUs | successful MSDUs | 19660 * rec 0 |-------------------------------------------------------------| 19661 * rec 0 | TX duration | failed MSDUs | 19662 * rec 0 |-------------------------------------------------------------| 19663 * ... 19664 * |-------------------------------------------------------------| 19665 * rec N | TLV header | 19666 * rec N |-------------------------------------------------------------| 19667 * rec N | ppdu successful bytes | 19668 * rec N |-------------------------------------------------------------| 19669 * rec N | ppdu retry bytes | 19670 * rec N |-------------------------------------------------------------| 19671 * rec N | ppdu failed bytes | 19672 * rec N |-------------------------------------------------------------| 19673 * rec N | peer id | S|SG| BW | BA |A|rate code| 19674 * rec N |-------------------------------------------------------------| 19675 * rec N | retried MSDUs | successful MSDUs | 19676 * rec N |-------------------------------------------------------------| 19677 * rec N | TX duration | failed MSDUs | 19678 * rec N |-------------------------------------------------------------| 19679 * 19680 * where: 19681 * A = is A-MPDU flag 19682 * BA = block-ack failure flags 19683 * BW = bandwidth spec 19684 * SG = SGI enabled spec 19685 * S = skipped rate ctrl 19686 * One htt_tx_ppdu_stats_info instance will have stats for one PPDU 19687 * 19688 * Header 19689 * ------ 19690 * dword0 - b'0:7 - msg_type : 0x23 (HTT_T2H_MSG_TYPE_PEER_STATS_IND) 19691 * dword0 - b'8:31 - reserved : Reserved for future use 19692 * 19693 * payload include below peer_stats information 19694 * -------------------------------------------- 19695 * @TLV : HTT_PPDU_STATS_INFO_TLV 19696 * @tx_success_bytes : total successful bytes in the PPDU. 19697 * @tx_retry_bytes : total retried bytes in the PPDU. 19698 * @tx_failed_bytes : total failed bytes in the PPDU. 19699 * @tx_ratecode : rate code used for the PPDU. 19700 * @is_ampdu : Indicates PPDU is AMPDU or not. 19701 * @ba_ack_failed : BA/ACK failed for this PPDU 19702 * b00 -> BA received 19703 * b01 -> BA failed once 19704 * b10 -> BA failed twice, when HW retry is enabled. 19705 * @bw : BW 19706 * b00 -> 20 MHz 19707 * b01 -> 40 MHz 19708 * b10 -> 80 MHz 19709 * b11 -> 160 MHz (or 80+80) 19710 * @sg : SGI enabled 19711 * @s : skipped ratectrl 19712 * @peer_id : peer id 19713 * @tx_success_msdus : successful MSDUs 19714 * @tx_retry_msdus : retried MSDUs 19715 * @tx_failed_msdus : MSDUs dropped in FW after max retry 19716 * @tx_duration : Tx duration for the PPDU (microsecond units) 19717 */ 19718 19719 19720 /** 19721 * @brief target -> host backpressure event 19722 * 19723 * MSG_TYPE => HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND 19724 * 19725 * @details 19726 * HTT_T2H_MSG_TYPE_BKPRESSURE_EVENTID message is sent by the target when 19727 * continuous backpressure is seen in the LMAC/ UMAC rings software rings. 19728 * This message will only be sent if the backpressure condition has existed 19729 * continuously for an initial period (100 ms). 19730 * Repeat messages with updated information will be sent after each 19731 * subsequent period (100 ms) as long as the backpressure remains unabated. 19732 * This message indicates the ring id along with current head and tail index 19733 * locations (i.e. write and read indices). 19734 * The backpressure time indicates the time in ms for which continuous 19735 * backpressure has been observed in the ring. 19736 * 19737 * The message format is as follows: 19738 * 19739 * |31 24|23 16|15 8|7 0| 19740 * |----------------+----------------+----------------+----------------| 19741 * | ring_id | ring_type | pdev_id | msg_type | 19742 * |-------------------------------------------------------------------| 19743 * | tail_idx | head_idx | 19744 * |-------------------------------------------------------------------| 19745 * | backpressure_time_ms | 19746 * |-------------------------------------------------------------------| 19747 * 19748 * The message is interpreted as follows: 19749 * dword0 - b'0:7 - msg_type: This will be set to 0x24 19750 * (HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND) 19751 * b'8:15 - pdev_id: 0 indicates msg is for UMAC ring. 19752 * 1, 2, 3 indicates pdev_id 0,1,2 and 19753 * the msg is for LMAC ring. 19754 * b'16:23 - ring_type: Refer to enum htt_backpressure_ring_type. 19755 * b'24:31 - ring_id: Refer enum htt_backpressure_umac_ring_id/ 19756 * htt_backpressure_lmac_ring_id. This represents 19757 * the ring id for which continuous backpressure 19758 * is seen 19759 * 19760 * dword1 - b'0:15 - head_idx: This indicates the current head index of 19761 * the ring indicated by the ring_id 19762 * 19763 * dword1 - b'16:31 - tail_idx: This indicates the current tail index of 19764 * the ring indicated by the ring id 19765 * 19766 * dword2 - b'0:31 - backpressure_time_ms: Indicates how long continuous 19767 * backpressure has been seen in the ring 19768 * indicated by the ring_id. 19769 * Units = milliseconds 19770 */ 19771 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_M 0x0000ff00 19772 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_S 8 19773 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_M 0x00ff0000 19774 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_S 16 19775 #define HTT_T2H_RX_BKPRESSURE_RINGID_M 0xff000000 19776 #define HTT_T2H_RX_BKPRESSURE_RINGID_S 24 19777 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M 0x0000ffff 19778 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S 0 19779 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M 0xffff0000 19780 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S 16 19781 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_M 0xffffffff 19782 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_S 0 19783 19784 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_SET(word, value) \ 19785 do { \ 19786 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_PDEV_ID, value); \ 19787 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_PDEV_ID_S; \ 19788 } while (0) 19789 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_GET(word) \ 19790 (((word) & HTT_T2H_RX_BKPRESSURE_PDEV_ID_M) >> \ 19791 HTT_T2H_RX_BKPRESSURE_PDEV_ID_S) 19792 19793 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_SET(word, value) \ 19794 do { \ 19795 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RING_TYPE, value); \ 19796 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RING_TYPE_S; \ 19797 } while (0) 19798 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_GET(word) \ 19799 (((word) & HTT_T2H_RX_BKPRESSURE_RING_TYPE_M) >> \ 19800 HTT_T2H_RX_BKPRESSURE_RING_TYPE_S) 19801 19802 #define HTT_T2H_RX_BKPRESSURE_RINGID_SET(word, value) \ 19803 do { \ 19804 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RINGID, value); \ 19805 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RINGID_S; \ 19806 } while (0) 19807 #define HTT_T2H_RX_BKPRESSURE_RINGID_GET(word) \ 19808 (((word) & HTT_T2H_RX_BKPRESSURE_RINGID_M) >> \ 19809 HTT_T2H_RX_BKPRESSURE_RINGID_S) 19810 19811 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_SET(word, value) \ 19812 do { \ 19813 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_HEAD_IDX, value); \ 19814 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S; \ 19815 } while (0) 19816 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_GET(word) \ 19817 (((word) & HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M) >> \ 19818 HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S) 19819 19820 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_SET(word, value) \ 19821 do { \ 19822 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TAIL_IDX, value); \ 19823 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S; \ 19824 } while (0) 19825 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_GET(word) \ 19826 (((word) & HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M) >> \ 19827 HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S) 19828 19829 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_SET(word, value) \ 19830 do { \ 19831 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TIME_MS, value); \ 19832 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TIME_MS_S; \ 19833 } while (0) 19834 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_GET(word) \ 19835 (((word) & HTT_T2H_RX_BKPRESSURE_TIME_MS_M) >> \ 19836 HTT_T2H_RX_BKPRESSURE_TIME_MS_S) 19837 19838 enum htt_backpressure_ring_type { 19839 HTT_SW_RING_TYPE_UMAC, 19840 HTT_SW_RING_TYPE_LMAC, 19841 HTT_SW_RING_TYPE_MAX, 19842 }; 19843 19844 /* Ring id for which the message is sent to host */ 19845 enum htt_backpressure_umac_ringid { 19846 HTT_SW_RING_IDX_REO_REO2SW1_RING, 19847 HTT_SW_RING_IDX_REO_REO2SW2_RING, 19848 HTT_SW_RING_IDX_REO_REO2SW3_RING, 19849 HTT_SW_RING_IDX_REO_REO2SW4_RING, 19850 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 19851 HTT_SW_RING_IDX_REO_REO2TCL_RING, 19852 HTT_SW_RING_IDX_REO_REO2FW_RING, 19853 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 19854 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 19855 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 19856 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 19857 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 19858 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 19859 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 19860 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 19861 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 19862 HTT_SW_RING_IDX_REO_REO_CMD_RING, 19863 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 19864 HTT_SW_UMAC_RING_IDX_MAX, 19865 }; 19866 19867 enum htt_backpressure_lmac_ringid { 19868 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 19869 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 19870 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 19871 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 19872 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 19873 HTT_SW_RING_IDX_RXDMA2FW_RING, 19874 HTT_SW_RING_IDX_RXDMA2SW_RING, 19875 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 19876 HTT_SW_RING_IDX_RXDMA2REO_RING, 19877 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 19878 HTT_SW_RING_IDX_MONITOR_BUF_RING, 19879 HTT_SW_RING_IDX_MONITOR_DESC_RING, 19880 HTT_SW_RING_IDX_MONITOR_DEST_RING, 19881 HTT_SW_LMAC_RING_IDX_MAX, 19882 }; 19883 19884 PREPACK struct htt_t2h_msg_bkpressure_event_ind_t { 19885 A_UINT32 msg_type: 8, /* HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND */ 19886 pdev_id: 8, 19887 ring_type: 8, /* htt_backpressure_ring_type */ 19888 /* 19889 * ring_id holds an enum value from either 19890 * htt_backpressure_umac_ringid or 19891 * htt_backpressure_lmac_ringid, based on 19892 * the ring_type setting. 19893 */ 19894 ring_id: 8; 19895 A_UINT16 head_idx; 19896 A_UINT16 tail_idx; 19897 A_UINT32 backpressure_time_ms; /* Time in milliseconds for which backpressure is seen continuously */ 19898 } POSTPACK; 19899 19900 19901 /* 19902 * Defines two 32 bit words that can be used by the target to indicate a per 19903 * user RU allocation and rate information. 19904 * 19905 * This information is currently provided in the "sw_response_reference_ptr" 19906 * (word 0) and "sw_response_reference_ptr_ext" (word 1) fields of the 19907 * "rx_ppdu_end_user_stats" TLV. 19908 * 19909 * VALID: 19910 * The consumer of these words must explicitly check the valid bit, 19911 * and only attempt interpretation of any of the remaining fields if 19912 * the valid bit is set to 1. 19913 * 19914 * VERSION: 19915 * The consumer of these words must also explicitly check the version bit, 19916 * and only use the V0 definition if the VERSION field is set to 0. 19917 * 19918 * Version 1 is currently undefined, with the exception of the VALID and 19919 * VERSION fields. 19920 * 19921 * Version 0: 19922 * 19923 * The fields below are duplicated per BW. 19924 * 19925 * The consumer must determine which BW field to use, based on the UL OFDMA 19926 * PPDU BW indicated by HW. 19927 * 19928 * RU_START: RU26 start index for the user. 19929 * Note that this is always using the RU26 index, regardless 19930 * of the actual RU assigned to the user 19931 * (i.e. the second RU52 is RU_START 2, RU_SIZE 19932 * HTT_UL_OFDMA_V0_RU_SIZE_RU_52) 19933 * 19934 * For example, 20MHz (the value in the top row is RU_START) 19935 * 19936 * RU Size 0 (26): |0|1|2|3|4|5|6|7|8| 19937 * RU Size 1 (52): | | | | | | 19938 * RU Size 2 (106): | | | | 19939 * RU Size 3 (242): | | 19940 * 19941 * RU_SIZE: Indicates the RU size, as defined by enum 19942 * htt_ul_ofdma_user_info_ru_size. 19943 * 19944 * LDPC: LDPC enabled (if 0, BCC is used) 19945 * 19946 * DCM: DCM enabled 19947 * 19948 * |31 | 30|29 23|22 19|18 16|15 9| 8 | 7 |6 3|2 0| 19949 * |---------------------------------+--------------------------------| 19950 * |Ver|Valid| FW internal | 19951 * |---------------------------------+--------------------------------| 19952 * | reserved |Trig Type|RU SIZE| RU START |DCM|LDPC|MCS |NSS| 19953 * |---------------------------------+--------------------------------| 19954 */ 19955 19956 enum htt_ul_ofdma_user_info_ru_size { 19957 HTT_UL_OFDMA_V0_RU_SIZE_RU_26, 19958 HTT_UL_OFDMA_V0_RU_SIZE_RU_52, 19959 HTT_UL_OFDMA_V0_RU_SIZE_RU_106, 19960 HTT_UL_OFDMA_V0_RU_SIZE_RU_242, 19961 HTT_UL_OFDMA_V0_RU_SIZE_RU_484, 19962 HTT_UL_OFDMA_V0_RU_SIZE_RU_996, 19963 HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2 19964 }; 19965 19966 /* htt_up_ofdma_user_info_v0 provides an abstract view of the info */ 19967 struct htt_ul_ofdma_user_info_v0 { 19968 A_UINT32 word0; 19969 A_UINT32 word1; 19970 }; 19971 19972 #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \ 19973 A_UINT32 w0_fw_rsvd:29; \ 19974 A_UINT32 w0_manual_ulofdma_trig:1; \ 19975 A_UINT32 w0_valid:1; \ 19976 A_UINT32 w0_version:1; 19977 19978 struct htt_ul_ofdma_user_info_v0_bitmap_w0 { 19979 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 19980 }; 19981 19982 #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 \ 19983 A_UINT32 w1_nss:3; \ 19984 A_UINT32 w1_mcs:4; \ 19985 A_UINT32 w1_ldpc:1; \ 19986 A_UINT32 w1_dcm:1; \ 19987 A_UINT32 w1_ru_start:7; \ 19988 A_UINT32 w1_ru_size:3; \ 19989 A_UINT32 w1_trig_type:4; \ 19990 A_UINT32 w1_unused:9; 19991 struct htt_ul_ofdma_user_info_v0_bitmap_w1 { 19992 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 19993 }; 19994 19995 19996 #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \ 19997 A_UINT32 w0_fw_rsvd:27; \ 19998 A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \ 19999 A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \ 20000 A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ 20001 20002 struct htt_ul_ofdma_user_info_v1_bitmap_w0 { 20003 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 20004 }; 20005 20006 #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 \ 20007 A_UINT32 w1_unused_0_to_18:19; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ \ 20008 A_UINT32 w1_trig_type:4; \ 20009 A_UINT32 w1_unused_23_to_31:9; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ 20010 20011 struct htt_ul_ofdma_user_info_v1_bitmap_w1 { 20012 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 20013 }; 20014 20015 20016 /* htt_ul_ofdma_user_info_v0_bitmap shows what bitfields are within the info */ 20017 PREPACK struct htt_ul_ofdma_user_info_v0_bitmap { 20018 union { 20019 A_UINT32 word0; 20020 struct { 20021 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 20022 }; 20023 }; 20024 union { 20025 A_UINT32 word1; 20026 struct { 20027 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 20028 }; 20029 }; 20030 } POSTPACK; 20031 20032 /* 20033 * htt_ul_ofdma_user_info_v1_bitmap bits are aligned to 20034 * htt_ul_ofdma_user_info_v0_bitmap, based on the w0_version 20035 * this should be picked. 20036 */ 20037 PREPACK struct htt_ul_ofdma_user_info_v1_bitmap { 20038 union { 20039 A_UINT32 word0; 20040 struct { 20041 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 20042 }; 20043 }; 20044 union { 20045 A_UINT32 word1; 20046 struct { 20047 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 20048 }; 20049 }; 20050 } POSTPACK; 20051 20052 20053 enum HTT_UL_OFDMA_TRIG_TYPE { 20054 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0, 20055 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP, 20056 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_BAR, 20057 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_RTS_CTS, 20058 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BSR, 20059 }; 20060 20061 20062 #define HTT_UL_OFDMA_USER_INFO_V0_SZ (sizeof(struct htt_ul_ofdma_user_info_v0)) 20063 20064 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff 20065 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0 20066 20067 #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000 20068 #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29 20069 20070 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000 20071 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30 20072 20073 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M 0x80000000 20074 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S 31 20075 20076 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M 0x00000007 20077 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S 0 20078 20079 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M 0x00000078 20080 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S 3 20081 20082 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M 0x00000080 20083 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S 7 20084 20085 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M 0x00000100 20086 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S 8 20087 20088 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M 0x0000fe00 20089 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S 9 20090 20091 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M 0x00070000 20092 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S 16 20093 20094 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M 0x00780000 20095 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S 19 20096 20097 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_M 0xff800000 20098 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_S 23 20099 20100 /*--- word 0 ---*/ 20101 20102 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_GET(word) \ 20103 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S) 20104 20105 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_SET(word, _val) \ 20106 do { \ 20107 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL, _val); \ 20108 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)); \ 20109 } while (0) 20110 20111 20112 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(word) \ 20113 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S) 20114 20115 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_SET(word, _val) \ 20116 do { \ 20117 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID, _val); \ 20118 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)); \ 20119 } while (0) 20120 20121 20122 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(word) \ 20123 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S) 20124 20125 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_SET(word, _val) \ 20126 do { \ 20127 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VER, _val); \ 20128 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)); \ 20129 } while (0) 20130 20131 20132 /*--- word 1 ---*/ 20133 20134 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(word) \ 20135 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S) 20136 20137 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_SET(word, _val) \ 20138 do { \ 20139 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_NSS, _val); \ 20140 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)); \ 20141 } while (0) 20142 20143 20144 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(word) \ 20145 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S) 20146 20147 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_SET(word, _val) \ 20148 do { \ 20149 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_MCS, _val); \ 20150 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)); \ 20151 } while (0) 20152 20153 20154 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_GET(word) \ 20155 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S) 20156 20157 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_SET(word, _val) \ 20158 do { \ 20159 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC, _val); \ 20160 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)); \ 20161 } while (0) 20162 20163 20164 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_GET(word) \ 20165 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S) 20166 20167 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_SET(word, _val) \ 20168 do { \ 20169 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_DCM, _val); \ 20170 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)); \ 20171 } while (0) 20172 20173 20174 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(word) \ 20175 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S) 20176 20177 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_SET(word, _val) \ 20178 do { \ 20179 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START, _val); \ 20180 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)); \ 20181 } while (0) 20182 20183 20184 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(word) \ 20185 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S) 20186 20187 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_SET(word, _val) \ 20188 do { \ 20189 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE, _val); \ 20190 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)); \ 20191 } while (0) 20192 20193 20194 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_GET(word) \ 20195 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S) 20196 20197 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_SET(word, _val) \ 20198 do { \ 20199 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP, _val); \ 20200 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP_S)); \ 20201 } while (0) 20202 20203 /** 20204 * @brief target -> host channel calibration data message 20205 * 20206 * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CALDATA 20207 * 20208 * @brief host -> target channel calibration data message 20209 * 20210 * MSG_TYPE => HTT_H2T_MSG_TYPE_CHAN_CALDATA 20211 * 20212 * @details 20213 * The following field definitions describe the format of the channel 20214 * calibration data message sent from the target to the host when 20215 * MSG_TYPE is HTT_T2H_MSG_TYPE_CHAN_CALDATA, and sent from the host 20216 * to the target when MSG_TYPE is HTT_H2T_MSG_TYPE_CHAN_CALDATA. 20217 * The message is defined as htt_chan_caldata_msg followed by a variable 20218 * number of 32-bit character values. 20219 * 20220 * |31 21|20|19 16|15 13| 12|11 8|7 0| 20221 * |------------------------------------------------------------------| 20222 * | rsv | A| frag | rsv |ck_v| sub_type| msg type | 20223 * |------------------------------------------------------------------| 20224 * | payload size | mhz | 20225 * |------------------------------------------------------------------| 20226 * | center frequency 2 | center frequency 1 | 20227 * |------------------------------------------------------------------| 20228 * | check sum | 20229 * |------------------------------------------------------------------| 20230 * | payload | 20231 * |------------------------------------------------------------------| 20232 * message info field: 20233 * - MSG_TYPE 20234 * Bits 7:0 20235 * Purpose: identifies this as a channel calibration data message 20236 * Value: 0x25 (HTT_T2H_MSG_TYPE_CHAN_CALDATA) 20237 * 0x14 (HTT_H2T_MSG_TYPE_CHAN_CALDATA) 20238 * - SUB_TYPE 20239 * Bits 11:8 20240 * Purpose: T2H: indicates whether target is providing chan cal data 20241 * to the host to store, or requesting that the host 20242 * download previously-stored data. 20243 * H2T: indicates whether the host is providing the requested 20244 * channel cal data, or if it is rejecting the data 20245 * request because it does not have the requested data. 20246 * Value: see HTT_T2H_MSG_CHAN_CALDATA_xxx defs 20247 * - CHKSUM_VALID 20248 * Bit 12 20249 * Purpose: indicates if the checksum field is valid 20250 * value: 20251 * - FRAG 20252 * Bit 19:16 20253 * Purpose: indicates the fragment index for message 20254 * value: 0 for first fragment, 1 for second fragment, ... 20255 * - APPEND 20256 * Bit 20 20257 * Purpose: indicates if this is the last fragment 20258 * value: 0 = final fragment, 1 = more fragments will be appended 20259 * 20260 * channel and payload size field 20261 * - MHZ 20262 * Bits 15:0 20263 * Purpose: indicates the channel primary frequency 20264 * Value: 20265 * - PAYLOAD_SIZE 20266 * Bits 31:16 20267 * Purpose: indicates the bytes of calibration data in payload 20268 * Value: 20269 * 20270 * center frequency field 20271 * - CENTER FREQUENCY 1 20272 * Bits 15:0 20273 * Purpose: indicates the channel center frequency 20274 * Value: channel center frequency, in MHz units 20275 * - CENTER FREQUENCY 2 20276 * Bits 31:16 20277 * Purpose: indicates the secondary channel center frequency, 20278 * only for 11acvht 80plus80 mode 20279 * Value: secondary channel center frequency, in MHz units, if applicable 20280 * 20281 * checksum field 20282 * - CHECK_SUM 20283 * Bits 31:0 20284 * Purpose: check the payload data, it is just for this fragment. 20285 * This is intended for the target to check that the channel 20286 * calibration data returned by the host is the unmodified data 20287 * that was previously provided to the host by the target. 20288 * value: checksum of fragment payload 20289 */ 20290 PREPACK struct htt_chan_caldata_msg { 20291 /* DWORD 0: message info */ 20292 A_UINT32 20293 msg_type: 8, 20294 sub_type: 4 , 20295 chksum_valid: 1, /** 1:valid, 0:invalid */ 20296 reserved1: 3, 20297 frag_idx: 4, /** fragment index for calibration data */ 20298 appending: 1, /** 0: no fragment appending, 20299 * 1: extra fragment appending */ 20300 reserved2: 11; 20301 20302 /* DWORD 1: channel and payload size */ 20303 A_UINT32 20304 mhz: 16, /** primary 20 MHz channel frequency in mhz */ 20305 payload_size: 16; /** unit: bytes */ 20306 20307 /* DWORD 2: center frequency */ 20308 A_UINT32 20309 band_center_freq1: 16, /** Center frequency 1 in MHz */ 20310 band_center_freq2: 16; /** Center frequency 2 in MHz, 20311 * valid only for 11acvht 80plus80 mode */ 20312 20313 /* DWORD 3: check sum */ 20314 A_UINT32 chksum; 20315 20316 /* variable length for calibration data */ 20317 A_UINT32 payload[1/* or more */]; 20318 } POSTPACK; 20319 20320 /* T2H SUBTYPE */ 20321 #define HTT_T2H_MSG_CHAN_CALDATA_REQ 0 20322 #define HTT_T2H_MSG_CHAN_CALDATA_UPLOAD 1 20323 20324 /* H2T SUBTYPE */ 20325 #define HTT_H2T_MSG_CHAN_CALDATA_REJ 0 20326 #define HTT_H2T_MSG_CHAN_CALDATA_DOWNLOAD 1 20327 20328 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_S 8 20329 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_M 0x00000f00 20330 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_GET(_var) \ 20331 (((_var) & HTT_CHAN_CALDATA_MSG_SUB_TYPE_M) >> HTT_CHAN_CALDATA_MSG_SUB_TYPE_S) 20332 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_SET(_var, _val) \ 20333 do { \ 20334 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_SUB_TYPE, _val); \ 20335 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_SUB_TYPE_S)); \ 20336 } while (0) 20337 20338 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_S 12 20339 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_M 0x00001000 20340 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_GET(_var) \ 20341 (((_var) & HTT_CHAN_CALDATA_MSG_CHKSUM_V_M) >> HTT_CHAN_CALDATA_MSG_CHKSUM_V_S) 20342 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_SET(_var, _val) \ 20343 do { \ 20344 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_CHKSUM_V, _val); \ 20345 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_CHKSUM_V_S)); \ 20346 } while (0) 20347 20348 20349 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_S 16 20350 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_M 0x000f0000 20351 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_GET(_var) \ 20352 (((_var) & HTT_CHAN_CALDATA_MSG_FRAG_IDX_M) >> HTT_CHAN_CALDATA_MSG_FRAG_IDX_S) 20353 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_SET(_var, _val) \ 20354 do { \ 20355 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FRAG_IDX, _val); \ 20356 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FRAG_IDX_S)); \ 20357 } while (0) 20358 20359 #define HTT_CHAN_CALDATA_MSG_APPENDING_S 20 20360 #define HTT_CHAN_CALDATA_MSG_APPENDING_M 0x00100000 20361 #define HTT_CHAN_CALDATA_MSG_APPENDING_GET(_var) \ 20362 (((_var) & HTT_CHAN_CALDATA_MSG_APPENDING_M) >> HTT_CHAN_CALDATA_MSG_APPENDING_S) 20363 #define HTT_CHAN_CALDATA_MSG_APPENDING_SET(_var, _val) \ 20364 do { \ 20365 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_APPENDING, _val); \ 20366 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_APPENDING_S)); \ 20367 } while (0) 20368 20369 #define HTT_CHAN_CALDATA_MSG_MHZ_S 0 20370 #define HTT_CHAN_CALDATA_MSG_MHZ_M 0x0000ffff 20371 #define HTT_CHAN_CALDATA_MSG_MHZ_GET(_var) \ 20372 (((_var) & HTT_CHAN_CALDATA_MSG_MHZ_M) >> HTT_CHAN_CALDATA_MSG_MHZ_S) 20373 #define HTT_CHAN_CALDATA_MSG_MHZ_SET(_var, _val) \ 20374 do { \ 20375 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_MHZ, _val); \ 20376 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_MHZ_S)); \ 20377 } while (0) 20378 20379 20380 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_S 16 20381 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_M 0xffff0000 20382 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_GET(_var) \ 20383 (((_var) & HTT_CHAN_CALDATA_MSG_PLD_SIZE_M) >> HTT_CHAN_CALDATA_MSG_PLD_SIZE_S) 20384 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_SET(_var, _val) \ 20385 do { \ 20386 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_PLD_SIZE, _val); \ 20387 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_PLD_SIZE_S)); \ 20388 } while (0) 20389 20390 20391 #define HTT_CHAN_CALDATA_MSG_FREQ1_S 0 20392 #define HTT_CHAN_CALDATA_MSG_FREQ1_M 0x0000ffff 20393 #define HTT_CHAN_CALDATA_MSG_FREQ1_GET(_var) \ 20394 (((_var) & HTT_CHAN_CALDATA_MSG_FREQ1_M) >> HTT_CHAN_CALDATA_MSG_FREQ1_S) 20395 #define HTT_CHAN_CALDATA_MSG_FREQ1_SET(_var, _val) \ 20396 do { \ 20397 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ1, _val); \ 20398 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ1_S)); \ 20399 } while (0) 20400 20401 #define HTT_CHAN_CALDATA_MSG_FREQ2_S 16 20402 #define HTT_CHAN_CALDATA_MSG_FREQ2_M 0xffff0000 20403 #define HTT_CHAN_CALDATA_MSG_FREQ2_GET(_var) \ 20404 (((_var) & HTT_CHAN_CALDATA_MSG_FREQ2_M) >> HTT_CHAN_CALDATA_MSG_FREQ2_S) 20405 #define HTT_CHAN_CALDATA_MSG_FREQ2_SET(_var, _val) \ 20406 do { \ 20407 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ2, _val); \ 20408 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ2_S)); \ 20409 } while (0) 20410 20411 20412 /** 20413 * @brief target -> host FSE CMEM based send 20414 * 20415 * MSG_TYPE => HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND 20416 * 20417 * @details 20418 * HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND message is sent by the target when 20419 * FSE placement in CMEM is enabled. 20420 * 20421 * This message sends the non-secure CMEM base address. 20422 * It will be sent to host in response to message 20423 * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG. 20424 * The message would appear as follows: 20425 * 20426 * |31 24|23 16|15 8|7 0| 20427 * |----------------+----------------+----------------+----------------| 20428 * | reserved | num_entries | msg_type | 20429 * |----------------+----------------+----------------+----------------| 20430 * | base_address_lo | 20431 * |----------------+----------------+----------------+----------------| 20432 * | base_address_hi | 20433 * |-------------------------------------------------------------------| 20434 * 20435 * The message is interpreted as follows: 20436 * dword0 - b'0:7 - msg_type: This will be set to 0x27 20437 * (HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND) 20438 * b'8:15 - number_entries: Indicated the number of entries 20439 * programmed. 20440 * b'16:31 - reserved. 20441 * dword1 - b'0:31 - base_address_lo: Indicate lower 32 bits of 20442 * CMEM base address 20443 * dword2 - b'0:31 - base_address_hi: Indicate upper 32 bits of 20444 * CMEM base address 20445 */ 20446 20447 PREPACK struct htt_cmem_base_send_t { 20448 A_UINT32 msg_type: 8, 20449 num_entries: 8, 20450 reserved: 16; 20451 A_UINT32 base_address_lo; 20452 A_UINT32 base_address_hi; 20453 } POSTPACK; 20454 20455 #define HTT_CMEM_BASE_SEND_SIZE (sizeof(struct htt_cmem_base_send_t)) 20456 20457 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_M 0x0000FF00 20458 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_S 8 20459 20460 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_GET(_var) \ 20461 (((_var) & HTT_CMEM_BASE_SEND_NUM_ENTRIES_M) >> \ 20462 HTT_CMEM_BASE_SEND_NUM_ENTRIES_S) 20463 20464 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_SET(_var, _val) \ 20465 do { \ 20466 HTT_CHECK_SET_VAL(HTT_CMEM_BASE_SEND_NUM_ENTRIES, _val); \ 20467 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ 20468 } while (0) 20469 20470 /** 20471 * @brief - HTT PPDU ID format 20472 * 20473 * @details 20474 * The following field definitions describe the format of the PPDU ID. 20475 * The PPDU ID is truncated to 24 bits for TLVs from TQM. 20476 * 20477 * |31 30|29 24| 23|22 21|20 19|18 17|16 12|11 0| 20478 * +-------------------------------------------------------------------------- 20479 * |rsvd |seq_cmd_type|tqm_cmd|rsvd |seq_idx|mac_id| hwq_ id | sch id | 20480 * +-------------------------------------------------------------------------- 20481 * 20482 * sch id :Schedule command id 20483 * Bits [11 : 0] : monotonically increasing counter to track the 20484 * PPDU posted to a specific transmit queue. 20485 * 20486 * hwq_id: Hardware Queue ID. 20487 * Bits [16 : 12] : Indicates the queue id in the hardware transmit queue. 20488 * 20489 * mac_id: MAC ID 20490 * Bits [18 : 17] : LMAC ID obtained from the whal_mac_struct 20491 * 20492 * seq_idx: Sequence index. 20493 * Bits [21 : 19] : Sequence index indicates all the PPDU belonging to 20494 * a particular TXOP. 20495 * 20496 * tqm_cmd: HWSCH/TQM flag. 20497 * Bit [23] : Always set to 0. 20498 * 20499 * seq_cmd_type: Sequence command type. 20500 * Bit [29 : 24] : Indicates the frame type for the current sequence. 20501 * Refer to enum HTT_STATS_FTYPE for values. 20502 */ 20503 PREPACK struct htt_ppdu_id { 20504 A_UINT32 20505 sch_id: 12, 20506 hwq_id: 5, 20507 mac_id: 2, 20508 seq_idx: 2, 20509 reserved1: 2, 20510 tqm_cmd: 1, 20511 seq_cmd_type: 6, 20512 reserved2: 2; 20513 } POSTPACK; 20514 20515 #define HTT_PPDU_ID_SCH_ID_S 0 20516 #define HTT_PPDU_ID_SCH_ID_M 0x00000fff 20517 #define HTT_PPDU_ID_SCH_ID_GET(_var) \ 20518 (((_var) & HTT_PPDU_ID_SCH_ID_M) >> HTT_PPDU_ID_SCH_ID_S) 20519 20520 #define HTT_PPDU_ID_SCH_ID_SET(_var, _val) \ 20521 do { \ 20522 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SCH_ID, _val); \ 20523 ((_var) |= ((_val) << HTT_PPDU_ID_SCH_ID_S)); \ 20524 } while (0) 20525 20526 #define HTT_PPDU_ID_HWQ_ID_S 12 20527 #define HTT_PPDU_ID_HWQ_ID_M 0x0001f000 20528 #define HTT_PPDU_ID_HWQ_ID_GET(_var) \ 20529 (((_var) & HTT_PPDU_ID_HWQ_ID_M) >> HTT_PPDU_ID_HWQ_ID_S) 20530 20531 #define HTT_PPDU_ID_HWQ_ID_SET(_var, _val) \ 20532 do { \ 20533 HTT_CHECK_SET_VAL(HTT_PPDU_ID_HWQ_ID, _val); \ 20534 ((_var) |= ((_val) << HTT_PPDU_ID_HWQ_ID_S)); \ 20535 } while (0) 20536 20537 #define HTT_PPDU_ID_MAC_ID_S 17 20538 #define HTT_PPDU_ID_MAC_ID_M 0x00060000 20539 #define HTT_PPDU_ID_MAC_ID_GET(_var) \ 20540 (((_var) & HTT_PPDU_ID_MAC_ID_M) >> HTT_PPDU_ID_MAC_ID_S) 20541 20542 #define HTT_PPDU_ID_MAC_ID_SET(_var, _val) \ 20543 do { \ 20544 HTT_CHECK_SET_VAL(HTT_PPDU_ID_MAC_ID, _val); \ 20545 ((_var) |= ((_val) << HTT_PPDU_ID_MAC_ID_S)); \ 20546 } while (0) 20547 20548 #define HTT_PPDU_ID_SEQ_IDX_S 19 20549 #define HTT_PPDU_ID_SEQ_IDX_M 0x00180000 20550 #define HTT_PPDU_ID_SEQ_IDX_GET(_var) \ 20551 (((_var) & HTT_PPDU_ID_SEQ_IDX_M) >> HTT_PPDU_ID_SEQ_IDX_S) 20552 20553 #define HTT_PPDU_ID_SEQ_IDX_SET(_var, _val) \ 20554 do { \ 20555 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_IDX, _val); \ 20556 ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_IDX_S)); \ 20557 } while (0) 20558 20559 #define HTT_PPDU_ID_TQM_CMD_S 23 20560 #define HTT_PPDU_ID_TQM_CMD_M 0x00800000 20561 #define HTT_PPDU_ID_TQM_CMD_GET(_var) \ 20562 (((_var) & HTT_PPDU_ID_TQM_CMD_M) >> HTT_PPDU_ID_TQM_CMD_S) 20563 20564 #define HTT_PPDU_ID_TQM_CMD_SET(_var, _val) \ 20565 do { \ 20566 HTT_CHECK_SET_VAL(HTT_PPDU_ID_TQM_CMD, _val); \ 20567 ((_var) |= ((_val) << HTT_PPDU_ID_TQM_CMD_S)); \ 20568 } while (0) 20569 20570 #define HTT_PPDU_ID_SEQ_CMD_TYPE_S 24 20571 #define HTT_PPDU_ID_SEQ_CMD_TYPE_M 0x3f000000 20572 #define HTT_PPDU_ID_SEQ_CMD_TYPE_GET(_var) \ 20573 (((_var) & HTT_PPDU_ID_SEQ_CMD_TYPE_M) >> HTT_PPDU_ID_SEQ_CMD_TYPE_S) 20574 20575 #define HTT_PPDU_ID_SEQ_CMD_TYPE_SET(_var, _val) \ 20576 do { \ 20577 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_CMD_TYPE, _val); \ 20578 ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_CMD_TYPE_S)); \ 20579 } while (0) 20580 20581 /** 20582 * @brief target -> RX PEER METADATA V0 format 20583 * Host will know the peer metadata version from the wmi_service_ready_ext2 20584 * message from target, and will confirm to the target which peer metadata 20585 * version to use in the wmi_init message. 20586 * 20587 * The following diagram shows the format of the RX PEER METADATA. 20588 * 20589 * |31 24|23 16|15 8|7 0| 20590 * |-----------------------------------------------------------------------| 20591 * | Reserved | VDEV ID | PEER ID | 20592 * |-----------------------------------------------------------------------| 20593 */ 20594 PREPACK struct htt_rx_peer_metadata_v0 { 20595 A_UINT32 20596 peer_id: 16, 20597 vdev_id: 8, 20598 reserved1: 8; 20599 } POSTPACK; 20600 20601 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_S 0 20602 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_M 0x0000ffff 20603 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_GET(_var) \ 20604 (((_var) & HTT_RX_PEER_META_DATA_V0_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V0_PEER_ID_S) 20605 20606 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_SET(_var, _val) \ 20607 do { \ 20608 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_PEER_ID, _val); \ 20609 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_PEER_ID_S)); \ 20610 } while (0) 20611 20612 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_S 16 20613 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_M 0x00ff0000 20614 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_GET(_var) \ 20615 (((_var) & HTT_RX_PEER_META_DATA_V0_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V0_VDEV_ID_S) 20616 20617 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_SET(_var, _val) \ 20618 do { \ 20619 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_VDEV_ID, _val); \ 20620 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_VDEV_ID_S)); \ 20621 } while (0) 20622 20623 /** 20624 * @brief target -> RX PEER METADATA V1 format 20625 * Host will know the peer metadata version from the wmi_service_ready_ext2 20626 * message from target, and will confirm to the target which peer metadata 20627 * version to use in the wmi_init message. 20628 * 20629 * The following diagram shows the format of the RX PEER METADATA V1 format. 20630 * 20631 * |31 29|28 26|25 24|23 16|15 14| 13 |12 0| 20632 * |---------------------------------------------------------------------------| 20633 * |Rsvd2|CHIP ID|LMAC ID|VDEV ID|logical_link_id|ML PEER|SW PEER ID/ML PEER ID| 20634 * |---------------------------------------------------------------------------| 20635 */ 20636 PREPACK struct htt_rx_peer_metadata_v1 { 20637 A_UINT32 20638 peer_id: 13, 20639 ml_peer_valid: 1, 20640 logical_link_id: 2, 20641 vdev_id: 8, 20642 lmac_id: 2, 20643 chip_id: 3, 20644 reserved2: 3; 20645 } POSTPACK; 20646 20647 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_S 0 20648 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_M 0x00001fff 20649 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_GET(_var) \ 20650 (((_var) & HTT_RX_PEER_META_DATA_V1_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1_PEER_ID_S) 20651 20652 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_SET(_var, _val) \ 20653 do { \ 20654 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_PEER_ID, _val); \ 20655 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_PEER_ID_S)); \ 20656 } while (0) 20657 20658 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S 13 20659 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M 0x00002000 20660 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_GET(_var) \ 20661 (((_var) & HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S) 20662 20663 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_SET(_var, _val) \ 20664 do { \ 20665 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID, _val); \ 20666 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S)); \ 20667 } while (0) 20668 20669 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_S 16 20670 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_M 0x00ff0000 20671 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_GET(_var) \ 20672 (((_var) & HTT_RX_PEER_META_DATA_V1_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1_VDEV_ID_S) 20673 20674 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S 14 20675 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M 0x0000c000 20676 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_GET(_var) \ 20677 (((_var) & HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S) 20678 20679 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_SET(_var, _val) \ 20680 do { \ 20681 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID, _val); \ 20682 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)); \ 20683 } while (0) 20684 20685 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_SET(_var, _val) \ 20686 do { \ 20687 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_VDEV_ID, _val); \ 20688 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_VDEV_ID_S)); \ 20689 } while (0) 20690 20691 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_S 24 20692 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_M 0x03000000 20693 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_GET(_var) \ 20694 (((_var) & HTT_RX_PEER_META_DATA_V1_LMAC_ID_M) >> HTT_RX_PEER_META_DATA_V1_LMAC_ID_S) 20695 20696 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_SET(_var, _val) \ 20697 do { \ 20698 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LMAC_ID, _val); \ 20699 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LMAC_ID_S)); \ 20700 } while (0) 20701 20702 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_S 26 20703 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_M 0x1c000000 20704 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_GET(_var) \ 20705 (((_var) & HTT_RX_PEER_META_DATA_V1_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1_CHIP_ID_S) 20706 20707 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_SET(_var, _val) \ 20708 do { \ 20709 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_CHIP_ID, _val); \ 20710 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)); \ 20711 } while (0) 20712 20713 /** 20714 * @brief target -> RX PEER METADATA V1A format 20715 * Host will know the peer metadata version from the wmi_service_ready_ext2 20716 * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, 20717 * and will confirm to the target which peer metadata version to use in the 20718 * wmi_init message. 20719 * 20720 * The following diagram shows the format of the RX PEER METADATA V1A format. 20721 * 20722 * |31 29|28 26|25 22|21 14| 13 |12 0| 20723 * |-------------------------------------------------------------------| 20724 * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| 20725 * |-------------------------------------------------------------------| 20726 */ 20727 PREPACK struct htt_rx_peer_metadata_v1a { 20728 A_UINT32 20729 peer_id: 13, 20730 ml_peer_valid: 1, 20731 vdev_id: 8, 20732 logical_link_id: 4, 20733 chip_id: 3, 20734 qdata_refill: 1, 20735 reserved2: 2; 20736 } POSTPACK; 20737 20738 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 20739 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_M 0x00001fff 20740 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_GET(_var) \ 20741 (((_var) & HTT_RX_PEER_META_DATA_V1A_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1A_PEER_ID_S) 20742 20743 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_SET(_var, _val) \ 20744 do { \ 20745 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PEER_ID, _val); \ 20746 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)); \ 20747 } while (0) 20748 20749 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S 13 20750 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M 0x00002000 20751 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_GET(_var) \ 20752 (((_var) & HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S) 20753 20754 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_SET(_var, _val) \ 20755 do { \ 20756 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID, _val); \ 20757 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)); \ 20758 } while (0) 20759 20760 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S 14 20761 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M 0x003fc000 20762 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_GET(_var) \ 20763 (((_var) & HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S) 20764 20765 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_SET(_var, _val) \ 20766 do { \ 20767 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_VDEV_ID, _val); \ 20768 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)); \ 20769 } while (0) 20770 20771 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S 22 20772 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M 0x03C00000 20773 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_GET(_var) \ 20774 (((_var) & HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S) 20775 20776 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_SET(_var, _val) \ 20777 do { \ 20778 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID, _val); \ 20779 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)); \ 20780 } while (0) 20781 20782 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S 26 20783 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M 0x1c000000 20784 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_GET(_var) \ 20785 (((_var) & HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S) 20786 20787 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_SET(_var, _val) \ 20788 do { \ 20789 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_CHIP_ID, _val); \ 20790 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)); \ 20791 } while (0) 20792 20793 #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S 29 20794 #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_M 0x20000000 20795 #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_GET(_var) \ 20796 (((_var) & HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_M) >> HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S) 20797 20798 #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_SET(_var, _val) \ 20799 do { \ 20800 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL, _val); \ 20801 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S)); \ 20802 } while (0) 20803 20804 20805 /** 20806 * @brief target -> RX PEER METADATA V1B format 20807 * Host will know the peer metadata version from the wmi_service_ready_ext2 20808 * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, 20809 * and will confirm to the target which peer metadata version to use in the 20810 * wmi_init message. 20811 * 20812 * The following diagram shows the format of the RX PEER METADATA V1B format. 20813 * 20814 * |31 29|28 26|25 22|21 14| 13 |12 0| 20815 * |--------------------------------------------------------------| 20816 * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| 20817 * |--------------------------------------------------------------| 20818 */ 20819 PREPACK struct htt_rx_peer_metadata_v1b { 20820 A_UINT32 20821 peer_id: 13, 20822 ml_peer_valid: 1, 20823 vdev_id: 8, 20824 hw_link_id: 4, 20825 chip_id: 3, 20826 reserved2: 3; 20827 } POSTPACK; 20828 20829 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 20830 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_M 0x00001fff 20831 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_GET(_var) \ 20832 (((_var) & HTT_RX_PEER_META_DATA_V1B_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1B_PEER_ID_S) 20833 20834 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_SET(_var, _val) \ 20835 do { \ 20836 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_PEER_ID, _val); \ 20837 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)); \ 20838 } while (0) 20839 20840 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S 13 20841 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M 0x00002000 20842 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_GET(_var) \ 20843 (((_var) & HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S) 20844 20845 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_SET(_var, _val) \ 20846 do { \ 20847 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID, _val); \ 20848 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)); \ 20849 } while (0) 20850 20851 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S 14 20852 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M 0x003fc000 20853 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_GET(_var) \ 20854 (((_var) & HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S) 20855 20856 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_SET(_var, _val) \ 20857 do { \ 20858 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_VDEV_ID, _val); \ 20859 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)); \ 20860 } while (0) 20861 20862 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S 22 20863 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M 0x03C00000 20864 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_GET(_var) \ 20865 (((_var) & HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S) 20866 20867 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_SET(_var, _val) \ 20868 do { \ 20869 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID, _val); \ 20870 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)); \ 20871 } while (0) 20872 20873 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S 26 20874 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M 0x1c000000 20875 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_GET(_var) \ 20876 (((_var) & HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S) 20877 20878 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_SET(_var, _val) \ 20879 do { \ 20880 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_CHIP_ID, _val); \ 20881 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ 20882 } while (0) 20883 20884 /* generic variables for masks and shifts for various fields */ 20885 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; 20886 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; 20887 20888 extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_S; 20889 extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_M; 20890 20891 /* generic function pointers to get/set values from rx peer metadata v0/v1/v1a/v1b */ 20892 extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_ID_GET) (A_UINT32 var); 20893 extern void (*HTT_RX_PEER_META_DATA_PEER_ID_SET) (A_UINT32 *var, A_UINT32 val); 20894 20895 extern A_UINT32 (*HTT_RX_PEER_META_DATA_VDEV_ID_GET) (A_UINT32 var); 20896 extern void (*HTT_RX_PEER_META_DATA_VDEV_ID_SET) (A_UINT32 *var, A_UINT32 val); 20897 20898 extern A_UINT32 (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_GET) (A_UINT32 var); 20899 extern void (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_SET) (A_UINT32 *var, A_UINT32 val); 20900 20901 extern A_UINT32 (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_GET) (A_UINT32 var); 20902 extern void (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); 20903 20904 extern A_UINT32 (*HTT_RX_PEER_META_DATA_LMAC_ID_GET) (A_UINT32 var); 20905 extern void (*HTT_RX_PEER_META_DATA_LMAC_ID_SET) (A_UINT32 *var, A_UINT32 val); 20906 20907 extern A_UINT32 (*HTT_RX_PEER_META_DATA_CHIP_ID_GET) (A_UINT32 var); 20908 extern void (*HTT_RX_PEER_META_DATA_CHIP_ID_SET) (A_UINT32 *var, A_UINT32 val); 20909 20910 extern A_UINT32 (*HTT_RX_PEER_META_DATA_HW_LINK_ID_GET) (A_UINT32 var); 20911 extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); 20912 20913 extern A_UINT32 (*HTT_RX_PEER_META_DATA_QDATA_REFILL_GET) (A_UINT32 var); 20914 extern void (*HTT_RX_PEER_META_DATA_QDATA_REFILL_SET) (A_UINT32 *var, A_UINT32 val); 20915 20916 20917 /* 20918 * In some systems, the host SW wants to specify priorities between 20919 * different MSDU / flow queues within the same peer-TID. 20920 * The below enums are used for the host to identify to the target 20921 * which MSDU queue's priority it wants to adjust. 20922 */ 20923 20924 /* 20925 * The MSDUQ index describe index of TCL HW, where each index is 20926 * used for queuing particular types of MSDUs. 20927 * The different MSDU queue types are defined in HTT_MSDU_QTYPE. 20928 */ 20929 enum HTT_MSDUQ_INDEX { 20930 HTT_MSDUQ_INDEX_NON_UDP, /* NON UDP MSDUQ index */ 20931 HTT_MSDUQ_INDEX_UDP, /* UDP MSDUQ index */ 20932 20933 HTT_MSDUQ_INDEX_CUSTOM_PRIO_0, /* Latency priority 0 index */ 20934 HTT_MSDUQ_INDEX_CUSTOM_PRIO_1, /* Latency priority 1 index */ 20935 20936 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_0, /* High num TID cases/ MLO dedicate link cases */ 20937 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_1, /* High num TID cases/ MLO dedicate link cases */ 20938 20939 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_2, /* High num TID cases/ MLO dedicate link cases */ 20940 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_3, /* High num TID cases/ MLO dedicate link cases */ 20941 20942 HTT_MSDUQ_MAX_INDEX, 20943 }; 20944 20945 /* MSDU qtype definition */ 20946 enum HTT_MSDU_QTYPE { 20947 /* 20948 * The LATENCY_CRIT_0 and LATENCY_CRIT_1 queue types don't have a fixed 20949 * relative priority. Instead, the relative priority of CRIT_0 versus 20950 * CRIT_1 is controlled by the FW, through the configuration parameters 20951 * it applies to the queues. 20952 */ 20953 HTT_MSDU_QTYPE_LATENCY_CRIT_0, /* Specified MSDUQ index used for latency critical 0 */ 20954 HTT_MSDU_QTYPE_LATENCY_CRIT_1, /* Specified MSDUQ index used for latency critical 1 */ 20955 HTT_MSDU_QTYPE_UDP, /* Specifies MSDUQ index used for UDP flow */ 20956 HTT_MSDU_QTYPE_NON_UDP, /* Specifies MSDUQ index used for non-udp flow */ 20957 HTT_MSDU_QTYPE_HOL, /* Specified MSDUQ index used for Head of Line */ 20958 HTT_MSDU_QTYPE_USER_SPECIFIED, /* Specifies MSDUQ index used for advertising changeable flow type */ 20959 HTT_MSDU_QTYPE_HI_PRIO, /* Specifies MSDUQ index used for high priority flow type */ 20960 HTT_MSDU_QTYPE_LO_PRIO, /* Specifies MSDUQ index used for low priority flow type */ 20961 20962 20963 /* New MSDU_QTYPE should be added above this line */ 20964 /* 20965 * Below QTYPE_MAX will increase if additional QTYPEs are defined 20966 * in the future. Hence HTT_MSDU_QTYPE_MAX can't be used in 20967 * any host/target message definitions. The QTYPE_MAX value can 20968 * only be used internally within the host or within the target. 20969 * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX 20970 * it must regard the unexpected value as a default qtype value, 20971 * or ignore it. 20972 */ 20973 HTT_MSDU_QTYPE_MAX, 20974 HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */ 20975 }; 20976 20977 enum HTT_MSDUQ_LEGACY_FLOW_INDEX { 20978 HTT_MSDUQ_LEGACY_HI_PRI_FLOW_INDEX = 0, 20979 HTT_MSDUQ_LEGACY_LO_PRI_FLOW_INDEX = 1, 20980 HTT_MSDUQ_LEGACY_UDP_FLOW_INDEX = 2, 20981 HTT_MSDUQ_LEGACY_NON_UDP_FLOW_INDEX = 3, 20982 }; 20983 20984 /** 20985 * @brief target -> host mlo timestamp offset indication 20986 * 20987 * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 20988 * 20989 * @details 20990 * The following field definitions describe the format of the HTT target 20991 * to host mlo timestamp offset indication message. 20992 * 20993 * 20994 * |31 16|15 12|11 10|9 8|7 0 | 20995 * |----------------------------------------------------------------------| 20996 * | mac_clk_freq_mhz | rsvd |chip_id|pdev_id| msg type | 20997 * |----------------------------------------------------------------------| 20998 * | Sync time stamp lo in us | 20999 * |----------------------------------------------------------------------| 21000 * | Sync time stamp hi in us | 21001 * |----------------------------------------------------------------------| 21002 * | mlo time stamp offset lo in us | 21003 * |----------------------------------------------------------------------| 21004 * | mlo time stamp offset hi in us | 21005 * |----------------------------------------------------------------------| 21006 * | mlo time stamp offset clocks in clock ticks | 21007 * |----------------------------------------------------------------------| 21008 * |31 26|25 16|15 0 | 21009 * |rsvd2 | mlo time stamp | mlo time stamp compensation in us | 21010 * | | compensation in clks | | 21011 * |----------------------------------------------------------------------| 21012 * |31 22|21 0 | 21013 * | rsvd 3 | mlo time stamp comp timer period | 21014 * |----------------------------------------------------------------------| 21015 * The message is interpreted as follows: 21016 * 21017 * dword0 - b'0:7 - msg_type: This will be set to 21018 * HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 21019 * value: 0x28 21020 * 21021 * dword0 - b'9:8 - pdev_id 21022 * 21023 * dword0 - b'11:10 - chip_id 21024 * 21025 * dword0 - b'15:12 - rsvd1: Reserved for future use 21026 * 21027 * dword0 - b'31:16 - mac clock frequency of the mac HW block in MHz 21028 * 21029 * dword1 - b'31:0 - lower 32 bits of the WLAN global time stamp (in us) at 21030 * which last sync interrupt was received 21031 * 21032 * dword2 - b'31:0 - upper 32 bits of the WLAN global time stamp (in us) at 21033 * which last sync interrupt was received 21034 * 21035 * dword3 - b'31:0 - lower 32 bits of the MLO time stamp offset in us 21036 * 21037 * dword4 - b'31:0 - upper 32 bits of the MLO time stamp offset in us 21038 * 21039 * dword5 - b'31:0 - MLO time stamp offset in clock ticks for sub us 21040 * 21041 * dword6 - b'15:0 - MLO time stamp compensation applied in us 21042 * 21043 * dword6 - b'25:16 - MLO time stamp compensation applied in clock ticks 21044 * for sub us resolution 21045 * 21046 * dword6 - b'31:26 - rsvd2: Reserved for future use 21047 * 21048 * dword7 - b'21:0 - period of MLO compensation timer at which compensation 21049 * is applied, in us 21050 * 21051 * dword7 - b'31:22 - rsvd3: Reserved for future use 21052 */ 21053 21054 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M 0x000000FF 21055 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S 0 21056 21057 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M 0x00000300 21058 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S 8 21059 21060 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M 0x00000C00 21061 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S 10 21062 21063 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M 0xFFFF0000 21064 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S 16 21065 21066 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M 0x0000FFFF 21067 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S 0 21068 21069 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M 0x03FF0000 21070 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S 16 21071 21072 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M 0x003FFFFF 21073 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S 0 21074 21075 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_GET(_var) \ 21076 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S) 21077 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_SET(_var, _val) \ 21078 do { \ 21079 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE, _val); \ 21080 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S)); \ 21081 } while (0) 21082 21083 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_GET(_var) \ 21084 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S) 21085 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_SET(_var, _val) \ 21086 do { \ 21087 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID, _val); \ 21088 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S)); \ 21089 } while (0) 21090 21091 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_GET(_var) \ 21092 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S) 21093 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_SET(_var, _val) \ 21094 do { \ 21095 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID, _val); \ 21096 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S)); \ 21097 } while (0) 21098 21099 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_GET(_var) \ 21100 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M) >> \ 21101 HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S) 21102 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_SET(_var, _val) \ 21103 do { \ 21104 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ, _val); \ 21105 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S)); \ 21106 } while (0) 21107 21108 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_GET(_var) \ 21109 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M) >> \ 21110 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S) 21111 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_SET(_var, _val) \ 21112 do { \ 21113 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US, _val); \ 21114 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S)); \ 21115 } while (0) 21116 21117 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_GET(_var) \ 21118 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M) >> \ 21119 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S) 21120 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_SET(_var, _val) \ 21121 do { \ 21122 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS, _val); \ 21123 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S)); \ 21124 } while (0) 21125 21126 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_GET(_var) \ 21127 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M) >> \ 21128 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S) 21129 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_SET(_var, _val) \ 21130 do { \ 21131 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US, _val); \ 21132 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S)); \ 21133 } while (0) 21134 21135 typedef struct { 21136 A_UINT32 msg_type: 8, /* bits 7:0 */ 21137 pdev_id: 2, /* bits 9:8 */ 21138 chip_id: 2, /* bits 11:10 */ 21139 reserved1: 4, /* bits 15:12 */ 21140 mac_clk_freq_mhz: 16; /* bits 31:16 */ 21141 A_UINT32 sync_timestamp_lo_us; 21142 A_UINT32 sync_timestamp_hi_us; 21143 A_UINT32 mlo_timestamp_offset_lo_us; 21144 A_UINT32 mlo_timestamp_offset_hi_us; 21145 A_UINT32 mlo_timestamp_offset_clks; 21146 A_UINT32 mlo_timestamp_comp_us: 16, /* bits 15:0 */ 21147 mlo_timestamp_comp_clks: 10, /* bits 25:16 */ 21148 reserved2: 6; /* bits 31:26 */ 21149 A_UINT32 mlo_timestamp_comp_timer_period_us: 22, /* bits 21:0 */ 21150 reserved3: 10; /* bits 31:22 */ 21151 } htt_t2h_mlo_offset_ind_t; 21152 21153 /* 21154 * @brief target -> host VDEV TX RX STATS 21155 * 21156 * MSG_TYPE => HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND 21157 * 21158 * @details 21159 * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message is sent by the target 21160 * every periodic interval programmed in HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG. 21161 * After the host sends an initial HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG, 21162 * this HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message will be sent 21163 * periodically by target even in the absence of any further HTT request 21164 * messages from host. 21165 * 21166 * The message is formatted as follows: 21167 * 21168 * |31 16|15 8|7 0| 21169 * |---------------------------------+----------------+----------------| 21170 * | payload_size | pdev_id | msg_type | 21171 * |---------------------------------+----------------+----------------| 21172 * | reserved0 | 21173 * |-------------------------------------------------------------------| 21174 * | reserved1 | 21175 * |-------------------------------------------------------------------| 21176 * | reserved2 | 21177 * |-------------------------------------------------------------------| 21178 * | | 21179 * | VDEV specific Tx Rx stats info | 21180 * | | 21181 * |-------------------------------------------------------------------| 21182 * 21183 * The message is interpreted as follows: 21184 * dword0 - b'0:7 - msg_type: This will be set to 0x2c 21185 * (HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND) 21186 * b'8:15 - pdev_id 21187 * b'16:31 - size in bytes of the payload that follows the 16-byte 21188 * message header fields (msg_type through reserved2) 21189 * dword1 - b'0:31 - reserved0. 21190 * dword2 - b'0:31 - reserved1. 21191 * dword3 - b'0:31 - reserved2. 21192 */ 21193 typedef struct { 21194 A_UINT32 msg_type: 8, 21195 pdev_id: 8, 21196 payload_size: 16; 21197 A_UINT32 reserved0; 21198 A_UINT32 reserved1; 21199 A_UINT32 reserved2; 21200 } htt_t2h_vdevs_txrx_stats_periodic_hdr_t; 21201 21202 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_HDR_SIZE 16 21203 21204 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M 0x0000FF00 21205 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S 8 21206 21207 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ 21208 (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S) 21209 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ 21210 do { \ 21211 HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID, _val); \ 21212 ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S)); \ 21213 } while (0) 21214 21215 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M 0xFFFF0000 21216 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S 16 21217 21218 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_GET(_var) \ 21219 (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S) 21220 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_SET(_var, _val) \ 21221 do { \ 21222 HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE, _val); \ 21223 ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S)); \ 21224 } while (0) 21225 21226 /* SOC related stats */ 21227 typedef struct { 21228 htt_tlv_hdr_t tlv_hdr; 21229 21230 /* When TQM is not able to find the peers during Tx, then it drops the packets 21231 * This can be due to either the peer is deleted or deletion is ongoing 21232 * */ 21233 A_UINT32 inv_peers_msdu_drop_count_lo; 21234 A_UINT32 inv_peers_msdu_drop_count_hi; 21235 } htt_stats_soc_txrx_stats_common_tlv; 21236 /* preserve old name alias for new name consistent with the tag name */ 21237 typedef htt_stats_soc_txrx_stats_common_tlv htt_t2h_soc_txrx_stats_common_tlv; 21238 21239 /* VDEV HW Tx/Rx stats */ 21240 typedef struct { 21241 htt_tlv_hdr_t tlv_hdr; 21242 A_UINT32 vdev_id; 21243 21244 /* Rx msdu byte cnt */ 21245 A_UINT32 rx_msdu_byte_cnt_lo; 21246 A_UINT32 rx_msdu_byte_cnt_hi; 21247 21248 /* Rx msdu cnt */ 21249 A_UINT32 rx_msdu_cnt_lo; 21250 A_UINT32 rx_msdu_cnt_hi; 21251 21252 /* tx msdu byte cnt */ 21253 A_UINT32 tx_msdu_byte_cnt_lo; 21254 A_UINT32 tx_msdu_byte_cnt_hi; 21255 21256 /* tx msdu cnt */ 21257 A_UINT32 tx_msdu_cnt_lo; 21258 A_UINT32 tx_msdu_cnt_hi; 21259 21260 /* tx excessive retry discarded msdu cnt */ 21261 A_UINT32 tx_msdu_excessive_retry_discard_cnt_lo; 21262 A_UINT32 tx_msdu_excessive_retry_discard_cnt_hi; 21263 21264 /* TX congestion ctrl msdu drop cnt */ 21265 A_UINT32 tx_msdu_cong_ctrl_drop_cnt_lo; 21266 A_UINT32 tx_msdu_cong_ctrl_drop_cnt_hi; 21267 21268 /* discarded tx msdus cnt coz of time to live expiry */ 21269 A_UINT32 tx_msdu_ttl_expire_drop_cnt_lo; 21270 A_UINT32 tx_msdu_ttl_expire_drop_cnt_hi; 21271 21272 /* tx excessive retry discarded msdu byte cnt */ 21273 A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_lo; 21274 A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_hi; 21275 21276 /* TX congestion ctrl msdu drop byte cnt */ 21277 A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_lo; 21278 A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_hi; 21279 21280 /* discarded tx msdus byte cnt coz of time to live expiry */ 21281 A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_lo; 21282 A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_hi; 21283 21284 /* TQM bypass frame cnt */ 21285 A_UINT32 tqm_bypass_frame_cnt_lo; 21286 A_UINT32 tqm_bypass_frame_cnt_hi; 21287 21288 /* TQM bypass byte cnt */ 21289 A_UINT32 tqm_bypass_byte_cnt_lo; 21290 A_UINT32 tqm_bypass_byte_cnt_hi; 21291 } htt_stats_vdev_txrx_stats_hw_stats_tlv; 21292 /* preserve old name alias for new name consistent with the tag name */ 21293 typedef htt_stats_vdev_txrx_stats_hw_stats_tlv 21294 htt_t2h_vdev_txrx_stats_hw_stats_tlv; 21295 21296 /* 21297 * MSG_TYPE => HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF 21298 * 21299 * @details 21300 * The SAWF_DEF_QUEUES_MAP_REPORT_CONF message is sent by the target in 21301 * response to a SAWF_DEF_QUEUES_MAP_REPORT_REQ from the host. 21302 * The SAWF_DEF_QUEUES_MAP_REPORT_CONF will show which service class 21303 * the default MSDU queues of each of the specified TIDs for the peer 21304 * specified in the SAWF_DEF_QUEUES_MAP_REPORT_REQ message are linked to. 21305 * If the default MSDU queues of a given TID within the peer are not linked 21306 * to a service class, the svc_class_id field for that TID will have a 21307 * 0xff HTT_SAWF_SVC_CLASS_INVALID_ID value to indicate the default MSDU 21308 * queues for that TID are not mapped to any service class. 21309 * 21310 * |31 16|15 8|7 0| 21311 * |------------------------------+--------------+--------------| 21312 * | peer ID | reserved | msg type | 21313 * |------------------------------+--------------+------+-------| 21314 * | reserved | svc class ID | TID | 21315 * |------------------------------------------------------------| 21316 * ... 21317 * |------------------------------------------------------------| 21318 * | reserved | svc class ID | TID | 21319 * |------------------------------------------------------------| 21320 * Header fields: 21321 * dword0 - b'7:0 - msg_type: This will be set to 21322 * 0x2d (HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF) 21323 * b'31:16 - peer ID 21324 * dword1 - b'7:0 - TID 21325 * b'15:8 - svc class ID 21326 * (dword2, etc. same format as dword1) 21327 */ 21328 21329 #define HTT_SAWF_SVC_CLASS_INVALID_ID 0xff 21330 21331 PREPACK struct htt_t2h_sawf_def_queues_map_report_conf { 21332 A_UINT32 msg_type :8, 21333 reserved0 :8, 21334 peer_id :16; 21335 struct { 21336 A_UINT32 tid :8, 21337 svc_class_id :8, 21338 reserved1 :16; 21339 } tid_reports[1/*or more*/]; 21340 } POSTPACK; 21341 21342 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_HDR_BYTES 4 /* msg_type, peer_id */ 21343 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_ELEM_BYTES 4 /* TID, svc_class_id */ 21344 21345 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M 0xFFFF0000 21346 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S 16 21347 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_GET(_var) \ 21348 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M) >> \ 21349 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S) 21350 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_SET(_var, _val) \ 21351 do { \ 21352 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID, _val); \ 21353 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S)); \ 21354 } while (0) 21355 21356 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M 0x000000FF 21357 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S 0 21358 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_GET(_var) \ 21359 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M) >> \ 21360 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S) 21361 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_SET(_var, _val) \ 21362 do { \ 21363 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID, _val); \ 21364 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S)); \ 21365 } while (0) 21366 21367 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M 0x0000FF00 21368 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S 8 21369 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_GET(_var) \ 21370 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M) >> \ 21371 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S) 21372 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_SET(_var, _val) \ 21373 do { \ 21374 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID, _val); \ 21375 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S)); \ 21376 } while (0) 21377 21378 21379 /* 21380 * MSG_TYPE => HTT_T2H_SAWF_MSDUQ_INFO_IND 21381 * 21382 * @details 21383 * When SAWF is enabled and a flow is mapped to a policy during the traffic 21384 * flow if the flow is seen the associated service class is conveyed to the 21385 * target via TCL Data Command. Target on the other hand internally creates the 21386 * MSDUQ. Once the target creates the MSDUQ the target sends the information 21387 * of the newly created MSDUQ and some other identifiers to uniquely identity 21388 * the newly created MSDUQ 21389 * 21390 * |31 27| 24|23 16|15|14 11|10|9 8|7 4|3 0| 21391 * |------------------------------+------------------------+--------------| 21392 * | peer ID | HTT qtype | msg type | 21393 * |---------------------------------+--------------+--+---+-------+------| 21394 * | reserved |AST list index|FO|WC | HLOS | remap| 21395 * | | | | | TID | TID | 21396 * |---------------------+------------------------------------------------| 21397 * | reserved1 | tgt_opaque_id | 21398 * |---------------------+------------------------------------------------| 21399 * 21400 * Header fields: 21401 * 21402 * dword0 - b'7:0 - msg_type: This will be set to 21403 * 0x2e (HTT_T2H_SAWF_MSDUQ_INFO_IND) 21404 * b'15:8 - HTT qtype 21405 * b'31:16 - peer ID 21406 * 21407 * dword1 - b'3:0 - remap TID, as assigned in firmware 21408 * b'7:4 - HLOS TID, as sent by host in TCL Data Command 21409 * hlos_tid : Common to Lithium and Beryllium 21410 * b'9:8 - who_classify_info_sel (WC), as sent by host in 21411 * TCL Data Command : Beryllium 21412 * b10 - flow_override (FO), as sent by host in 21413 * TCL Data Command: Beryllium 21414 * b11:14 - ast_list_idx 21415 * Array index into the list of extension AST entries 21416 * (not the actual AST 16-bit index). 21417 * The ast_list_idx is one-based, with the following 21418 * range of values: 21419 * - legacy targets supporting 16 user-defined 21420 * MSDU queues: 1-2 21421 * - legacy targets supporting 48 user-defined 21422 * MSDU queues: 1-6 21423 * - new targets: 0 (peer_id is used instead) 21424 * Note that since ast_list_idx is one-based, 21425 * the host will need to subtract 1 to use it as an 21426 * index into a list of extension AST entries. 21427 * b15:31 - reserved 21428 * 21429 * dword2 - b'23:0 - tgt_opaque_id Opaque Tx flow number which is a 21430 * unique MSDUQ id in firmware 21431 * b'24:31 - reserved1 21432 */ 21433 PREPACK struct htt_t2h_sawf_msduq_event { 21434 A_UINT32 msg_type : 8, 21435 htt_qtype : 8, 21436 peer_id :16; 21437 21438 A_UINT32 remap_tid : 4, 21439 hlos_tid : 4, 21440 who_classify_info_sel : 2, 21441 flow_override : 1, 21442 ast_list_idx : 4, 21443 reserved :17; 21444 21445 A_UINT32 tgt_opaque_id :24, 21446 reserved1 : 8; 21447 } POSTPACK; 21448 21449 #define HTT_SAWF_MSDUQ_INFO_SIZE (sizeof(struct htt_t2h_sawf_msduq_event)) 21450 21451 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M 0x0000FF00 21452 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S 8 21453 21454 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_GET(_var) \ 21455 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M) >> \ 21456 HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S) 21457 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_SET(_var, _val) \ 21458 do { \ 21459 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE, _val); \ 21460 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S));\ 21461 } while (0) 21462 21463 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M 0xFFFF0000 21464 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S 16 21465 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_GET(_var) \ 21466 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M) >> \ 21467 HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S) 21468 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_SET(_var, _val) \ 21469 do { \ 21470 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID, _val); \ 21471 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S)); \ 21472 } while (0) 21473 21474 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M 0x0000000F 21475 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S 0 21476 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_GET(_var) \ 21477 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M) >> \ 21478 HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S) 21479 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_SET(_var, _val) \ 21480 do { \ 21481 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID, _val); \ 21482 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S)); \ 21483 } while (0) 21484 21485 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M 0x000000F0 21486 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S 4 21487 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_GET(_var) \ 21488 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M) >> \ 21489 HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S) 21490 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_SET(_var, _val) \ 21491 do { \ 21492 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID, _val); \ 21493 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S)); \ 21494 } while (0) 21495 21496 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M 0x00000300 21497 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S 8 21498 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_GET(_var) \ 21499 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M) >> \ 21500 HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S) 21501 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_SET(_var, _val) \ 21502 do { \ 21503 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL, _val); \ 21504 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S)); \ 21505 } while (0) 21506 21507 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M 0x00000400 21508 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S 10 21509 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_GET(_var) \ 21510 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M) >> \ 21511 HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S) 21512 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_SET(_var, _val) \ 21513 do { \ 21514 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE, _val); \ 21515 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S)); \ 21516 } while (0) 21517 21518 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M 0x00007800 21519 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S 11 21520 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_GET(_var) \ 21521 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M) >> \ 21522 HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S) 21523 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_SET(_var, _val) \ 21524 do { \ 21525 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX, _val); \ 21526 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S)); \ 21527 } while (0) 21528 21529 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_M 0x00FFFFFF 21530 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S 0 21531 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_GET(_var) \ 21532 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_M) >> \ 21533 HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S) 21534 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_SET(_var, _val) \ 21535 do { \ 21536 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID, _val); \ 21537 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S)); \ 21538 } while (0) 21539 21540 21541 /** 21542 * @brief target -> PPDU id format indication 21543 * 21544 * MSG_TYPE => HTT_T2H_PPDU_ID_FMT_IND 21545 * 21546 * @details 21547 * The following field definitions describe the format of the HTT target 21548 * to host PPDU ID format indication message. 21549 * hwsch_cmd_id :- A number per ring, increases by one with each HWSCH command. 21550 * ring_id :- HWSCH ring id in which this PPDU was enqueued. 21551 * seq_idx :- Sequence control index of this PPDU. 21552 * link_id :- HW link ID of the link in which the PPDU was enqueued. 21553 * seq_cmd_type:- WHAL_TXSEND_FTYPE (SU Data, MU Data, SGEN frames etc.) 21554 * tqm_cmd:- 21555 * 21556 * |31 27|26 22|21 17| 16 |15 11|10 8|7 6|5 1| 0 | 21557 * |--------------------------------------------------+------------------------| 21558 * | rsvd0 | msg type | 21559 * |-----+----------+----------+---------+-----+----------+----------+---------| 21560 * |rsvd2|ring_id OF|ring_id NB|ring_id V|rsvd1|cmd_id OF |cmd_id NB |cmd_id V | 21561 * |-----+----------+----------+---------+-----+----------+----------+---------| 21562 * |rsvd4|link_id OF|link_id NB|link_id V|rsvd3|seq_idx OF|seq_idx NB|seq_idx V| 21563 * |-----+----------+----------+---------+-----+----------+----------+---------| 21564 * |rsvd6|tqm_cmd OF|tqm_cmd NB|tqm_cmd V|rsvd5|seq_cmd OF|seq_cmd NB|seq_cmd V| 21565 * |-----+----------+----------+---------+-----+----------+----------+---------| 21566 * |rsvd8| crc OF | crc NB | crc V |rsvd7|mac_id OF |mac_id NB |mac_id V | 21567 * |-----+----------+----------+---------+-----+----------+----------+---------| 21568 * Where: OF = bit offset, NB = number of bits, V = valid 21569 * The message is interpreted as follows: 21570 * 21571 * dword0 - b'7:0 - msg_type: This will be set to 21572 * HTT_T2H_PPDU_ID_FMT_IND 21573 * value: 0x30 21574 * 21575 * dword0 - b'31:8 - reserved 21576 * 21577 * dword1 - b'0:0 - field to indicate whether hwsch_cmd_id is valid or not 21578 * 21579 * dword1 - b'5:1 - number of bits in hwsch_cmd_id 21580 * 21581 * dword1 - b'10:6 - offset of hwsch_cmd_id (in number of bits) 21582 * 21583 * dword1 - b'15:11 - reserved for future use 21584 * 21585 * dword1 - b'16:16 - field to indicate whether ring_id is valid or not 21586 * 21587 * dword1 - b'21:17 - number of bits in ring_id 21588 * 21589 * dword1 - b'26:22 - offset of ring_id (in number of bits) 21590 * 21591 * dword1 - b'31:27 - reserved for future use 21592 * 21593 * dword2 - b'0:0 - field to indicate whether sequence index is valid or not 21594 * 21595 * dword2 - b'5:1 - number of bits in sequence index 21596 * 21597 * dword2 - b'10:6 - offset of sequence index (in number of bits) 21598 * 21599 * dword2 - b'15:11 - reserved for future use 21600 * 21601 * dword2 - b'16:16 - field to indicate whether link_id is valid or not 21602 * 21603 * dword2 - b'21:17 - number of bits in link_id 21604 * 21605 * dword2 - b'26:22 - offset of link_id (in number of bits) 21606 * 21607 * dword2 - b'31:27 - reserved for future use 21608 * 21609 * dword3 - b'0:0 - field to indicate whether seq_cmd_type is valid or not 21610 * 21611 * dword3 - b'5:1 - number of bits in seq_cmd_type 21612 * 21613 * dword3 - b'10:6 - offset of seq_cmd_type (in number of bits) 21614 * 21615 * dword3 - b'15:11 - reserved for future use 21616 * 21617 * dword3 - b'16:16 - field to indicate whether tqm_cmd is valid or not 21618 * 21619 * dword3 - b'21:17 - number of bits in tqm_cmd 21620 * 21621 * dword3 - b'26:22 - offset of tqm_cmd (in number of bits) 21622 * 21623 * dword3 - b'31:27 - reserved for future use 21624 * 21625 * dword4 - b'0:0 - field to indicate whether mac_id is valid or not 21626 * 21627 * dword4 - b'5:1 - number of bits in mac_id 21628 * 21629 * dword4 - b'10:6 - offset of mac_id (in number of bits) 21630 * 21631 * dword4 - b'15:11 - reserved for future use 21632 * 21633 * dword4 - b'16:16 - field to indicate whether crc is valid or not 21634 * 21635 * dword4 - b'21:17 - number of bits in crc 21636 * 21637 * dword4 - b'26:22 - offset of crc (in number of bits) 21638 * 21639 * dword4 - b'31:27 - reserved for future use 21640 * 21641 */ 21642 21643 #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M 0x00000001 21644 #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S 0 21645 21646 #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M 0x0000003E 21647 #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S 1 21648 21649 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M 0x000007C0 21650 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S 6 21651 21652 #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M 0x00010000 21653 #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S 16 21654 21655 #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M 0x003E0000 21656 #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S 17 21657 21658 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M 0x07C00000 21659 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S 22 21660 21661 21662 /* macros for accessing lower 16 bits in dword */ 21663 #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0(word, value) \ 21664 do { \ 21665 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS15_0, value); \ 21666 (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S; \ 21667 } while (0) 21668 #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS15_0(word) \ 21669 (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S) 21670 21671 #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0(word, value) \ 21672 do { \ 21673 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS15_0, value); \ 21674 (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S; \ 21675 } while (0) 21676 #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS15_0(word) \ 21677 (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S) 21678 21679 #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0(word, value) \ 21680 do { \ 21681 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0, value); \ 21682 (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S; \ 21683 } while (0) 21684 #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS15_0(word) \ 21685 (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S) 21686 21687 /* macros for accessing upper 16 bits in dword */ 21688 #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16(word, value) \ 21689 do { \ 21690 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS31_16, value); \ 21691 (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S; \ 21692 } while (0) 21693 #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS31_16(word) \ 21694 (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S) 21695 21696 #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16(word, value) \ 21697 do { \ 21698 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS31_16, value); \ 21699 (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S; \ 21700 } while (0) 21701 #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS31_16(word) \ 21702 (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S) 21703 21704 #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16(word, value) \ 21705 do { \ 21706 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16, value); \ 21707 (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S; \ 21708 } while (0) 21709 #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS31_16(word) \ 21710 (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S) 21711 21712 21713 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_VALID_SET \ 21714 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21715 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_BITS_SET \ 21716 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21717 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET_SET \ 21718 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21719 21720 #define HTT_PPDU_ID_FMT_IND_RING_ID_VALID_SET \ 21721 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21722 #define HTT_PPDU_ID_FMT_IND_RING_ID_BITS_SET \ 21723 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21724 #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET_SET \ 21725 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21726 21727 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_VALID_SET \ 21728 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21729 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_BITS_SET \ 21730 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21731 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET_SET \ 21732 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21733 21734 #define HTT_PPDU_ID_FMT_IND_LINK_ID_VALID_SET \ 21735 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21736 #define HTT_PPDU_ID_FMT_IND_LINK_ID_BITS_SET \ 21737 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21738 #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET_SET \ 21739 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21740 21741 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_VALID_SET \ 21742 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21743 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_BITS_SET \ 21744 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21745 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET_SET \ 21746 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21747 21748 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_VALID_SET \ 21749 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21750 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_BITS_SET \ 21751 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21752 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET_SET \ 21753 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21754 21755 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_VALID_SET \ 21756 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21757 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_BITS_SET \ 21758 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21759 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_OFFSET_SET \ 21760 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21761 21762 #define HTT_PPDU_ID_FMT_IND_CRC_VALID_SET \ 21763 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21764 #define HTT_PPDU_ID_FMT_IND_CRC_BITS_SET \ 21765 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21766 #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET_SET \ 21767 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21768 21769 21770 /* offsets in number dwords */ 21771 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET 1 21772 #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET 1 21773 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET 2 21774 #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET 2 21775 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET 3 21776 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET 3 21777 #define HTT_PPDU_ID_FMT_IND_MAC_ID_OFFSET 4 21778 #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET 4 21779 21780 21781 typedef struct { 21782 A_UINT32 msg_type: 8, /* bits 7:0 */ 21783 rsvd0: 24;/* bits 31:8 */ 21784 A_UINT32 hwsch_cmd_id_valid: 1, /* bits 0:0 */ 21785 hwsch_cmd_id_bits: 5, /* bits 5:1 */ 21786 hwsch_cmd_id_offset: 5, /* bits 10:6 */ 21787 rsvd1: 5, /* bits 15:11 */ 21788 ring_id_valid: 1, /* bits 16:16 */ 21789 ring_id_bits: 5, /* bits 21:17 */ 21790 ring_id_offset: 5, /* bits 26:22 */ 21791 rsvd2: 5; /* bits 31:27 */ 21792 A_UINT32 seq_idx_valid: 1, /* bits 0:0 */ 21793 seq_idx_bits: 5, /* bits 5:1 */ 21794 seq_idx_offset: 5, /* bits 10:6 */ 21795 rsvd3: 5, /* bits 15:11 */ 21796 link_id_valid: 1, /* bits 16:16 */ 21797 link_id_bits: 5, /* bits 21:17 */ 21798 link_id_offset: 5, /* bits 26:22 */ 21799 rsvd4: 5; /* bits 31:27 */ 21800 A_UINT32 seq_cmd_type_valid: 1, /* bits 0:0 */ 21801 seq_cmd_type_bits: 5, /* bits 5:1 */ 21802 seq_cmd_type_offset: 5, /* bits 10:6 */ 21803 rsvd5: 5, /* bits 15:11 */ 21804 tqm_cmd_valid: 1, /* bits 16:16 */ 21805 tqm_cmd_bits: 5, /* bits 21:17 */ 21806 tqm_cmd_offset: 5, /* bits 26:12 */ 21807 rsvd6: 5; /* bits 31:27 */ 21808 A_UINT32 mac_id_valid: 1, /* bits 0:0 */ 21809 mac_id_bits: 5, /* bits 5:1 */ 21810 mac_id_offset: 5, /* bits 10:6 */ 21811 rsvd8: 5, /* bits 15:11 */ 21812 crc_valid: 1, /* bits 16:16 */ 21813 crc_bits: 5, /* bits 21:17 */ 21814 crc_offset: 5, /* bits 26:12 */ 21815 rsvd9: 5; /* bits 31:27 */ 21816 } htt_t2h_ppdu_id_fmt_ind_t; 21817 21818 21819 /** 21820 * @brief target -> host RX_CCE_SUPER_RULE setup done message 21821 * 21822 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE 21823 * 21824 * @details 21825 * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE message is sent by the target 21826 * when RX_CCE_SUPER_RULE setup is done 21827 * 21828 * This message shows the configuration results after the setup operation. 21829 * It will always be sent to host. 21830 * The message would appear as follows: 21831 * 21832 * |31 24|23 16|15 8|7 0| 21833 * |-----------------+-----------------+----------------+----------------| 21834 * | result | response_type | pdev_id | msg_type | 21835 * |---------------------------------------------------------------------| 21836 * 21837 * The message is interpreted as follows: 21838 * dword0 - b'0:7 - msg_type: This will be set to 0x33 21839 * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE) 21840 * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is setup on 21841 * b'16:23 - response_type: Indicate the response type of this setup 21842 * done msg 21843 * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE, 21844 * response to HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST 21845 * 1: HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, 21846 * response to HTT_RX_CCE_SUPER_RULE_INSTALL 21847 * 2: HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, 21848 * response to HTT_RX_CCE_SUPER_RULE_RELEASE 21849 * b'24:31 - result: Indicate result of setup operation 21850 * For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE: 21851 * b'24 - is_rule_enough: indicate if there are 21852 * enough free cce rule slots 21853 * 0: not enough 21854 * 1: enough 21855 * b'25:31 - avail_rule_num: indicate the number of 21856 * remaining free cce rule slots, only makes sense 21857 * when is_rule_enough = 0 21858 * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE: 21859 * b'24 - cfg_result_0: indicate the config result 21860 * of RX_CCE_SUPER_RULE_0 21861 * 0: Install/Uninstall fails 21862 * 1: Install/Uninstall succeeds 21863 * b'25 - cfg_result_1: indicate the config result 21864 * of RX_CCE_SUPER_RULE_1 21865 * 0: Install/Uninstall fails 21866 * 1: Install/Uninstall succeeds 21867 * b'26:31 - reserved 21868 * For HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE: 21869 * b'24 - cfg_result_0: indicate the config result 21870 * of RX_CCE_SUPER_RULE_0 21871 * 0: Release fails 21872 * 1: Release succeeds 21873 * b'25 - cfg_result_1: indicate the config result 21874 * of RX_CCE_SUPER_RULE_1 21875 * 0: Release fails 21876 * 1: Release succeeds 21877 * b'26:31 - reserved 21878 */ 21879 21880 enum htt_rx_cce_super_rule_setup_done_response_type { 21881 HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE = 0, 21882 HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, 21883 HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, 21884 21885 /*All reply type should be before this*/ 21886 HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_RESPONSE, 21887 }; 21888 21889 PREPACK struct htt_rx_cce_super_rule_setup_done_t { 21890 A_UINT8 msg_type; 21891 A_UINT8 pdev_id; 21892 A_UINT8 response_type; 21893 union { 21894 struct { 21895 /* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE */ 21896 A_UINT8 is_rule_enough: 1, 21897 avail_rule_num: 7; 21898 }; 21899 struct { 21900 /* 21901 * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE and 21902 * HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE 21903 */ 21904 A_UINT8 cfg_result_0: 1, 21905 cfg_result_1: 1, 21906 rsvd: 6; 21907 }; 21908 } result; 21909 } POSTPACK; 21910 21911 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t)) 21912 21913 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00 21914 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8 21915 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \ 21916 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \ 21917 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S) 21918 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \ 21919 do { \ 21920 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \ 21921 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \ 21922 } while (0) 21923 21924 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 21925 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16 21926 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \ 21927 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \ 21928 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S) 21929 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \ 21930 do { \ 21931 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \ 21932 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \ 21933 } while (0) 21934 21935 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M 0xff000000 21936 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S 24 21937 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \ 21938 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \ 21939 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S) 21940 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \ 21941 do { \ 21942 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \ 21943 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \ 21944 } while (0) 21945 21946 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M 0x01000000 21947 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S 24 21948 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_GET(_var) \ 21949 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M) >> \ 21950 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S) 21951 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_SET(_var, _val) \ 21952 do { \ 21953 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH, _val); \ 21954 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)); \ 21955 } while (0) 21956 21957 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M 0xFE000000 21958 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S 25 21959 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_GET(_var) \ 21960 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M) >> \ 21961 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S) 21962 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_SET(_var, _val) \ 21963 do { \ 21964 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM, _val); \ 21965 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)); \ 21966 } while (0) 21967 21968 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M 0x01000000 21969 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S 24 21970 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_GET(_var) \ 21971 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M) >> \ 21972 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S) 21973 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_SET(_var, _val) \ 21974 do { \ 21975 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0, _val); \ 21976 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)); \ 21977 } while (0) 21978 21979 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M 0x02000000 21980 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S 25 21981 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_GET(_var) \ 21982 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M) >> \ 21983 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S) 21984 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_SET(_var, _val) \ 21985 do { \ 21986 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1, _val); \ 21987 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \ 21988 } while (0) 21989 21990 21991 /** 21992 * @brief target -> host TX_LCE_SUPER_RULE setup done message 21993 * 21994 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE 21995 * 21996 * @details 21997 * HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE message is sent by the target 21998 * when TX_SUPER_RULE setup is done. 21999 * 22000 * This message shows the configuration results after the setup operation. 22001 * It will always be sent to host. 22002 * The message would appear as follows: 22003 * 22004 * |31 24|23 16|15 8|7 0| 22005 * |-----------------+-----------------+----------------+----------------| 22006 * | reserved | response_type | pdev_id | msg_type | 22007 * |---------------------------------------------------------------------| 22008 * | tx_super_rule_result[0] | 22009 * |---------------------------------------------------------------------| 22010 * | tx_super_rule_result[1] | 22011 * |---------------------------------------------------------------------| 22012 * | tx_super_rule_result[2] | 22013 * |---------------------------------------------------------------------| 22014 * 22015 * The message is interpreted as follows: 22016 * dword0 - b'0:7 - msg_type: This will be set to 0x3b 22017 * (HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE) 22018 * b'8:15 - pdev_id: Identify which pdev TX_SUPER_RULE is setup on 22019 * b'16:23 - response_type: Indicate the response type of this setup 22020 * done msg 22021 * 0: HTT_TX_LCE_SUPER_RULE_INSTALL_RESPONSE, 22022 * response to HTT_TX_LCE_SUPER_RULE_INSTALL 22023 * 1: HTT_TX_LCE_SUPER_RULE_RELEASE_RESPONSE, 22024 * response to HTT_TX_LCE_SUPER_RULE_RELEASE or 22025 * FW internal trigger on LCE rule release 22026 * b'24:31 - reserved: 22027 * 22028 * Each tx_super_rule_result structure would appear as follows: 22029 * |31 24|23 16|15 8|7 0| 22030 * |---------------------------------------------------------------------| 22031 * | is_valid | result | l4_dst_port | 22032 * |---------------------------------------------------------------------| 22033 * 22034 * dword0 - b'0:15 - l4_dst_port: destination port corresponding to rule 22035 * which is added/released 22036 * b'16:23 - result: Indicate the result of the operation based on 22037 * the message header's "response_type" 22038 * For HTT_TX_LCE_SUPER_RULE_INSTALL_RESPONSE: 22039 * 0: HTT_TX_LCE_SUPER_RULE_INSTALL_FAIL 22040 * 1: HTT_TX_LCE_SUPER_RULE_INSTALL_SUCCESS 22041 * For HTT_TX_LCE_SUPER_RULE_RELEASE_RESPONSE: 22042 * 0: HTT_TX_LCE_SUPER_RULE_RELEASE_FAIL 22043 * 1: HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS 22044 * 2: HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS_HIGH_TPUT 22045 * 22046 * The tx_super_rule_result[1] structure is similar. 22047 * The tx_super_rule_result[2] structure is similar. 22048 */ 22049 22050 enum htt_tx_lce_super_rule_setup_done_response_type { 22051 /* Two LCE rules operation responses */ 22052 HTT_TX_LCE_SUPER_RULE_INSTALL_RESPONSE = 0, 22053 HTT_TX_LCE_SUPER_RULE_RELEASE_RESPONSE, 22054 22055 /* All reply type should be before this */ 22056 HTT_TX_LCE_RULE_SETUP_INVALID_RESPONSE, 22057 }; 22058 22059 enum htt_tx_super_rule_install_response_result { 22060 HTT_TX_LCE_SUPER_RULE_INSTALL_FAIL = 0, 22061 HTT_TX_LCE_SUPER_RULE_INSTALL_SUCCESS, 22062 }; 22063 22064 enum htt_tx_super_rule_release_response_result{ 22065 HTT_TX_LCE_SUPER_RULE_RELEASE_FAIL = 0, 22066 HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS, 22067 HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS_HIGH_TPUT, 22068 }; 22069 22070 typedef struct { 22071 A_UINT32 l4_dst_port: 16, 22072 /* result: 22073 * htt_tx_super_rule_install_response_result or 22074 * htt_tx_super_rule_release_response_result 22075 */ 22076 result: 8, 22077 is_valid: 8; 22078 } htt_tx_lce_super_rule_result_t; 22079 22080 PREPACK struct htt_tx_lce_super_rule_setup_done_t { 22081 A_UINT8 msg_type; 22082 A_UINT8 pdev_id; 22083 A_UINT8 response_type; /* htt_tx_lce_super_rule_setup_done_response_type */ 22084 A_UINT8 reserved; 22085 htt_tx_lce_super_rule_result_t tx_super_rule_result[HTT_TX_LCE_SUPER_RULE_SETUP_NUM]; 22086 } POSTPACK; 22087 22088 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_tx_lce_super_rule_setup_done_t)) 22089 22090 22091 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00 22092 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8 22093 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \ 22094 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \ 22095 HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S) 22096 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \ 22097 do { \ 22098 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \ 22099 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \ 22100 } while (0) 22101 22102 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 22103 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16 22104 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \ 22105 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \ 22106 HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S) 22107 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \ 22108 do { \ 22109 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \ 22110 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \ 22111 } while (0) 22112 22113 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_M 0x0000ffff 22114 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_S 0 22115 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_GET(_var) \ 22116 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_M) >> \ 22117 HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_S) 22118 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_SET(_var, _val) \ 22119 do { \ 22120 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT, _val); \ 22121 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_S)); \ 22122 } while (0) 22123 22124 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_M 0x00ff0000 22125 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_S 16 22126 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \ 22127 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \ 22128 HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_S) 22129 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \ 22130 do { \ 22131 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \ 22132 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \ 22133 } while (0) 22134 22135 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_M 0xff000000 22136 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_S 24 22137 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_GET(_var) \ 22138 (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_M) >> \ 22139 HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_S) 22140 #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_SET(_var, _val) \ 22141 do { \ 22142 HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID, _val); \ 22143 ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_S)); \ 22144 } while (0) 22145 22146 22147 /** 22148 * THE BELOW MESSAGE HAS BEEN DEPRECATED 22149 *====================================== 22150 * @brief target -> host CoDel MSDU queue latencies array configuration 22151 * 22152 * MSG_TYPE => HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND 22153 * 22154 * @details 22155 * The HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND message is used 22156 * by the target to inform the host of the location and size of the DDR array of 22157 * per MSDU queue latency metrics. This array is updated by the host and 22158 * read by the target. The target uses these metric values to determine 22159 * which MSDU queues have latencies exceeding their CoDel latency target. 22160 * 22161 * |31 16|15 8|7 0| 22162 * |-------------------------------------------+----------| 22163 * | number of array elements | reserved | MSG_TYPE | 22164 * |-------------------------------------------+----------| 22165 * | array physical address, low bits | 22166 * |------------------------------------------------------| 22167 * | array physical address, high bits | 22168 * |------------------------------------------------------| 22169 * Header fields: 22170 * - MSG_TYPE 22171 * Bits 7:0 22172 * Purpose: Identifies this as a CoDel MSDU queue latencies 22173 * array configuration message. 22174 * Value: (HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND) 22175 * - NUM_ELEM 22176 * Bits 31:16 22177 * Purpose: Inform the host of the length of the MSDU queue latencies array. 22178 * Value: Specifies the number of elements in the MSDU queue latency 22179 * metrics array. This value is the same as the maximum number of 22180 * MSDU queues supported by the target. 22181 * Since each array element is 16 bits, the size in bytes of the 22182 * MSDU queue latency metrics array is twice the number of elements. 22183 * - PADDR_LOW 22184 * Bits 31:0 22185 * Purpose: Inform the host of the MSDU queue latencies array's location. 22186 * Value: Lower 32 bits of the physical address of the MSDU queue latency 22187 * metrics array. 22188 * - PADDR_HIGH 22189 * Bits 31:0 22190 * Purpose: Inform the host of the MSDU queue latencies array's location. 22191 * Value: Upper 32 bits of the physical address of the MSDU queue latency 22192 * metrics array. 22193 */ 22194 typedef struct { 22195 A_UINT32 msg_type: 8, /* bits 7:0 */ 22196 reserved: 8, /* bits 15:8 */ 22197 num_elem: 16; /* bits 31:16 */ 22198 A_UINT32 paddr_low; 22199 A_UINT32 paddr_high; 22200 } htt_t2h_codel_msduq_latencies_array_cfg_int_t; /* DEPRECATED */ 22201 22202 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_SIZE 12 /* bytes */ 22203 22204 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M 0xffff0000 22205 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S 16 22206 22207 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_GET(_var) \ 22208 (((_var) & HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M) >> \ 22209 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S) 22210 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_SET(_var, _val) \ 22211 do { \ 22212 HTT_CHECK_SET_VAL( \ 22213 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM, _val); \ 22214 ((_var) |= ((_val) << \ 22215 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S)); \ 22216 } while (0) 22217 22218 /* 22219 * This CoDel MSDU queue latencies array whose location and number of 22220 * elements are specified by this HTT_T2H message consists of 16-bit elements 22221 * that each specify a statistical summary (min) of a MSDU queue's latency, 22222 * using milliseconds units. 22223 */ 22224 #define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 22225 22226 22227 /** 22228 * @brief target -> host rx completion indication message definition 22229 * 22230 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DATA_IND 22231 * 22232 * @details 22233 * The following diagram shows the format of the Rx completion indication sent 22234 * from the target to the host 22235 * 22236 * |31|29|28 24|23 12|11 9|8| 7|6|5|4|3|2|1|0| 22237 * |---------------+----------------------------+----------------| 22238 * | vdev_id | peer_id | msg_type | 22239 * hdr: |---------------+--------------------------+-+----------------| 22240 * | rsvd0 |F| msdu_cnt | 22241 * pyld: |==========================================+=+================| 22242 * MSDU 0 | buf addr lo (bits 31:0) | 22243 * |-----+--------------------------------------+----------------| 22244 * |rsvd1| SW buffer cookie | buf addr hi | 22245 * |--+--+-----------------------------+--------+--+-+-+-+-+-+-+-| 22246 * |R2| W| MSDU length | TID |MC|D|S|C|L|F|R|M| 22247 * |-------------------------------------------------+---------+-| 22248 * | rsvd3 | err info|E| 22249 * |=================================================+=========+=| 22250 * MSDU 1 | buf addr lo (bits 31:0) | 22251 * : ... : 22252 * | rsvd3 | err info|E| 22253 * |-------------------------------------------------------------| 22254 * Where: 22255 * F = fragment 22256 * M = MPDU retry bit 22257 * R = raw MPDU frame 22258 * F = first MSDU in MPDU 22259 * L = last MSDU in MPDU 22260 * C = MSDU continuation 22261 * S = Souce Addr is valid 22262 * D = Dest Addr is valid 22263 * MC = Dest Addr is multicast / broadcast 22264 * W = is first MSDU after WoW wakeup 22265 * R2 = rsvd2 22266 * E = error valid 22267 */ 22268 22269 /* htt_t2h_rx_data_msdu_err: 22270 * To be filled in "htt_t2h_rx_data_msdu_info.error_info" field 22271 * when FW forwards MSDU to host. 22272 */ 22273 typedef enum htt_t2h_rx_data_msdu_err { 22274 /* ERR_DECRYPT: 22275 * FW sets this when rxdma_error_code = <enum 3 rxdma_decrypt_err>. 22276 * host maintains error stats, recycles buffer. 22277 */ 22278 HTT_RXDATA_ERR_DECRYPT = 0, 22279 22280 /* ERR_TKIP_MIC: 22281 * FW sets this when rxdma_error_code = <enum 4 rxdma_tkip_mic_err>. 22282 * Host maintains error stats, recycles buffer, sends notification to 22283 * middleware. 22284 */ 22285 HTT_RXDATA_ERR_TKIP_MIC = 1, 22286 22287 /* ERR_UNENCRYPTED: 22288 * FW sets this when rxdma_error_code = <enum 5 rxdma_unecrypted_err>. 22289 * Host maintains error stats, recycles buffer. 22290 */ 22291 HTT_RXDATA_ERR_UNENCRYPTED = 2, 22292 22293 /* ERR_MSDU_LIMIT: 22294 * FW sets this when rxdma_error_code = <enum 7 rxdma_msdu_limit_err>. 22295 * Host maintains error stats, recycles buffer. 22296 */ 22297 HTT_RXDATA_ERR_MSDU_LIMIT = 3, 22298 22299 /* ERR_FLUSH_REQUEST: 22300 * FW sets this when rxdma_error_code = <enum 13 rxdma_flush_request>. 22301 * Host maintains error stats, recycles buffer. 22302 */ 22303 HTT_RXDATA_ERR_FLUSH_REQUEST = 4, 22304 22305 /* ERR_OOR: 22306 * FW full reorder layer maps this error to <enum 7 regular_frame_OOR>. 22307 * Host maintains error stats, recycles buffer mainly for low 22308 * TCP KPI debugging. 22309 */ 22310 HTT_RXDATA_ERR_OOR = 5, 22311 22312 /* ERR_2K_JUMP: 22313 * FW full reorder layer maps this error to <enum 5 regular_frame_2k_jump>. 22314 * Host maintains error stats, recycles buffer mainly for low 22315 * TCP KPI debugging. 22316 */ 22317 HTT_RXDATA_ERR_2K_JUMP = 6, 22318 22319 /* ERR_ZERO_LEN_MSDU: 22320 * FW sets this error flag for a 0 length MSDU. 22321 * Host maintains error stats, recycles buffer. 22322 */ 22323 HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7, 22324 22325 /* ERR_INVALID_PEER: 22326 * FW sets this error flag when MSDU is recived from invalid PEER 22327 * HOST decides to send DEAUTH or not, recyles buffer. 22328 */ 22329 HTT_RXDATA_ERR_INVALID_PEER = 8, 22330 22331 /* add new error codes here */ 22332 22333 HTT_RXDATA_ERR_MAX = 32 22334 } htt_t2h_rx_data_msdu_err_e; 22335 22336 struct htt_t2h_rx_data_ind_t 22337 { 22338 A_UINT32 /* word 0 */ 22339 /* msg_type: 22340 * Set to Rx data indication i.e. HTT_T2H_MSG_TYPE_RX_DATA_IND. 22341 */ 22342 msg_type: 8, 22343 peer_id: 16, /* This will provide peer data */ 22344 vdev_id: 8; /* This will provide vdev id info */ 22345 A_UINT32 /* word 1 */ 22346 /* msdu_cnt: 22347 * Total number of MSDUs (htt_t2h_rx_data_msdu_info items) in message. 22348 */ 22349 msdu_cnt: 8, 22350 frag: 1, /* this bit will be set for 802.11 frag MPDU */ 22351 rsvd0: 23; 22352 /* NOTE: 22353 * To preserve backwards compatibility, 22354 * no new fields can be added in this struct. 22355 */ 22356 }; 22357 22358 struct htt_t2h_rx_data_msdu_info 22359 { 22360 A_UINT32 /* word 0 */ 22361 buffer_addr_low : 32; 22362 A_UINT32 /* word 1 */ 22363 buffer_addr_high : 8, 22364 sw_buffer_cookie : 21, 22365 /* fw_offloads_inspected: 22366 * When reo_destination_indication is 6 in reo_entrance_ring 22367 * of the RXDMA2REO MPDU upload, all the MSDUs that are part 22368 * of the MPDU are inspected by FW offloads layer, subsequently 22369 * the MSDUs are qualified to be host interested. 22370 * In such case the fw_offloads_inspected is set to 1, else 0. 22371 * This will assist host to not consider such MSDUs for FISA 22372 * flow addition. 22373 */ 22374 fw_offloads_inspected : 1, 22375 rsvd1 : 2; 22376 A_UINT32 /* word 2 */ 22377 mpdu_retry_bit : 1, /* used for stats maintenance */ 22378 raw_mpdu_frame : 1, /* used for pkt drop and processing */ 22379 first_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ 22380 last_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ 22381 msdu_continuation : 1, /* used for MSDU scatter/gather support */ 22382 sa_is_valid : 1, /* used for HW issue check in 22383 * is_sa_da_idx_valid() */ 22384 da_is_valid : 1, /* used for HW issue check and 22385 * intra-BSS forwarding */ 22386 da_is_mcbc : 1, 22387 tid_info : 8, /* used for stats maintenance */ 22388 msdu_length : 14, 22389 is_first_pkt_after_wkp : 1, /* indicates this is the first rx MSDU 22390 * provided by fw after WoW exit */ 22391 rsvd2 : 1; 22392 A_UINT32 /* word 3 */ 22393 error_valid : 1, /* Set if the MSDU has any error */ 22394 error_info : 5, /* If error_valid is TRUE, then refer to 22395 * "htt_t2h_rx_data_msdu_err_e" for 22396 * checking error reason. */ 22397 rsvd3 : 26; 22398 /* NOTE: 22399 * To preserve backwards compatibility, 22400 * no new fields can be added in this struct. 22401 */ 22402 }; 22403 22404 /* HTT_RX_DATA_IND_HDR_SIZE: 2 4-byte words 22405 * This is the size of htt_t2h_rx_data_ind_t alone which is fixed overhead 22406 * for every Rx DATA IND sent by FW to host. 22407 */ 22408 #define HTT_RX_DATA_IND_HDR_SIZE (2*4) 22409 /* HTT_RX_DATA_MSDU_INFO_SIZE: 4 4-bytes words 22410 * This is the size of each MSDU detail that will be piggybacked with the 22411 * RX IND header. 22412 */ 22413 #define HTT_RX_DATA_MSDU_INFO_SIZE (4*4) 22414 22415 /* member definitions of htt_t2h_rx_data_ind_t */ 22416 22417 #define HTT_RX_DATA_IND_PEER_ID_M 0x00ffff00 22418 #define HTT_RX_DATA_IND_PEER_ID_S 8 22419 22420 #define HTT_RX_DATA_IND_PEER_ID_SET(word, value) \ 22421 do { \ 22422 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_PEER_ID, value); \ 22423 (word) |= (value) << HTT_RX_DATA_IND_PEER_ID_S; \ 22424 } while (0) 22425 #define HTT_RX_DATA_IND_PEER_ID_GET(word) \ 22426 (((word) & HTT_RX_DATA_IND_PEER_ID_M) >> HTT_RX_DATA_IND_PEER_ID_S) 22427 22428 #define HTT_RX_DATA_IND_VDEV_ID_M 0xff000000 22429 #define HTT_RX_DATA_IND_VDEV_ID_S 24 22430 22431 #define HTT_RX_DATA_IND_VDEV_ID_SET(word, value) \ 22432 do { \ 22433 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_VDEV_ID, value); \ 22434 (word) |= (value) << HTT_RX_DATA_IND_VDEV_ID_S; \ 22435 } while (0) 22436 #define HTT_RX_DATA_IND_VDEV_ID_GET(word) \ 22437 (((word) & HTT_RX_DATA_IND_VDEV_ID_M) >> HTT_RX_DATA_IND_VDEV_ID_S) 22438 22439 #define HTT_RX_DATA_IND_MSDU_CNT_M 0x000000ff 22440 #define HTT_RX_DATA_IND_MSDU_CNT_S 0 22441 22442 #define HTT_RX_DATA_IND_MSDU_CNT_SET(word, value) \ 22443 do { \ 22444 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_MSDU_CNT, value); \ 22445 (word) |= (value) << HTT_RX_DATA_IND_MSDU_CNT_S; \ 22446 } while (0) 22447 #define HTT_RX_DATA_IND_MSDU_CNT_GET(word) \ 22448 (((word) & HTT_RX_DATA_IND_MSDU_CNT_M) >> HTT_RX_DATA_IND_MSDU_CNT_S) 22449 22450 #define HTT_RX_DATA_IND_FRAG_M 0x00000100 22451 #define HTT_RX_DATA_IND_FRAG_S 8 22452 22453 #define HTT_RX_DATA_IND_FRAG_SET(word, value) \ 22454 do { \ 22455 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_FRAG, value); \ 22456 (word) |= (value) << HTT_RX_DATA_IND_FRAG_S; \ 22457 } while (0) 22458 #define HTT_RX_DATA_IND_FRAG_GET(word) \ 22459 (((word) & HTT_RX_DATA_IND_FRAG_M) >> HTT_RX_DATA_IND_FRAG_S) 22460 22461 /* member definitions of htt_t2h_rx_data_msdu_info */ 22462 22463 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M 0xFFFFFFFF 22464 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S 0 22465 22466 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M 0x000000FF 22467 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S 0 22468 22469 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_SET(word, value) \ 22470 do { \ 22471 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW, value); \ 22472 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S; \ 22473 } while (0) 22474 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_GET(word) \ 22475 (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S) 22476 22477 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_SET(word, value) \ 22478 do { \ 22479 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH, value); \ 22480 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S; \ 22481 } while (0) 22482 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_GET(word) \ 22483 (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S) 22484 22485 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M 0x1FFFFF00 22486 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S 8 22487 22488 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_SET(word, value) \ 22489 do { \ 22490 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE, value); \ 22491 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S; \ 22492 } while (0) 22493 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \ 22494 (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S) 22495 22496 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M 0x20000000 22497 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S 29 22498 22499 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_SET(word, value) \ 22500 do { \ 22501 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED, value); \ 22502 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S; \ 22503 } while (0) 22504 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_GET(word) \ 22505 (((word) & HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M) >> HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S) 22506 22507 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001 22508 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0 22509 22510 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_SET(word, value) \ 22511 do { \ 22512 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT, value); \ 22513 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S; \ 22514 } while (0) 22515 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_GET(word) \ 22516 (((word) & HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M) >> HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S) 22517 22518 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M 0x00000002 22519 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S 1 22520 22521 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_SET(word, value) \ 22522 do { \ 22523 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME, value); \ 22524 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S; \ 22525 } while (0) 22526 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_GET(word) \ 22527 (((word) & HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M) >> HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S) 22528 22529 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M 0x00000004 22530 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S 2 22531 22532 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_SET(word, value) \ 22533 do { \ 22534 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU, value); \ 22535 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S; \ 22536 } while (0) 22537 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_GET(word) \ 22538 (((word) & HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S) 22539 22540 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M 0x00000008 22541 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S 3 22542 22543 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_SET(word, value) \ 22544 do { \ 22545 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU, value); \ 22546 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S; \ 22547 } while (0) 22548 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_GET(word) \ 22549 (((word) & HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S) 22550 22551 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M 0x00000010 22552 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S 4 22553 22554 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_SET(word, value) \ 22555 do { \ 22556 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION, value); \ 22557 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S; \ 22558 } while (0) 22559 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_GET(word) \ 22560 (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S) 22561 22562 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M 0x00000020 22563 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S 5 22564 22565 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_SET(word, value) \ 22566 do { \ 22567 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SA_IS_VALID, value); \ 22568 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S; \ 22569 } while (0) 22570 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_GET(word) \ 22571 (((word) & HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S) 22572 22573 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M 0x00000040 22574 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S 6 22575 22576 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_SET(word, value) \ 22577 do { \ 22578 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_VALID, value); \ 22579 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S; \ 22580 } while (0) 22581 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_GET(word) \ 22582 (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S) 22583 22584 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M 0x00000080 22585 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S 7 22586 22587 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_SET(word, value) \ 22588 do { \ 22589 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC, value); \ 22590 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S; \ 22591 } while (0) 22592 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_GET(word) \ 22593 (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S) 22594 22595 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_M 0x0000FF00 22596 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_S 8 22597 22598 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_SET(word, value) \ 22599 do { \ 22600 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_TID_INFO, value); \ 22601 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_TID_INFO_S; \ 22602 } while (0) 22603 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_GET(word) \ 22604 (((word) & HTT_RX_DATA_MSDU_INFO_TID_INFO_M) >> HTT_RX_DATA_MSDU_INFO_TID_INFO_S) 22605 22606 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M 0x3FFF0000 22607 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S 16 22608 22609 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_SET(word, value) \ 22610 do { \ 22611 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH, value); \ 22612 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S; \ 22613 } while (0) 22614 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_GET(word) \ 22615 (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S) 22616 22617 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M 0x40000000 22618 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S 30 22619 22620 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_SET(word, value) \ 22621 do { \ 22622 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP, value); \ 22623 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S; \ 22624 } while (0) 22625 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_GET(word) \ 22626 (((word) & HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M) >> HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S) 22627 22628 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M 0x00000001 22629 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S 0 22630 22631 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_SET(word, value) \ 22632 do { \ 22633 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_VALID, value); \ 22634 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S; \ 22635 } while (0) 22636 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_GET(word) \ 22637 (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S) 22638 22639 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M 0x0000001E 22640 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S 1 22641 22642 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_SET(word, value) \ 22643 do { \ 22644 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_INFO, value); \ 22645 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S; \ 22646 } while (0) 22647 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_GET(word) \ 22648 (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S) 22649 22650 22651 /** 22652 * @brief target -> Primary peer migration message to host 22653 * 22654 * MSG_TYPE => HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND 22655 * 22656 * @details 22657 * HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND message is sent by target 22658 * to host to flush & set-up the RX rings to new primary peer 22659 * 22660 * The message would appear as follows: 22661 * 22662 * |31 16|15 12|11 8|7 0| 22663 * |-------------------------------+---------+---------+--------------| 22664 * | vdev ID | pdev ID | chip ID | msg type | 22665 * |-------------------------------+---------+---------+--------------| 22666 * | ML peer ID | SW peer ID | 22667 * |-------------------------------+----------------------------------| 22668 * 22669 * The message is interpreted as follows: 22670 * dword0 - b'0:7 - msg_type: This will be set to 0x37 22671 * (HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND) 22672 * b'8:11 - chip_id: Indicate which chip has been chosen as primary 22673 * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen 22674 * as primary 22675 * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen 22676 * as primary 22677 * 22678 * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer 22679 * chosen as primary 22680 * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the 22681 * primary peer belongs. 22682 */ 22683 typedef struct { 22684 A_UINT32 msg_type: 8, /* bits 7:0 */ 22685 chip_id: 4, /* bits 11:8 */ 22686 pdev_id: 4, /* bits 15:12 */ 22687 vdev_id: 16; /* bits 31:16 */ 22688 A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ 22689 ml_peer_id: 16; /* bits 31:16 */ 22690 } htt_t2h_primary_link_peer_migrate_ind_t; 22691 22692 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 22693 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 22694 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ 22695 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ 22696 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) 22697 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ 22698 do { \ 22699 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ 22700 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ 22701 } while (0) 22702 22703 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 22704 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 22705 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ 22706 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ 22707 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) 22708 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ 22709 do { \ 22710 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ 22711 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ 22712 } while (0) 22713 22714 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 22715 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 22716 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ 22717 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ 22718 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) 22719 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ 22720 do { \ 22721 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ 22722 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ 22723 } while (0) 22724 22725 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF 22726 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 22727 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ 22728 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ 22729 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) 22730 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ 22731 do { \ 22732 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ 22733 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ 22734 } while (0) 22735 22736 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 22737 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 22738 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ 22739 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ 22740 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) 22741 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ 22742 do { \ 22743 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ 22744 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ 22745 } while (0) 22746 22747 /** 22748 * @brief target -> host rx peer AST override message defenition 22749 * 22750 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND 22751 * 22752 * @details 22753 * Format inherits parts of the HTT_T2H_MSG_TYPE_PEER_MAP_V3 published above 22754 * where in the dummy ast index is provided to the host. 22755 * This new message below is sent to the host at run time from the TX_DE 22756 * exception path when a SAWF flow is detected for a peer. 22757 * This is sent up once per SAWF peer. 22758 * This layout assumes the target operates as little-endian. 22759 * 22760 * |31 24|23 16|15 8|7 0| 22761 * |--------------------------------------+-----------------+-----------------| 22762 * | SW peer ID | vdev ID | msg type | 22763 * |-----------------+--------------------+-----------------+-----------------| 22764 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 22765 * |-----------------+--------------------+-----------------+-----------------| 22766 * | dummy AST Index #1 | MAC addr 5 | MAC addr 4 | 22767 * |--------------------------------------+-----------------+-----------------| 22768 * | reserved | dummy AST Index #2 | 22769 * |--------------------------------------+-----------------------------------| 22770 * 22771 * The following field definitions describe the format of the peer ast override 22772 * index messages sent from the target to the host. 22773 * - MSG_TYPE 22774 * Bits 7:0 22775 * Purpose: identifies this as a peer map v3 message 22776 * Value: 0x38 (HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND) 22777 * - VDEV_ID 22778 * Bits 15:8 22779 * Purpose: Indicates which virtual device the peer is associated with. 22780 * - SW_PEER_ID 22781 * Bits 31:16 22782 * Purpose: The peer ID (index) that WAL has allocated for this peer. 22783 * - MAC_ADDR_L32 22784 * Bits 31:0 22785 * Purpose: Identifies which peer node the peer ID is for. 22786 * Value: lower 4 bytes of peer node's MAC address 22787 * - MAC_ADDR_U16 22788 * Bits 15:0 22789 * Purpose: Identifies which peer node the peer ID is for. 22790 * Value: upper 2 bytes of peer node's MAC address 22791 * - AST_INDEX1 22792 * Bits 31:16 22793 * Purpose: The 1st extra AST index used to identify user defined MSDUQ 22794 * - AST_INDEX2 22795 * Bits 15:0 22796 * Purpose: The 2nd extra AST index used to identify user defined MSDUQ 22797 */ 22798 22799 /* dword 0 */ 22800 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M 0xffff0000 22801 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S 16 22802 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_M 0x0000ff00 22803 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_S 8 22804 /* dword 1 */ 22805 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M 0xffffffff 22806 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S 0 22807 /* dword 2 */ 22808 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M 0x0000ffff 22809 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S 0 22810 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_M 0xffff0000 22811 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_S 16 22812 /* dword 3 */ 22813 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_M 0x0000ffff 22814 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_S 0 22815 22816 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_SET(word, value) \ 22817 do { \ 22818 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_VDEV_ID, value); \ 22819 (word) |= (value) << HTT_PEER_AST_OVERRIDE_VDEV_ID_S; \ 22820 } while (0) 22821 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_GET(word) \ 22822 (((word) & HTT_PEER_AST_OVERRIDE_VDEV_ID_M) >> HTT_PEER_AST_OVERRIDE_VDEV_ID_S) 22823 22824 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_SET(word, value) \ 22825 do { \ 22826 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_SW_PEER_ID, value); \ 22827 (word) |= (value) << HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S; \ 22828 } while (0) 22829 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_GET(word) \ 22830 (((word) & HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M) >> HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S) 22831 22832 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_SET(word, value) \ 22833 do { \ 22834 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32, value); \ 22835 (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S; \ 22836 } while (0) 22837 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_GET(word) \ 22838 (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S) 22839 22840 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_SET(word, value) \ 22841 do { \ 22842 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16, value); \ 22843 (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S; \ 22844 } while (0) 22845 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_GET(word) \ 22846 (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S) 22847 22848 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_SET(word, value) \ 22849 do { \ 22850 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX1, value); \ 22851 (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX1_S; \ 22852 } while (0) 22853 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_GET(word) \ 22854 (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX1_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX1_S) 22855 22856 22857 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_SET(word, value) \ 22858 do { \ 22859 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX2, value); \ 22860 (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX2_S; \ 22861 } while (0) 22862 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_GET(word) \ 22863 (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX2_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX2_S) 22864 22865 22866 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_WORD_BASE_OFFSET 4 /* bytes */ 22867 #define HTT_PEER_AST_OVERRIDE_DUMMY_AST1_WORD_BASE_OFFSET 8 /* bytes */ 22868 #define HTT_PEER_AST_OVERRIDE_DUMMY_AST2_WORD_BASE_OFFSET 12 /* bytes */ 22869 22870 #define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16 22871 22872 22873 /** 22874 * @brief target -> periodic report of tx latency to host 22875 * 22876 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND 22877 * 22878 * @details 22879 * The message starts with a message header followed by one or more 22880 * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev. 22881 * After each upload, these tx latency stats will be reset. 22882 * 22883 * |31 24|23 16|15 14|13 10|9 8|7 0| 22884 * +-------------------------+-----+-----+---+----------| 22885 * hdr | |pyld elem sz| | GR | P | msg type | 22886 *- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22887 * pyld | peer ID | 22888 * |----------------------------------------------------| 22889 * | peer_tx_latency[0] | 22890 * |----------------------------------------------------| 22891 * 1st | peer_tx_latency[1] | 22892 * peer |----------------------------------------------------| 22893 * | peer_tx_latency[2] | 22894 * |----------------------------------------------------| 22895 * | peer_tx_latency[3] | 22896 * |----------------------------------------------------| 22897 * | avg latency | 22898 * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22899 * | peer ID | 22900 * |----------------------------------------------------| 22901 * | peer_tx_latency[0] | 22902 * |----------------------------------------------------| 22903 * 2nd | peer_tx_latency[1] | 22904 * peer |----------------------------------------------------| 22905 * | peer_tx_latency[2] | 22906 * |----------------------------------------------------| 22907 * | peer_tx_latency[3] | 22908 * |----------------------------------------------------| 22909 * | avg latency | 22910 * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22911 * Where: 22912 * P = pdev ID 22913 * GR = granularity 22914 * 22915 * @details 22916 * htt_t2h_tx_latency_stats_periodic_hdr_t: 22917 * - msg_type 22918 * Bits 7:0 22919 * Purpose: identifies this as a tx latency report message 22920 * Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND) 22921 * - pdev_id 22922 * Bits 9:8 22923 * Purpose: Indicates which pdev this message is associated with. 22924 * - granularity 22925 * Bits 13:10 22926 * Purpose: specifies the granulairty of each tx latency bucket in MS. 22927 * There are 4 buckets in total. E.g. if granularity is set to 5 ms, 22928 * then the ranges for the 4 latency histogram buckets will be 22929 * 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively. 22930 * - payload_elem_size 22931 * Bits 23:16 22932 * Purpose: specifies the size of each element within the msg's payload 22933 * In other words, this field specified the value of 22934 * sizeof(htt_t2h_peer_tx_latency_stats) based on the target's 22935 * revision of the htt_t2h_peer_tx_latency_stats definition. 22936 * If the payload_elem_size reported in the message exceeds the 22937 * sizeof(htt_t2h_peer_tx_latency_stats) based on the host's 22938 * revision of the htt_t2h_peer_tx_latency_stats definition, 22939 * the host shall ignore the excess data. 22940 * Conversely, if the payload_elem_size reported in the message is 22941 * less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's 22942 * revision of the htt_t2h_peer_tx_latency_stats definition, 22943 * the host shall use 0x0 values for the portion of the data not 22944 * provided by the target. 22945 * The host can compare the payload_elem_size to the total size of 22946 * the message minus the size of the message header to determine 22947 * how many peer payload elements are present in the message. 22948 * - sw_peer_id 22949 * Purpose: The peer to which the following stats belong 22950 * - peer_tx_latency 22951 * Purpose: tx latency histogram for this peer, with 4 buckets whose 22952 * size (in milliseconds) is specified by the granularity field 22953 * - avg_latency 22954 * Purpose: average tx latency (in ms) for this peer in this report interval 22955 */ 22956 typedef struct { 22957 A_UINT32 msg_type: 8, 22958 pdev_id: 2, 22959 granularity: 4, 22960 reserved1: 2, 22961 payload_elem_size: 8, 22962 reserved2: 8; 22963 } htt_t2h_tx_latency_stats_periodic_hdr_t; 22964 22965 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \ 22966 (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t)) 22967 #define HTT_PEER_TX_LATENCY_REPORT_BINS 4 22968 22969 typedef struct _htt_tx_latency_stats { 22970 A_UINT32 peer_id; 22971 A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS]; 22972 A_UINT32 avg_latency; 22973 } htt_t2h_peer_tx_latency_stats; 22974 22975 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300 22976 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8 22977 22978 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ 22979 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S) 22980 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ 22981 do { \ 22982 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \ 22983 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \ 22984 } while (0) 22985 22986 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00 22987 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10 22988 22989 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \ 22990 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S) 22991 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \ 22992 do { \ 22993 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \ 22994 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \ 22995 } while (0) 22996 22997 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000 22998 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16 22999 23000 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \ 23001 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S) 23002 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \ 23003 do { \ 23004 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \ 23005 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \ 23006 } while (0) 23007 23008 23009 /** 23010 * @brief target -> host report showing MSDU queue configuration 23011 * 23012 * MSG_TYPE => HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND 23013 * 23014 * @details 23015 * 23016 * |31 24|23 16|15|14 11|10|9 8|7 0| 23017 * |----------------+----------------+--+-----+--+---+----------------------| 23018 * | peer_id | htt_qtype | msg type | 23019 * |----------------+----------------+--+-----+--+---+----------+-----------| 23020 * | error_code | svc_class_id | R| AST | F|WHO| hlos_tid | remap_tid | 23021 * |----------------+----------------+--+-----+--+---+----------+-----------| 23022 * | request_cookie | tgt_opaque_msduq_id | 23023 * |------------------------------------------------------------------------| 23024 * Where WHO = who_classify_info_sel 23025 * F = flow_override 23026 * AST = ast_list_idx 23027 * R = reserved 23028 * 23029 * @details 23030 * htt_t2h_msg_type_sdwf_msduq_cfg_ind_t: 23031 * 23032 * The message is interpreted as follows: 23033 * dword0 - b'7:0 - msg_type: Identifies this as a MSDU queue cfg indication 23034 * This will be set to 0x3c 23035 * (HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND) 23036 * b'15:8 - HTT qtype (refer to HTT_MSDU_QTYPE) 23037 * b'31:16 - peer ID 23038 * 23039 * dword1 - b'3:0 - remap TID, as assigned in firmware 23040 * b'7:4 - HLOS TID, as sent by host in TCL Data Command 23041 * hlos_tid : Common to Lithium and Beryllium 23042 * b'9:8 - who_classify_info_sel (WWHO, as sent by host in 23043 * TCL Data Command : Beryllium 23044 * b'10:10 - flow_override (F), as sent by host in 23045 * TCL Data Command: Beryllium 23046 * b'14:11 - ast_list_idx (AST) 23047 * Array index into the list of extension AST entries 23048 * (not the actual AST 16-bit index). 23049 * The ast_list_idx is one-based, with the following 23050 * range of values: 23051 * - legacy targets supporting 16 user-defined 23052 * MSDU queues: 1-2 23053 * - legacy targets supporting 48 user-defined 23054 * MSDU queues: 1-6 23055 * - new targets: 0 (peer_id is used instead) 23056 * Note that since ast_list_idx is one-based, 23057 * the host will need to subtract 1 to use it as an 23058 * index into a list of extension AST entries. 23059 * b'15:15 - reserved 23060 * b'23:16 - svc_class_id 23061 * b'31:24 - error_code 23062 * 23063 * dword2 - b'23:0 - tgt_opaque_msduq_id: tx flow number that uniquely 23064 * identifies the MSDU queue 23065 * b'24:31 - request_cookie: Identifies which H2T SDWF_MSDUQ_RECFG_REQ 23066 * request triggered this indication. 23067 * This will be set to HTT_MSDUQ_CFG_REG_COOKIE_INVALID 23068 * (0xFF) in any cases when the FW generates this 23069 * indication autonomously rather than in response to 23070 * a SDWF_MSDUQ_RECFG_REQ message from the host. 23071 * 23072 * The behavior of this indication is as follows: 23073 * - svc_class_id is set to the service class that the specified MSDUQ is 23074 * currently linked to. 23075 * - error_code is set to a defined code if any errors arise. 23076 * Otherwise a value of 0x00 (ERROR_NONE) indicates success. 23077 */ 23078 23079 /* HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND */ 23080 typedef enum { 23081 HTT_SDWF_MSDUQ_CFG_IND_ERROR_NONE = 0x00, 23082 HTT_SDWF_MSDUQ_CFG_IND_ERROR_PEER_DELETE_IN_PROG = 0x01, 23083 HTT_SDWF_MSDUQ_CFG_IND_ERROR_SW_MSDUQ_NULL = 0x02, 23084 HTT_SDWF_MSDUQ_CFG_IND_ERROR_MSDUQ_LOCATE_ERROR = 0x03, 23085 HTT_SDWF_MSDUQ_CFG_IND_ERROR_QPEER_NULL = 0x04, 23086 HTT_SDWF_MSDUQ_CFG_IND_ERROR_DEACTIVATED_MSDUQ = 0x05, 23087 HTT_SDWF_MSDUQ_CFG_IND_ERROR_REACTIVATED_MSDUQ = 0x06, 23088 HTT_SDWF_MSDUQ_CFG_IND_ERROR_INVALID_SVC_CLASS = 0x07, 23089 HTT_SDWF_MSDUQ_CFG_IND_ERROR_TIDQ_LOCATE_ERROR = 0x08, 23090 } HTT_SDWF_MSDUQ_CFG_IND_ERROR_CODE_E; 23091 23092 PREPACK struct htt_t2h_sdwf_msduq_cfg_ind { 23093 A_UINT32 msg_type: 8, /* bits 7:0 */ 23094 htt_qtype: 8, /* bits 15:8 */ 23095 peer_id: 16; /* bits 31:16 */ 23096 A_UINT32 remap_tid: 4, /* bits 3:0 */ 23097 hlos_tid: 4, /* bits 7:4 */ 23098 who_classify_info_sel: 2, /* bits 9:8 */ 23099 flow_override: 1, /* bits 10:10 */ 23100 ast_list_idx: 4, /* bits 14:11 */ 23101 reserved: 1, /* bits 15:15 */ 23102 svc_class_id: 8, /* bits 23:16 */ 23103 error_code: 8; /* bits 31:24 */ 23104 A_UINT32 tgt_opaque_msduq_id: 24, /* bits 23:0 */ 23105 request_cookie: 8; /* bits 31:24 */ 23106 } POSTPACK; 23107 23108 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_M 0x0000FF00 23109 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_S 8 23110 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_GET(_var) \ 23111 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_M) >> \ 23112 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_S) 23113 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_SET(_var, _val) \ 23114 do { \ 23115 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE, _val); \ 23116 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_S)); \ 23117 } while (0) 23118 23119 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_M 0xFFFF0000 23120 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_S 16 23121 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_GET(_var) \ 23122 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_M) >> \ 23123 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_S) 23124 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_SET(_var, _val) \ 23125 do { \ 23126 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID, _val); \ 23127 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_S)); \ 23128 } while (0) 23129 23130 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_M 0x0000000F 23131 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_S 0 23132 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_GET(_var) \ 23133 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_M) >> \ 23134 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_S) 23135 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_SET(_var, _val) \ 23136 do { \ 23137 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID, _val); \ 23138 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_S)); \ 23139 } while (0) 23140 23141 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_M 0x000000F0 23142 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_S 4 23143 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_GET(_var) \ 23144 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_M) >> \ 23145 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_S) 23146 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_SET(_var, _val) \ 23147 do { \ 23148 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID, _val); \ 23149 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_S)); \ 23150 } while (0) 23151 23152 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_M 0x00000300 23153 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_S 8 23154 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_GET(_var) \ 23155 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_M) >> \ 23156 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_S) 23157 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_SET(_var, _val) \ 23158 do { \ 23159 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO, _val); \ 23160 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_S)); \ 23161 } while (0) 23162 23163 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_M 0x00000400 23164 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_S 10 23165 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_GET(_var) \ 23166 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_M) >> \ 23167 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_S) 23168 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_SET(_var, _val) \ 23169 do { \ 23170 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE, _val); \ 23171 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_S)); \ 23172 } while (0) 23173 23174 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_M 0x00007800 23175 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_S 11 23176 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_GET(_var) \ 23177 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_M) >> \ 23178 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_S) 23179 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_SET(_var, _val) \ 23180 do { \ 23181 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX, _val); \ 23182 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_S)); \ 23183 } while (0) 23184 23185 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_M 0x00FF0000 23186 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_S 16 23187 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_GET(_var) \ 23188 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_M) >> \ 23189 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_S) 23190 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_SET(_var, _val) \ 23191 do { \ 23192 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID, _val); \ 23193 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_S)); \ 23194 } while (0) 23195 23196 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_M 0xFF000000 23197 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_S 24 23198 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_GET(_var) \ 23199 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_M) >> \ 23200 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_S) 23201 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_SET(_var, _val) \ 23202 do { \ 23203 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE, _val); \ 23204 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_S)); \ 23205 } while (0) 23206 23207 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_M 0x00FFFFFF 23208 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_S 0 23209 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_GET(_var) \ 23210 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_M) >> \ 23211 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_S) 23212 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_SET(_var, _val) \ 23213 do { \ 23214 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID, _val); \ 23215 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_S)); \ 23216 } while (0) 23217 23218 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_M 0xFF000000 23219 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_S 24 23220 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_GET(_var) \ 23221 (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_M) >> \ 23222 HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_S) 23223 #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_SET(_var, _val) \ 23224 do { \ 23225 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE, _val); \ 23226 ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_S)); \ 23227 } while (0) 23228 23229 23230 23231 #endif 23232